osc detector on H7 (#2992)
* detect clock with TIM11 instead of TIM5 * s * h7 has a different register name * detect on H7 * cleanup * comment * use define * f4 typo
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Matthew Kennedy
GitHub
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d1941aa38e
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@ -22,12 +22,18 @@
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float hseFrequencyMhz;
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uint8_t autoDetectedRoundedMhz;
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#ifdef STM32H7XX
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#define TIMER TIM17
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#else // not H7
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#define TIMER TIM11
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#endif
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static uint32_t getOneCapture() {
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// wait for input capture
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while ((TIM11->SR & TIM_SR_CC1IF) == 0);
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while ((TIMER->SR & TIM_SR_CC1IF) == 0);
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// Return captured count
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return TIM11->CCR1;
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return TIMER->CCR1;
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}
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static uint32_t getTimerCounts(size_t count) {
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@ -45,14 +51,64 @@ static uint32_t getTimerCounts(size_t count) {
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return lastCapture - firstCapture;
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}
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// This only works if you're using the PLL as the configured clock source!
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static_assert(STM32_SW == RCC_CFGR_SW_PLL);
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// These clocks must all be enabled for this to work
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static_assert(STM32_HSI_ENABLED);
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static_assert(STM32_HSE_ENABLED);
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static void reprogramPll(uint8_t roundedMhz) {
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#ifdef STM32H7XX
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static constexpr float rtcpreDivider = 63;
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static void enableTimer() {
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RCC->APB2ENR |= RCC_APB2ENR_TIM17EN;
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}
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static void disableTimer() {
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RCC->APB2ENR &= RCC_APB2ENR_TIM17EN;
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}
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static void reprogramPll(uint8_t roundedHseMhz) {
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// Switch system clock to HSI to configure PLL (SW = 0)
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RCC->CFGR &= ~RCC_CFGR_SW;
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// Stop all 3 PLLs
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RCC->CR &= ~(RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
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// H7 is configured for 2MHz input to PLL
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auto pllm = roundedHseMhz / 2;
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// Set PLLM for all 3 PLLs to the new value, and select HSE as the clock source
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RCC->PLLCKSELR =
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pllm << RCC_PLLCKSELR_DIVM1_Pos |
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pllm << RCC_PLLCKSELR_DIVM2_Pos |
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pllm << RCC_PLLCKSELR_DIVM3_Pos |
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RCC_PLLCKSELR_PLLSRC_HSE;
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// Enable PLLs
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RCC->CR |= RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON;
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// Wait for PLLs to lock
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auto readyMask = RCC_CR_PLL1RDY | RCC_CR_PLL2RDY | RCC_CR_PLL3RDY;
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while ((RCC->CR & readyMask) != readyMask) ;
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// Switch system clock source back to PLL
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RCC->CFGR |= RCC_CFGR_SW_PLL1;
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}
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#else // not STM32H7
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static constexpr float rtcpreDivider = 31;
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// This only works if you're using the PLL as the configured clock source!
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static_assert(STM32_SW == RCC_CFGR_SW_PLL);
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static void enableTimer() {
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RCC->APB2ENR |= RCC_APB2ENR_TIM11EN;
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}
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static void disableTimer() {
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM11EN;
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}
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static void reprogramPll(uint8_t roundedHseMhz) {
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// Switch back to HSI to configure PLL
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// clear SW to use HSI
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RCC->CFGR &= ~RCC_CFGR_SW;
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@ -64,7 +120,7 @@ static void reprogramPll(uint8_t roundedMhz) {
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RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLM_Msk | RCC_PLLCFGR_PLLSRC_Msk);
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// Stick in the new PLLM value
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RCC->PLLCFGR |= (roundedMhz << RCC_PLLCFGR_PLLM_Pos) & RCC_PLLCFGR_PLLM_Msk;
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RCC->PLLCFGR |= (roundedHseMhz << RCC_PLLCFGR_PLLM_Pos) & RCC_PLLCFGR_PLLM_Msk;
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// Set PLLSRC to HSE
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RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
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@ -77,37 +133,41 @@ static void reprogramPll(uint8_t roundedMhz) {
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2));
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}
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#endif
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// __late_init runs after bss/zero initialziation, but before static constructors and main
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extern "C" void __late_init() {
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// Set RTCPRE to /31 - just set all the bits
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RCC->CFGR |= RCC_CFGR_RTCPRE_Msk;
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// Turn on timer 11
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RCC->APB2ENR |= RCC_APB2ENR_TIM11EN;
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// Turn on timer
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enableTimer();
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// Remap to connect HSERTC to TIM11 CH1
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#ifdef STM32F4XX
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TIM11->OR = TIM_OR_TI1_RMP_1;
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// Remap to connect HSERTC to CH1
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#ifdef STM32H7XX
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// TI1SEL = 2, HSE_1MHz
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TIMER->TISEL = TIM_TISEL_TI1SEL_1;
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#elif defined(STM32F4XX)
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TIMER->OR = TIM_OR_TI1_RMP_1;
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#else
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// the definition has a different name on F7 for whatever reason
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TIM11->OR = TIM11_OR_TI1_RMP_1;
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TIMER->OR = TIM11_OR_TI1_RMP_1;
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#endif
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// Enable capture on channel 1
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TIM11->CCMR1 = TIM_CCMR1_CC1S_0;
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TIM11->CCER = TIM_CCER_CC1E;
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TIMER->CCMR1 = TIM_CCMR1_CC1S_0;
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TIMER->CCER = TIM_CCER_CC1E;
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// Start TIM11
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TIM11->CR1 |= TIM_CR1_CEN;
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// Start timer
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TIMER->CR1 |= TIM_CR1_CEN;
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// Measure HSE against SYSCLK
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auto hseCounts = getTimerCounts(10);
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// Turn off timer 11 now that we're done with it
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RCC->APB2ENR &= ~RCC_APB2ENR_TIM11EN;
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// Turn off timer now that we're done with it
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disableTimer();
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float hseFrequencyHz = 10 * 31.0f * STM32_SYSCLK / hseCounts;
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float hseFrequencyHz = 10 * rtcpreDivider * STM32_TIMCLK2 / hseCounts;
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hseFrequencyMhz = hseFrequencyHz / 1e6;
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autoDetectedRoundedMhz = efiRound(hseFrequencyMhz, 1);
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@ -80,14 +80,18 @@
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/*
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* PLLs static settings.
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* Reading STM32 Reference Manual is required.
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*
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* Configured to use HSI to generate 400mhz, but we will reconfigure to use HSE
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* with appropriate PLLx_DIVM values for the detected external frequency.
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* See osc_detector.cpp
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*/
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#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
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#define STM32_PLLSRC STM32_PLLSRC_HSI_CK
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#define STM32_PLLCFGR_MASK ~0
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#define STM32_PLL1_ENABLED TRUE
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#define STM32_PLL1_P_ENABLED TRUE
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#define STM32_PLL1_Q_ENABLED TRUE
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#define STM32_PLL1_R_ENABLED TRUE
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#define STM32_PLL1_DIVM_VALUE 4
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#define STM32_PLL1_DIVM_VALUE 32
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#define STM32_PLL1_DIVN_VALUE 400
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#define STM32_PLL1_FRACN_VALUE 0
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#define STM32_PLL1_DIVP_VALUE 2
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@ -97,7 +101,7 @@
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#define STM32_PLL2_P_ENABLED TRUE
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#define STM32_PLL2_Q_ENABLED TRUE
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#define STM32_PLL2_R_ENABLED TRUE
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#define STM32_PLL2_DIVM_VALUE 4
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#define STM32_PLL2_DIVM_VALUE 32
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#define STM32_PLL2_DIVN_VALUE 480
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#define STM32_PLL2_FRACN_VALUE 0
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#define STM32_PLL2_DIVP_VALUE 10
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@ -107,7 +111,7 @@
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#define STM32_PLL3_P_ENABLED TRUE
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#define STM32_PLL3_Q_ENABLED TRUE
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#define STM32_PLL3_R_ENABLED TRUE
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#define STM32_PLL3_DIVM_VALUE 4
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#define STM32_PLL3_DIVM_VALUE 32
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#define STM32_PLL3_DIVN_VALUE 480
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#define STM32_PLL3_FRACN_VALUE 0
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#define STM32_PLL3_DIVP_VALUE 2
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@ -485,6 +489,8 @@
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#define STM32_SYSCLK STM32_SYS_CK
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#define ENABLE_AUTO_DETECT_HSE
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/* common for all STM32 */
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#include "../../cfg/mcuconf_community.h"
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