andreika-git
/
rusefi
mirror of https://github.com/andreika-git/rusefi.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Start on HSI clock (#2957) 

* chibios uses HSI

* set pll to use HSE

* simplify capture

* even better logging

* string

Co-authored-by: Matthew Kennedy <makenne@microsoft.com>
This commit is contained in:
Matthew Kennedy 2021-07-14 12:20:38 -07:00 committed by GitHub
parent c36fdc15a5
commit d475b4721f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 20 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
firmware/console/eficonsole.cpp
View File

@ -43,8 +43,9 @@ static void sayHello(void) {
efiPrintf(PROTOCOL_HELLO_PREFIX " COMPILER=%s", __VERSION__);
#ifdef ENABLE_AUTO_DETECT_HSE
extern float hseFrequencyMhz;
extern uint8_t autoDetectedPllMValue;
efiPrintf(PROTOCOL_HELLO_PREFIX " autoDetectedPllMValue=%d", autoDetectedPllMValue);
efiPrintf(PROTOCOL_HELLO_PREFIX " detected HSE clock %.2f MHz, PLLM = %d", hseFrequencyMhz, autoDetectedPllMValue);
#endif /* ENABLE_AUTO_DETECT_HSE */
#if defined(STM32F4) || defined(STM32F7)

8
firmware/hw_layer/ports/stm32/mcuconf_common_f4_f7.h
View File

@ -324,11 +324,9 @@
*/
#define STM32_WDG_USE_IWDG FALSE
// We auto detect the value of HSE, so set the default PLLM value to the maximum,
// so we don't accidentially overclock to processor before we know how fast HSE is
#define STM32_PLLM_VALUE 25
// This also means we have to pretend (for now) we have a 25MHz HSE fitted
// Pretend we have a 25MHz external crystal. This value isn't actually used since we
// configure the PLL to start on the HSI oscillator, then compute HSE's speed at runtime
// and reconfigure the PLL appropriately.
#define STM32_HSECLK 25000000
// After boot, we will detect the real frequency, and adjust the PLL M value to suit

20
firmware/hw_layer/ports/stm32/osc_detector.cpp
View File

@ -19,6 +19,7 @@
#ifdef ENABLE_AUTO_DETECT_HSE
float hseFrequencyMhz;
uint8_t autoDetectedPllMValue;
static void useHsi() {
@ -50,17 +51,15 @@ static uint32_t getAverageLsiCounts() {
// Burn one count
getOneCapture();
uint32_t lastCapture = getOneCapture();
uint32_t sum = 0;
uint32_t firstCapture = getOneCapture();
uint32_t lastCapture;
for (size_t i = 0; i < 20; i++)
{
auto capture = getOneCapture();
sum += (capture - lastCapture);
lastCapture = capture;
lastCapture = getOneCapture();
}
return sum;
return lastCapture - firstCapture;
}
// This only works if you're using the PLL as the configured clock source!
@ -78,11 +77,13 @@ static void reprogramPll(uint8_t pllM) {
// Stop the PLL
RCC->CR &= ~RCC_CR_PLLON;
// Mask out the old PLLM val
RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLM_Msk;
// Mask out the old PLLM and PLLSRC
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLM_Msk | RCC_PLLCFGR_PLLSRC_Msk);
// Stick in the new PLLM value
RCC->PLLCFGR |= (pllM << RCC_PLLCFGR_PLLM_Pos) & RCC_PLLCFGR_PLLM_Msk;
// Set PLLSRC to HSE
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE;
// Reenable PLL, wait for lock
RCC->CR |= RCC_CR_PLLON;
@ -122,8 +123,9 @@ extern "C" void __late_init() {
RCC->APB1ENR &= ~RCC_APB1ENR_TIM5EN;
// The external clocks's frequency is the ratio of the measured LSI speed, times HSI's speed (16MHz)
float hseFrequencyMhz = 16.0f * hseCounts / hsiCounts;
constexpr float hsiMhz = STM32_HSICLK * 1e-6;
hseFrequencyMhz = hsiMhz * hseCounts / hsiCounts;
autoDetectedPllMValue = efiRound(hseFrequencyMhz, 1);
reprogramPll(autoDetectedPllMValue);

4
firmware/hw_layer/ports/stm32/stm32f4/cfg/mcuconf.h
View File

@ -51,8 +51,8 @@
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLM_VALUE 16
#define STM32_PLLN_VALUE 336
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 7

3
firmware/hw_layer/ports/stm32/stm32f7/cfg/mcuconf.h
View File

@ -72,7 +72,8 @@
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLSRC STM32_PLLSRC_HSI
#define STM32_PLLM_VALUE 16
#define STM32_PLLN_VALUE 432
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 9