gpio: tle9104: codestyle align with other gpio drivers
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@ -4,6 +4,20 @@
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#if defined(BOARD_TLE9104_COUNT) && BOARD_TLE9104_COUNT > 0
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/*
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* TODO list:
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* - support driving outputs over SPI
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* - count communication errors, POR events, etc
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* - support WD functionality
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* - implement direct-io mapping test. Check if user provides correct direct_io data
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*/
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/*==========================================================================*/
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/* Driver local definitions. */
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/*==========================================================================*/
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#define DRIVER_NAME "tle9104"
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/* IN MOSI and MISO a read is defined with a s0 and a write is defined with a 1. */
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#define TLE9104_WR_REG(addr, val) ((((addr) & 0x0f) << 8) | ((val) & 0xff))
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#define TLE9104_RD_REG(addr) (BIT(15) | (((addr) & 0x0f) << 8))
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@ -21,6 +35,14 @@
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#define TLE9104_REG_GLOBAL_STATUS 0x07
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#define TLE9104_REG_ICVID 0x08
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/*==========================================================================*/
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/* Driver exported variables. */
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/*==========================================================================*/
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/*==========================================================================*/
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/* Driver local variables and types. */
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/*==========================================================================*/
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struct Tle9104 : public GpioChip {
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int init() override;
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@ -45,6 +67,12 @@ private:
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uint8_t diag_on34;
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};
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static Tle9104 chips[BOARD_TLE9104_COUNT];
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/*==========================================================================*/
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/* Driver local functions. */
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/*==========================================================================*/
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static bool parityBit(uint16_t val) {
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// (1 + number of bits set) mod 2 = parity bit
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int count = 1;
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@ -148,17 +176,22 @@ int Tle9104::chip_init() {
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return 0;
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}
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/*==========================================================================*/
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/* Driver exported functions. */
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/*==========================================================================*/
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int Tle9104::init() {
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int ret;
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m_resn.initPin("TLE9104 RESN", cfg->resn);
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m_en.initPin("TLE9104 EN", cfg->en);
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m_resn.initPin(DRIVER_NAME " RESN", cfg->resn);
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m_en.initPin(DRIVER_NAME " EN", cfg->en);
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// disable outputs
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m_en.setValue(false);
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/* TODO: ensure all direct_io pins valid, otherwise support manipulationg output states over SPI */
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for (int i = 0; i < 4; i++) {
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gpio_pin_markUsed(cfg->direct_io[i].port, cfg->direct_io[i].pad, "TLE9104 Direct IO");
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gpio_pin_markUsed(cfg->direct_io[i].port, cfg->direct_io[i].pad, DRIVER_NAME " Direct IO");
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palSetPadMode(cfg->direct_io[i].port, cfg->direct_io[i].pad, PAL_MODE_OUTPUT_PUSHPULL);
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// Ensure all outputs are off
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@ -301,8 +334,6 @@ brain_pin_diag_e Tle9104::getDiag(size_t pin) {
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return (brain_pin_diag_e)result;
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}
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static Tle9104 chips[BOARD_TLE9104_COUNT];
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int tle9104_add(Gpio base, int index, const tle9104_config* cfg) {
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Tle9104& chip = chips[index];
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@ -313,7 +344,7 @@ int tle9104_add(Gpio base, int index, const tle9104_config* cfg) {
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chip.cfg = cfg;
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return gpiochip_register(base, "TLE9104", chip, 4);
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return gpiochip_register(base, DRIVER_NAME, chip, 4);
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}
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void updatetlediag() {
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