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This commit is contained in:
rusEfi 2014-12-26 07:04:06 -06:00
parent 41f5690a1e
commit d5c5a4edb5
11 changed files with 1527 additions and 393 deletions
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hardware/DDPAK_breakout/DDPAK_breakout.kicad_pcb
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@ -3,10 +3,10 @@
(general
(links 11)
(no_connects 0)
(area 200.225429 155.709477 231.089201 180.234166)
(area 188.850001 145.740001 231.089201 181.229)
(thickness 1.6)
(drawings 13)
(tracks 188)
(drawings 14)
(tracks 134)
(zones 0)
(modules 6)
(nets 5)
@ -15,7 +15,7 @@
(page A)
(title_block
(title "DDPAK breakout")
(rev R0.1)
(rev R0.2)
(company rusEFI)
)
@ -49,6 +49,8 @@
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(user_via 0.889 0.635)
(user_via 1.54178 1.18618)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
@ -87,7 +89,7 @@
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(drillshape 0)
(scaleselection 1)
(outputdirectory ""))
)
@ -131,13 +133,13 @@
)
(module SM0805_jumper (layer F.Cu) (tedit 53B680BA) (tstamp 544A797B)
(at 221.742 176.784 180)
(at 206.375 171.45 90)
(path /54499D02)
(attr smd)
(fp_text reference R1 (at 0.0635 0 270) (layer F.SilkS)
(fp_text reference R1 (at 0.0635 0 180) (layer F.SilkS)
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(fp_text value 1K (at 0 1.27 180) (layer F.SilkS) hide
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@ -147,27 +149,27 @@
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(pad 2 smd rect (at 1.27 0 180) (size 1.524 0.2032)
(pad 2 smd rect (at 1.27 0 90) (size 1.524 0.2032)
(layers F.Cu F.Paste F.Mask)
(net 4 /SIG2)
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(pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397)
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(pad 2 thru_hole circle (at 1.905 0 90) (size 1.524 1.524) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 4 /SIG2)
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(pad 1 thru_hole circle (at -1.905 0 180) (size 1.524 1.524) (drill 0.8128)
(pad 1 thru_hole circle (at -1.905 0 90) (size 1.524 1.524) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 3 /SIG)
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(pad 1 smd rect (at -1.27 0 90) (size 1.524 0.2032)
(layers F.Cu F.Paste F.Mask)
(net 3 /SIG)
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@ -178,55 +180,13 @@
)
)
(module DPAK2 (layer F.Cu) (tedit 5449A3A9) (tstamp 5449C06D)
(at 212.09 168.91)
(descr "MOS boitier DPACK G-D-S")
(tags "CMD DPACK")
(path /54499B8E)
(attr smd)
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(pad 1 smd rect (at -2.286 0) (size 1.651 3.048)
(layers F.Cu F.Paste F.Mask)
(net 4 /SIG2)
)
(pad 2 smd rect (at 0 -6.35) (size 6.096 6.096)
(layers F.Cu F.Paste F.Mask)
(net 2 /HV)
)
(pad 3 smd rect (at 2.286 0) (size 1.651 3.048)
(layers F.Cu F.Paste F.Mask)
(net 1 /GND)
)
(model smd/dpack_2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module AK300-2 (layer F.Cu) (tedit 544A157D) (tstamp 544A2601)
(module AK300-2 (layer F.Cu) (tedit 549D4368) (tstamp 544A2601)
(at 222.25 166.878 270)
(descr CONNECTOR)
(tags CONNECTOR)
(path /5449A1BA)
(attr virtual)
(fp_text reference P2 (at 2.54 5.08 270) (layer F.SilkS)
(fp_text reference P2 (at 0.127 6.985 270) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)))
)
(fp_text value CONN_2 (at 0.254 7.747 270) (layer F.SilkS) hide
@ -324,7 +284,7 @@
)
(module SM2010 (layer F.Cu) (tedit 544A1B10) (tstamp 5449C04A)
(at 212.09 172.212)
(at 210.82 174.625)
(tags "CMS SM")
(path /54499C42)
(attr smd)
@ -356,12 +316,12 @@
)
)
(module SIL-1 (layer F.Cu) (tedit 544A1D71) (tstamp 544A798F)
(at 216.916 172.72)
(module SIL-1 (layer F.Cu) (tedit 549D3F21) (tstamp 544A798F)
(at 215.265 175.26)
(descr "Connecteurs 1 pin")
(tags "CONN DEV")
(path /544A1CD8)
(fp_text reference P3 (at 0 2.286) (layer F.SilkS)
(fp_text reference P3 (at 1.905 0.635) (layer F.SilkS)
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)
(fp_text value CONN_1 (at 0 -2.54) (layer F.SilkS) hide
@ -377,12 +337,12 @@
)
)
(module SIL-1 (layer F.Cu) (tedit 544A1F68) (tstamp 544A7985)
(at 223.266 173.736 180)
(module SIL-1 (layer F.Cu) (tedit 549D4054) (tstamp 544A7985)
(at 206.375 175.26 180)
(descr "Connecteurs 1 pin")
(tags "CONN DEV")
(path /544A1CBF)
(fp_text reference P1 (at 2.54 -1.27 180) (layer F.SilkS)
(fp_text reference P1 (at -4.445 -0.635 180) (layer F.SilkS)
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(fp_text value CONN_1 (at 0 -2.54 180) (layer F.SilkS) hide
@ -398,218 +358,269 @@
)
)
(gr_text "HV 600+" (at 220.472 162.814) (layer B.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)) (justify mirror))
(module m-pad-2.1-TO-263AB (layer F.Cu) (tedit 549D3FB2) (tstamp 5449C06D)
(at 210.82 160.655)
(descr "FAIRCHILD'S TO-263AB/D2PAK PACKAGE DIMENSIONS")
(tags "FAIRCHILD'S TO-263AB/D2PAK PACKAGE DIMENSIONS")
(path /5498B4BA)
(attr smd)
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(xy 214.501796 173.350443) (xy 214.501664 173.198872) (xy 214.443538 173.058889) (xy 214.336267 172.951806) (xy 214.317392 172.944007)
(xy 214.391468 172.870061) (xy 214.449594 172.730078) (xy 214.449726 172.578507) (xy 214.44966 171.13123) (xy 214.35441 171.03598)
(xy 213.69401 171.03598) (xy 213.69401 172.89653) (xy 213.6013 172.98924) (xy 213.6013 174.244) (xy 213.6213 174.244)
(xy 213.6213 175.006) (xy 213.6013 175.006) (xy 213.6013 175.026) (xy 212.852 175.026) (xy 212.852 173.03242)
(xy 212.94471 172.93971) (xy 212.94471 171.03598) (xy 212.91836 171.03598) (xy 212.91836 170.27398) (xy 212.94471 170.27398)
(xy 212.94471 170.25398) (xy 213.69401 170.25398) (xy 213.69401 170.27398) (xy 214.35441 170.27398) (xy 214.44966 170.17873)
(xy 214.449712 169.037) (xy 222.651 169.037) (xy 222.651 169.7482) (xy 222.631 169.7482) (xy 222.631 170.7388)
(xy 223.6216 170.7388) (xy 224.117487 170.488591) (xy 224.359 170.208062) (xy 224.359 176.099)
)
)
)
(zone (net 2) (net_name /HV) (layer F.Cu) (tstamp 549D413C) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill (arc_segments 16) (thermal_gap 0.254) (thermal_bridge_width 1.016) (smoothing fillet) (radius 0.762))
(polygon
(pts
(xy 227.33 165.1) (xy 227.33 151.13) (xy 201.93 151.13) (xy 201.93 165.1)
)
)
(filled_polygon
(pts
(xy 224.359 163.522537) (xy 224.117487 163.242009) (xy 223.6216 162.9918) (xy 222.631 162.9918) (xy 222.631 163.9824)
(xy 222.651 163.9824) (xy 222.651 164.7444) (xy 222.631 164.7444) (xy 222.631 164.7644) (xy 221.869 164.7644)
(xy 221.869 164.7444) (xy 221.869 163.9824) (xy 221.869 162.9918) (xy 220.8784 162.9918) (xy 220.382513 163.242009)
(xy 220.020124 163.66294) (xy 220.017603 163.780969) (xy 220.041243 163.9824) (xy 221.869 163.9824) (xy 221.869 164.7444)
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)
)

66
hardware/DDPAK_breakout/DDPAK_breakout.net
View File

@ -1,15 +1,9 @@
(export (version D)
(design
(source C:\Users\LJ\Desktop\Jared\daecu\Hardware\trunk\rusefi.com\DDPAK_breakout\DDPAK_breakout.sch)
(date "10/24/2014 5:34:36 AM")
(source C:/Users/LJ/Desktop/Jared/daecu/Hardware/trunk/rusefi.com/DDPAK_breakout/DDPAK_breakout.sch)
(date "12/26/2014 5:37:57 AM")
(tool "eeschema (2013-07-07 BZR 4022)-stable"))
(components
(comp (ref Q1)
(value IRGS14C40L)
(footprint DPAK2)
(libsource (lib project_specific_libs) (part IRGS14C40L))
(sheetpath (names /) (tstamps /))
(tstamp 54499B8E))
(comp (ref R2)
(value 100K)
(footprint SM2010)
@ -39,7 +33,13 @@
(footprint SIL-1)
(libsource (lib conn) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 544A1CD8)))
(tstamp 544A1CD8))
(comp (ref Q1)
(value IRGS14C40L)
(footprint m-pad-2.1-TO-263AB)
(libsource (lib transistors) (part TIP121))
(sheetpath (names /) (tstamps /))
(tstamp 5498B4BA)))
(libparts
(libpart (lib device) (part R)
(description Resistance)
@ -57,6 +57,20 @@
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib transistors) (part TIP120)
(description "TIP120, 5A Ic, 60V Vce, Silicon Darlington Power Transistor NPN")
(docs http://www.fairchildsemi.com/ds/TI/TIP120.pdf)
(footprints
(fp TO220*))
(fields
(field (name Reference) Q)
(field (name Value) TIP120)
(field (name Footprint) TO220)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name B) (type input))
(pin (num 2) (name C) (type passive))
(pin (num 3) (name E) (type passive))))
(libpart (lib conn) (part CONN_1)
(description "1 pin")
(fields
@ -71,26 +85,14 @@
(field (name Value) CONN_2))
(pins
(pin (num 1) (name P1) (type passive))
(pin (num 2) (name PM) (type passive))))
(libpart (lib project_specific_libs) (part IRGS14C40L)
(footprints
(fp DPAK2))
(fields
(field (name Reference) Q)
(field (name Value) IRGS14C40L)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name G) (type input))
(pin (num 2) (name C) (type passive))
(pin (num 3) (name E) (type passive)))))
(pin (num 2) (name PM) (type passive)))))
(libraries
(library (logical transistors)
(uri "C:\\Program Files\\KiCad\\share\\library\\transistors.lib"))
(library (logical device)
(uri "C:\\Program Files\\KiCad\\share\\library\\device.lib"))
(library (logical conn)
(uri "C:\\Program Files\\KiCad\\share\\library\\conn.lib"))
(library (logical project_specific_libs)
(uri ..\rusefi_lib\project_specific_libs.lib)))
(uri "C:\\Program Files\\KiCad\\share\\library\\conn.lib")))
(nets
(net (code 1) (name /HV)
(node (ref P2) (pin 1))
@ -98,12 +100,12 @@
(net (code 2) (name /SIG)
(node (ref P1) (pin 1))
(node (ref R1) (pin 1)))
(net (code 3) (name /GND)
(node (ref Q1) (pin 3))
(net (code 3) (name /SIG2)
(node (ref R1) (pin 2))
(node (ref Q1) (pin 1))
(node (ref R2) (pin 1)))
(net (code 4) (name /GND)
(node (ref R2) (pin 2))
(node (ref P2) (pin 2))
(node (ref P3) (pin 1)))
(net (code 4) (name /SIG2)
(node (ref Q1) (pin 1))
(node (ref R1) (pin 2))
(node (ref R2) (pin 1)))))
(node (ref P3) (pin 1))
(node (ref Q1) (pin 3)))))

84
hardware/DDPAK_breakout/DDPAK_breakout.pro
View File

@ -1,45 +1,5 @@
update=12/22/2014 5:52:52 AM
last_client=pcbnew
[eeschema]
version=1
LibDir=../rusefi_lib
NetFmtName=
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=project_specific_libs
update=12/26/2014 6:49:06 AM
last_client=eeschema
[cvpcb]
version=1
NetIExt=net
@ -83,3 +43,43 @@ LibName14=dip_sockets
LibName15=pga_sockets
LibName16=valves
LibName17=SM0805-Jumper
LibName18=d2pak_TO263AB
[eeschema]
version=1
LibDir=../rusefi_lib
NetFmtName=PcbnewAdvanced
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves

34
hardware/DDPAK_breakout/DDPAK_breakout.sch
View File

@ -29,15 +29,15 @@ LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:project_specific_libs
LIBS:DDPAK_breakout-cache
EELAYER 27 0
EELAYER END
$Descr A 11000 8500
encoding utf-8
Sheet 1 1
Title "DDPAK breakout"
Date "24 oct 2014"
Rev "R0.1"
Date "26 dec 2014"
Rev "R0.2"
Comp "rusEFI"
Comment1 ""
Comment2 ""
@ -45,17 +45,6 @@ Comment3 ""
Comment4 ""
$EndDescr
$Comp
L IRGS14C40L Q1
U 1 1 54499B8E
P 6550 4100
F 0 "Q1" H 6453 4350 70 0000 C CNN
F 1 "IRGS14C40L" H 6350 3900 60 0001 C CNN
F 2 "DPAK2" H 6550 4100 60 0001 C CNN
F 3 "~" H 6550 4100 60 0000 C CNN
1 6550 4100
1 0 0 -1
$EndComp
$Comp
L R R2
U 1 1 54499C42
P 5900 4350
@ -78,10 +67,10 @@ F 3 "~" H 5600 4100 30 0000 C CNN
0 -1 -1 0
$EndComp
Wire Wire Line
5850 4100 6350 4100
5850 4100 6450 4100
Connection ~ 5900 4100
Wire Wire Line
6750 4350 6750 4600
6750 4300 6750 4600
Connection ~ 6750 4600
$Comp
L CONN_2 P2
@ -131,4 +120,17 @@ Text Label 6750 3850 0 60 ~ 0
HV
Text Label 6000 4100 0 60 ~ 0
SIG2
$Comp
L TIP121 Q1
U 1 1 5498B4BA
P 6650 4100
F 0 "Q1" H 6600 3950 40 0000 R CNN
F 1 "IRGS14C40L" H 6650 4250 40 0001 R CNN
F 2 "m-pad-2.1-TO-263AB" H 6530 4205 29 0001 C CNN
F 3 "~" H 6650 4100 60 0000 C CNN
1 6650 4100
1 0 0 -1
$EndComp
Wire Wire Line
6750 3850 6750 3900
$EndSCHEMATC

7
hardware/DDPAK_breakout/known_issues.txt
View File

@ -1,4 +1,3 @@
1) support both DPAK and DDPAk
2) larger diameter vias
3) remove screw-in terminal
4) breakboard approach
1) RESOLVED IN R0.2 DPAK2 is apparently different than D2PAK, now it uses TO-263AB
2) RESOLVED IN R0.2 Make vias under large GND pad larger to allow more heat form iron during soldering
3) RESOLVED IN R0.2 move Via's to PCB edge to allow install on proto area of Frankenso

667
hardware/DPAK2_breakout/DPAK2_breakout.kicad_pcb Normal file
View File

@ -0,0 +1,667 @@
(kicad_pcb (version 3) (host pcbnew "(2013-07-07 BZR 4022)-stable")
(general
(links 11)
(no_connects 0)
(area 200.225429 155.709477 231.089201 180.234166)
(thickness 1.6)
(drawings 13)
(tracks 188)
(zones 0)
(modules 6)
(nets 5)
)
(page A)
(title_block
(title "DDPAK breakout")
(rev R0.1)
(company rusEFI)
)
(layers
(15 F.Cu signal)
(0 B.Cu signal)
(16 B.Adhes user)
(17 F.Adhes user)
(18 B.Paste user)
(19 F.Paste user)
(20 B.SilkS user)
(21 F.SilkS user)
(22 B.Mask user)
(23 F.Mask user)
(24 Dwgs.User user)
(25 Cmts.User user)
(26 Eco1.User user)
(27 Eco2.User user)
(28 Edge.Cuts user)
)
(setup
(last_trace_width 0.3048)
(trace_clearance 0.3048)
(zone_clearance 0.254)
(zone_45_only no)
(trace_min 0.254)
(segment_width 0.2)
(edge_width 0.1)
(via_size 0.889)
(via_drill 0.635)
(via_min_size 0.889)
(via_min_drill 0.508)
(uvia_size 0.508)
(uvia_drill 0.127)
(uvias_allowed no)
(uvia_min_size 0.508)
(uvia_min_drill 0.127)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.5 1.5)
(pad_drill 0.6)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements 7FFFFF3F)
(pcbplotparams
(layerselection 3178497)
(usegerberextensions true)
(excludeedgelayer true)
(linewidth 0.150000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotothertext true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 /GND)
(net 2 /HV)
(net 3 /SIG)
(net 4 /SIG2)
(net_class Default "This is the default net class."
(clearance 0.3048)
(trace_width 0.3048)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net "")
(add_net /GND)
(add_net /HV)
(add_net /SIG)
(add_net /SIG2)
)
(net_class FAT ""
(clearance 1.7526)
(trace_width 2.54)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
)
(net_class MIN ""
(clearance 2.54)
(trace_width 0.3048)
(via_dia 0.889)
(via_drill 0.635)
(uvia_dia 0.508)
(uvia_drill 0.127)
)
(module SM0805_jumper (layer F.Cu) (tedit 53B680BA) (tstamp 544A797B)
(at 221.742 176.784 180)
(path /54499D02)
(attr smd)
(fp_text reference R1 (at 0.0635 0 270) (layer F.SilkS)
(effects (font (size 0.762 0.762) (thickness 0.127)))
)
(fp_text value 1K (at 0 1.27 180) (layer F.SilkS) hide
(effects (font (size 0.50038 0.50038) (thickness 0.10922)))
)
(fp_circle (center -1.651 0.762) (end -1.651 0.635) (layer F.SilkS) (width 0.09906))
(fp_line (start -0.508 0.762) (end -1.524 0.762) (layer F.SilkS) (width 0.09906))
(fp_line (start -1.524 0.762) (end -1.524 -0.762) (layer F.SilkS) (width 0.09906))
(fp_line (start -1.524 -0.762) (end -0.508 -0.762) (layer F.SilkS) (width 0.09906))
(fp_line (start 0.508 -0.762) (end 1.524 -0.762) (layer F.SilkS) (width 0.09906))
(fp_line (start 1.524 -0.762) (end 1.524 0.762) (layer F.SilkS) (width 0.09906))
(fp_line (start 1.524 0.762) (end 0.508 0.762) (layer F.SilkS) (width 0.09906))
(pad 2 smd rect (at 1.27 0 180) (size 1.524 0.2032)
(layers F.Cu F.Paste F.Mask)
(net 4 /SIG2)
)
(pad 1 smd rect (at -0.9525 0 180) (size 0.889 1.397)
(layers F.Cu F.Paste F.Mask)
(net 3 /SIG)
)
(pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
(layers F.Cu F.Paste F.Mask)
(net 4 /SIG2)
)
(pad 2 thru_hole circle (at 1.905 0 180) (size 1.524 1.524) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 4 /SIG2)
)
(pad 1 thru_hole circle (at -1.905 0 180) (size 1.524 1.524) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 3 /SIG)
)
(pad 1 smd rect (at -1.27 0 180) (size 1.524 0.2032)
(layers F.Cu F.Paste F.Mask)
(net 3 /SIG)
)
(model smd/chip_cms.wrl
(at (xyz 0 0 0))
(scale (xyz 0.1 0.1 0.1))
(rotate (xyz 0 0 0))
)
)
(module DPAK2 (layer F.Cu) (tedit 5449A3A9) (tstamp 5449C06D)
(at 212.09 168.91)
(descr "MOS boitier DPACK G-D-S")
(tags "CMD DPACK")
(path /5498B4BA)
(attr smd)
(fp_text reference Q1 (at 0 0.635) (layer F.SilkS)
(effects (font (size 1.27 1.016) (thickness 0.2032)))
)
(fp_text value IRGS14C40L (at 0 -2.413) (layer F.SilkS) hide
(effects (font (size 1.016 1.016) (thickness 0.2032)))
)
(fp_line (start 1.397 -1.524) (end 1.397 1.651) (layer F.SilkS) (width 0.127))
(fp_line (start 1.397 1.651) (end 3.175 1.651) (layer F.SilkS) (width 0.127))
(fp_line (start 3.175 1.651) (end 3.175 -1.524) (layer F.SilkS) (width 0.127))
(fp_line (start -3.175 -1.524) (end -3.175 1.651) (layer F.SilkS) (width 0.127))
(fp_line (start -3.175 1.651) (end -1.397 1.651) (layer F.SilkS) (width 0.127))
(fp_line (start -1.397 1.651) (end -1.397 -1.524) (layer F.SilkS) (width 0.127))
(fp_line (start 3.429 -7.62) (end 3.429 -1.524) (layer F.SilkS) (width 0.127))
(fp_line (start 3.429 -1.524) (end -3.429 -1.524) (layer F.SilkS) (width 0.127))
(fp_line (start -3.429 -1.524) (end -3.429 -9.398) (layer F.SilkS) (width 0.127))
(fp_line (start -3.429 -9.525) (end 3.429 -9.525) (layer F.SilkS) (width 0.127))
(fp_line (start 3.429 -9.398) (end 3.429 -7.62) (layer F.SilkS) (width 0.127))
(pad 1 smd rect (at -2.286 0) (size 1.651 3.048)
(layers F.Cu F.Paste F.Mask)
(net 4 /SIG2)
)
(pad 2 smd rect (at 0 -6.35) (size 6.096 6.096)
(layers F.Cu F.Paste F.Mask)
(net 2 /HV)
)
(pad 3 smd rect (at 2.286 0) (size 1.651 3.048)
(layers F.Cu F.Paste F.Mask)
(net 1 /GND)
)
(model smd/dpack_2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module AK300-2 (layer F.Cu) (tedit 544A157D) (tstamp 544A2601)
(at 222.25 166.878 270)
(descr CONNECTOR)
(tags CONNECTOR)
(path /5449A1BA)
(attr virtual)
(fp_text reference P2 (at 2.54 5.08 270) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)))
)
(fp_text value CONN_2 (at 0.254 7.747 270) (layer F.SilkS) hide
(effects (font (size 1.778 1.778) (thickness 0.0889)))
)
(fp_line (start -3.7846 2.54) (end -1.2446 2.54) (layer F.SilkS) (width 0.06604))
(fp_line (start -1.2446 2.54) (end -1.2446 -0.254) (layer F.SilkS) (width 0.06604))
(fp_line (start -3.7846 -0.254) (end -1.2446 -0.254) (layer F.SilkS) (width 0.06604))
(fp_line (start -3.7846 2.54) (end -3.7846 -0.254) (layer F.SilkS) (width 0.06604))
(fp_line (start 1.2192 2.54) (end 3.7592 2.54) (layer F.SilkS) (width 0.06604))
(fp_line (start 3.7592 2.54) (end 3.7592 -0.254) (layer F.SilkS) (width 0.06604))
(fp_line (start 1.2192 -0.254) (end 3.7592 -0.254) (layer F.SilkS) (width 0.06604))
(fp_line (start 1.2192 2.54) (end 1.2192 -0.254) (layer F.SilkS) (width 0.06604))
(fp_line (start 5.08 -6.223) (end 5.08 -3.175) (layer F.SilkS) (width 0.1524))
(fp_line (start 5.08 -6.223) (end -5.08 -6.223) (layer F.SilkS) (width 0.1524))
(fp_line (start 5.08 -6.223) (end 5.588 -6.223) (layer F.SilkS) (width 0.1524))
(fp_line (start 5.588 -6.223) (end 5.588 -1.397) (layer F.SilkS) (width 0.1524))
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(fp_line (start 5.588 5.461) (end 5.08 5.207) (layer F.SilkS) (width 0.1524))
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(fp_arc (start 1.3462 -4.64566) (end 1.05664 -4.1275) (angle 104.2) (layer F.SilkS) (width 0.1524))
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(pad 1 thru_hole oval (at -2.5146 0 270) (size 1.9812 3.9624) (drill 1.3208)
(layers *.Cu F.Paste F.SilkS F.Mask)
(net 2 /HV)
)
(pad 2 thru_hole oval (at 2.4892 0 270) (size 1.9812 3.9624) (drill 1.3208)
(layers *.Cu F.Paste F.SilkS F.Mask)
(net 1 /GND)
)
)
(module SM2010 (layer F.Cu) (tedit 544A1B10) (tstamp 5449C04A)
(at 212.09 172.212)
(tags "CMS SM")
(path /54499C42)
(attr smd)
(fp_text reference R2 (at 0 0) (layer F.SilkS)
(effects (font (size 0.70104 0.70104) (thickness 0.127)))
)
(fp_text value 100K (at 0 0.8) (layer F.SilkS) hide
(effects (font (size 0.70104 0.70104) (thickness 0.127)))
)
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(pad 1 smd rect (at -2.4003 0) (size 1.80086 2.70002)
(layers F.Cu F.Paste F.Mask)
(net 4 /SIG2)
)
(pad 2 smd rect (at 2.4003 0) (size 1.80086 2.70002)
(layers F.Cu F.Paste F.Mask)
(net 1 /GND)
)
(model smd\chip_smd_pol_wide.wrl
(at (xyz 0 0 0))
(scale (xyz 0.35 0.35 0.35))
(rotate (xyz 0 0 0))
)
)
(module SIL-1 (layer F.Cu) (tedit 544A1D71) (tstamp 544A798F)
(at 216.916 172.72)
(descr "Connecteurs 1 pin")
(tags "CONN DEV")
(path /544A1CD8)
(fp_text reference P3 (at 0 2.286) (layer F.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)))
)
(fp_text value CONN_1 (at 0 -2.54) (layer F.SilkS) hide
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)
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(fp_line (start -1.27 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.3175))
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(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.3048))
(pad 1 thru_hole rect (at 0 0) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 1 /GND)
)
)
(module SIL-1 (layer F.Cu) (tedit 544A1F68) (tstamp 544A7985)
(at 223.266 173.736 180)
(descr "Connecteurs 1 pin")
(tags "CONN DEV")
(path /544A1CBF)
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)
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)
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(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.3048))
(pad 1 thru_hole rect (at 0 0 180) (size 1.397 1.397) (drill 0.8128)
(layers *.Cu *.Mask F.SilkS)
(net 3 /SIG)
)
)
(gr_text "HV 600+" (at 220.472 162.814) (layer B.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)) (justify mirror))
)
(gr_text SIG (at 221.488 176.276 90) (layer B.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)) (justify mirror))
)
(gr_text GND (at 219.202 171.45 90) (layer B.SilkS)
(effects (font (size 1.27 1.27) (thickness 0.127)) (justify mirror))
)
(gr_text "rusEFI by DAECU\nignition R0.1\nDDPAK breakout\n" (at 209.804 168.402 90) (layer B.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror))
)
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(gr_text "600V +" (at 220.345 160.02) (layer F.SilkS)
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)
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(segment (start 212.7504 164.4904) (end 213.7156 164.4904) (width 0.3048) (layer F.Cu) (net 2) (tstamp 544A7ACD))
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(segment (start 213.868 164.338) (end 212.09 162.56) (width 0.3048) (layer F.Cu) (net 2) (tstamp 544A7ACF))
(segment (start 224.155 159.385) (end 224.155 160.02) (width 0.3048) (layer F.Cu) (net 2))
(segment (start 224.155 160.02) (end 223.52 160.655) (width 0.3048) (layer F.Cu) (net 2) (tstamp 544A7A5F))
(via (at 223.52 160.655) (size 0.889) (layers F.Cu B.Cu) (net 2))
(segment (start 223.52 160.655) (end 222.25 160.655) (width 0.3048) (layer B.Cu) (net 2) (tstamp 544A7A61))
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(segment (start 215.265 161.925) (end 216.535 161.925) (width 0.3048) (layer F.Cu) (net 2) (tstamp 544A7A94))
(via (at 216.535 161.925) (size 0.889) (layers F.Cu B.Cu) (net 2))
(segment (start 216.535 161.925) (end 217.805 161.925) (width 0.3048) (layer B.Cu) (net 2) (tstamp 544A7A97))
(via (at 217.805 161.925) (size 0.889) (layers F.Cu B.Cu) (net 2))
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(via (at 219.075 161.925) (size 0.889) (layers F.Cu B.Cu) (net 2))
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(via (at 220.345 161.925) (size 0.889) (layers F.Cu B.Cu) (net 2))
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(via (at 221.615 161.925) (size 0.889) (layers F.Cu B.Cu) (net 2))
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(via (at 220.345 159.385) (size 0.889) (layers F.Cu B.Cu) (net 2))
(segment (start 219.075 159.385) (end 220.345 159.385) (width 0.3048) (layer B.Cu) (net 2) (tstamp 544A7A4C))
(via (at 219.075 159.385) (size 0.889) (layers F.Cu B.Cu) (net 2))
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(segment (start 216.662 164.338) (end 213.868 164.338) (width 2.54) (layer F.Cu) (net 2) (tstamp 544A269C))
(segment (start 216.8144 164.4904) (end 216.662 164.338) (width 2.54) (layer F.Cu) (net 2) (tstamp 544A269B))
(segment (start 223.266 173.736) (end 223.266 176.2125) (width 0.3048) (layer F.Cu) (net 3))
(segment (start 223.266 176.2125) (end 222.6945 176.784) (width 0.3048) (layer F.Cu) (net 3) (tstamp 544A7A21))
(segment (start 220.472 176.784) (end 211.328 176.784) (width 0.3048) (layer F.Cu) (net 4))
(segment (start 209.6897 175.1457) (end 209.6897 172.212) (width 0.3048) (layer F.Cu) (net 4) (tstamp 544A7A26))
(segment (start 211.328 176.784) (end 209.6897 175.1457) (width 0.3048) (layer F.Cu) (net 4) (tstamp 544A7A24))
(segment (start 209.6897 172.212) (end 209.6897 169.0243) (width 0.3048) (layer F.Cu) (net 4))
(segment (start 209.6897 169.0243) (end 209.804 168.91) (width 0.3048) (layer F.Cu) (net 4) (tstamp 544A77EC))
(zone (net 2) (net_name /HV) (layer B.Cu) (tstamp 544A1897) (hatch edge 0.508)
(connect_pads (clearance 0.254))
(min_thickness 0.254)
(fill (arc_segments 16) (thermal_gap 0.254) (thermal_bridge_width 1.016) (smoothing fillet) (radius 0.762))
(polygon
(pts
(xy 225.044 158.496) (xy 208.026 158.496) (xy 208.026 165.608) (xy 225.044 165.608)
)
)
(filled_polygon
(pts
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)
(zone (net 1) (net_name /GND) (layer B.Cu) (tstamp 544A26B3) (hatch edge 0.508)
(connect_pads (clearance 1.27))
(min_thickness 0.254)
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(polygon
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111
hardware/DPAK2_breakout/DPAK2_breakout.net Normal file
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@ -0,0 +1,111 @@
(export (version D)
(design
(source C:/Users/LJ/Desktop/Jared/daecu/Hardware/trunk/rusefi.com/DPAK2_breakout/DPAK2_breakout.sch)
(date "12/26/2014 5:27:54 AM")
(tool "eeschema (2013-07-07 BZR 4022)-stable"))
(components
(comp (ref R2)
(value 100K)
(footprint SM2010)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 54499C42))
(comp (ref R1)
(value 1K)
(footprint SM0805_jumper)
(libsource (lib device) (part R))
(sheetpath (names /) (tstamps /))
(tstamp 54499D02))
(comp (ref P2)
(value CONN_2)
(footprint AK300-2)
(libsource (lib conn) (part CONN_2))
(sheetpath (names /) (tstamps /))
(tstamp 5449A1BA))
(comp (ref P1)
(value CONN_1)
(footprint SIL-1)
(libsource (lib conn) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 544A1CBF))
(comp (ref P3)
(value CONN_1)
(footprint SIL-1)
(libsource (lib conn) (part CONN_1))
(sheetpath (names /) (tstamps /))
(tstamp 544A1CD8))
(comp (ref Q1)
(value IRGS14C40L)
(footprint DPAK2)
(libsource (lib transistors) (part TIP121))
(sheetpath (names /) (tstamps /))
(tstamp 5498B4BA)))
(libparts
(libpart (lib device) (part R)
(description Resistance)
(footprints
(fp R?)
(fp SM0603)
(fp SM0805)
(fp R?-*)
(fp SM1206))
(fields
(field (name Reference) R)
(field (name Value) R)
(field (name Footprint) ~)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name ~) (type passive))
(pin (num 2) (name ~) (type passive))))
(libpart (lib transistors) (part TIP120)
(description "TIP120, 5A Ic, 60V Vce, Silicon Darlington Power Transistor NPN")
(docs http://www.fairchildsemi.com/ds/TI/TIP120.pdf)
(footprints
(fp TO220*))
(fields
(field (name Reference) Q)
(field (name Value) TIP120)
(field (name Footprint) TO220)
(field (name Datasheet) ~))
(pins
(pin (num 1) (name B) (type input))
(pin (num 2) (name C) (type passive))
(pin (num 3) (name E) (type passive))))
(libpart (lib conn) (part CONN_1)
(description "1 pin")
(fields
(field (name Reference) P)
(field (name Value) CONN_1))
(pins
(pin (num 1) (name 1) (type passive))))
(libpart (lib conn) (part CONN_2)
(description "Symbole general de connecteur")
(fields
(field (name Reference) P)
(field (name Value) CONN_2))
(pins
(pin (num 1) (name P1) (type passive))
(pin (num 2) (name PM) (type passive)))))
(libraries
(library (logical transistors)
(uri "C:\\Program Files\\KiCad\\share\\library\\transistors.lib"))
(library (logical device)
(uri "C:\\Program Files\\KiCad\\share\\library\\device.lib"))
(library (logical conn)
(uri "C:\\Program Files\\KiCad\\share\\library\\conn.lib")))
(nets
(net (code 1) (name /HV)
(node (ref P2) (pin 1))
(node (ref Q1) (pin 2)))
(net (code 2) (name /SIG)
(node (ref P1) (pin 1))
(node (ref R1) (pin 1)))
(net (code 3) (name /SIG2)
(node (ref R1) (pin 2))
(node (ref Q1) (pin 1))
(node (ref R2) (pin 1)))
(net (code 4) (name /GND)
(node (ref R2) (pin 2))
(node (ref P2) (pin 2))
(node (ref P3) (pin 1))
(node (ref Q1) (pin 3)))))

84
hardware/DPAK2_breakout/DPAK2_breakout.pro Normal file
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@ -0,0 +1,84 @@
update=12/22/2014 7:07:18 PM
last_client=eeschema
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[pcbnew/libraries]
LibDir=../rusefi_lib
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=smd_capacitors
LibName7=smd_resistors
LibName8=smd_crystal&oscillator
LibName9=smd_dil
LibName10=smd_transistors
LibName11=libcms
LibName12=display
LibName13=led
LibName14=dip_sockets
LibName15=pga_sockets
LibName16=valves
LibName17=SM0805-Jumper
[eeschema]
version=1
LibDir=../rusefi_lib
NetFmtName=
RptD_X=0
RptD_Y=100
RptLab=1
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves

136
hardware/DPAK2_breakout/DPAK2_breakout.sch Normal file
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@ -0,0 +1,136 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:DDPAK_breakout-cache
EELAYER 27 0
EELAYER END
$Descr A 11000 8500
encoding utf-8
Sheet 1 1
Title "DDPAK breakout"
Date "23 dec 2014"
Rev "R0.1"
Comp "rusEFI"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L R R2
U 1 1 54499C42
P 5900 4350
F 0 "R2" V 5980 4350 40 0000 C CNN
F 1 "100K" V 5907 4351 40 0000 C CNN
F 2 "SM2010" V 5830 4350 30 0001 C CNN
F 3 "~" H 5900 4350 30 0000 C CNN
1 5900 4350
1 0 0 -1
$EndComp
$Comp
L R R1
U 1 1 54499D02
P 5600 4100
F 0 "R1" V 5680 4100 40 0000 C CNN
F 1 "1K" V 5607 4101 40 0000 C CNN
F 2 "SM0805_jumper" V 5530 4100 30 0001 C CNN
F 3 "~" H 5600 4100 30 0000 C CNN
1 5600 4100
0 -1 -1 0
$EndComp
Wire Wire Line
5850 4100 6450 4100
Connection ~ 5900 4100
Wire Wire Line
6750 4300 6750 4600
Connection ~ 6750 4600
$Comp
L CONN_2 P2
U 1 1 5449A1BA
P 7250 3950
F 0 "P2" V 7200 3950 40 0000 C CNN
F 1 "CONN_2" V 7300 3950 40 0001 C CNN
F 2 "AK300-2" H 7250 3950 60 0001 C CNN
F 3 "" H 7250 3950 60 0000 C CNN
1 7250 3950
1 0 0 -1
$EndComp
Wire Wire Line
6900 4600 6900 4050
Wire Wire Line
5350 4600 6900 4600
Connection ~ 5900 4600
Wire Wire Line
6900 3850 6750 3850
$Comp
L CONN_1 P1
U 1 1 544A1CBF
P 5200 4100
F 0 "P1" H 5280 4100 40 0000 L CNN
F 1 "CONN_1" H 5200 4155 30 0001 C CNN
F 2 "SIL-1" H 5200 4100 60 0001 C CNN
F 3 "" H 5200 4100 60 0000 C CNN
1 5200 4100
-1 0 0 1
$EndComp
$Comp
L CONN_1 P3
U 1 1 544A1CD8
P 5200 4600
F 0 "P3" H 5280 4600 40 0000 L CNN
F 1 "CONN_1" H 5200 4655 30 0001 C CNN
F 2 "SIL-1" H 5200 4600 60 0001 C CNN
F 3 "" H 5200 4600 60 0000 C CNN
1 5200 4600
-1 0 0 1
$EndComp
Text Label 5350 4100 1 60 ~ 0
SIG
Text Label 6100 4600 0 60 ~ 0
GND
Text Label 6750 3850 0 60 ~ 0
HV
Text Label 6000 4100 0 60 ~ 0
SIG2
$Comp
L TIP121 Q1
U 1 1 5498B4BA
P 6650 4100
F 0 "Q1" H 6600 3950 40 0000 R CNN
F 1 "IRGS14C40L" H 6650 4250 40 0001 R CNN
F 2 "DPAK2" H 6530 4205 29 0001 C CNN
F 3 "~" H 6650 4100 60 0000 C CNN
1 6650 4100
1 0 0 -1
$EndComp
Wire Wire Line
6750 3850 6750 3900
$EndSCHEMATC

1
hardware/DPAK2_breakout/known_issues.txt Normal file
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@ -0,0 +1 @@
1)

72
hardware/rusefi_lib/d2pak_TO263AB.mod Normal file
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@ -0,0 +1,72 @@
PCBNEW-LibModule-V1 12/23/2014 6:17:34 AM
# encoding utf-8
Units mm
$INDEX
m-pad-2.1-TO-263AB
$EndINDEX
$MODULE m-pad-2.1-TO-263AB
Po 0 0 0 15 549946B6 00000000 ~~
Li m-pad-2.1-TO-263AB
Cd FAIRCHILD'S TO-263AB/D2PAK PACKAGE DIMENSIONS
Kw FAIRCHILD'S TO-263AB/D2PAK PACKAGE DIMENSIONS
Sc 0
AR
Op 0 0 0
At SMD
T0 -6.8326 0.12446 1.27 1.27 900 0.0889 N V 20 N ">NAME"
T1 6.86308 -0.30988 1.27 1.27 900 0.0889 N V 20 N ">VALUE"
DS -4.99872 4.49834 -3.29946 4.49834 0.127 21
DS -3.29946 4.49834 -1.69926 4.49834 0.127 21
DS -1.69926 4.49834 -0.89916 4.49834 0.127 21
DS -0.89916 4.49834 0.89916 4.49834 0.127 21
DS 0.89916 4.49834 1.69926 4.49834 0.127 21
DS 1.69926 4.49834 3.29946 4.49834 0.127 21
DS 3.29946 4.49834 4.99872 4.49834 0.127 21
DS 4.99872 4.49834 4.99872 -4.49834 0.127 21
DS 4.99872 -4.49834 -4.99872 -4.49834 0.127 21
DS -4.99872 -4.49834 -4.99872 4.49834 0.127 21
DS -4.99872 -4.49834 -4.99872 -4.79044 0.127 21
DS -4.99872 -4.79044 -3.79222 -5.4991 0.127 21
DS -3.79222 -5.4991 3.79222 -5.4991 0.127 21
DS 3.79222 -5.4991 4.99872 -4.79044 0.127 21
DS 4.99872 -4.79044 4.99872 -4.49834 0.127 21
DS -0.89916 4.49834 -0.89916 6.2992 0.127 21
DS -0.89916 6.2992 0.89916 6.2992 0.127 21
DS 0.89916 6.2992 0.89916 4.49834 0.127 21
DS -3.29946 4.49834 -3.29946 7.0993 0.127 21
DS -3.29946 7.0993 -3.0988 7.69874 0.127 21
DS -3.0988 7.69874 -3.0988 10.79754 0.127 21
DS -3.0988 10.79754 -1.89992 10.79754 0.127 21
DS -1.89992 10.79754 -1.89992 7.69874 0.127 21
DS -1.89992 7.69874 -1.69926 7.0993 0.127 21
DS -1.69926 7.0993 -1.69926 4.49834 0.127 21
DS 1.69926 4.49834 1.69926 7.0993 0.127 21
DS 1.69926 7.0993 1.89992 7.69874 0.127 21
DS 1.89992 7.69874 1.89992 10.79754 0.127 21
DS 1.89992 10.79754 3.0988 10.79754 0.127 21
DS 3.0988 10.79754 3.0988 7.69874 0.127 21
DS 3.0988 7.69874 3.29946 7.0993 0.127 21
DS 3.29946 7.0993 3.29946 4.49834 0.127 21
$PAD
Sh "2" R 9.99998 8.99922 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 0 0
$EndPAD
$PAD
Sh "1" R 1.4986 3.99796 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po -2.49936 9.99998
$EndPAD
$PAD
Sh "3" R 1.4986 3.99796 0 0 0
Dr 0 0 0
At SMD N 00888000
Ne 0 ""
Po 2.49936 9.99998
$EndPAD
$EndMODULE m-pad-2.1-TO-263AB
$EndLIBRARY