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Mc33 ucode (#1734) 

* mc33 flash check

* DI sanity checks for setting HV config

* mc33816 microcodee source code update for what we got running on the r0.4 board w/ pt2001

Co-authored-by: Christopher W. Anderson <gitstuff@pswitch.com>
This commit is contained in:
NOx-z 2020-08-29 19:24:11 -07:00 committed by GitHub
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commit e1e9e2caf0
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13 changed files with 139 additions and 234 deletions
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88
firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/ch1.psc
View File

@ -1,67 +1,20 @@
********************************************************************************
* Example Code
*
* Copyright(C) 2019 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* NXP products. This software is supplied "AS IS" without any warranties
* of any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights
* under any patent, copyright, mask work right, or any other intellectual
* property rights in or to any products. NXP Semiconductors reserves the
* right to make changes in the software without notification. NXP
* Semiconductors also makes no representation or warranty that such
* application will be suitable for the specified use without further testing
* or modification.
*
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided
* that it is used in conjunction with NXP Semiconductors devices. This
* copyright, permission, and disclaimer notice must appear in all copies
* of this code.
********************************************************************************
#include "dram1.def"; #include "dram1.def";
* ### Channel 1 - uCore0 controls the injectors 1 and 2 ### * ### Channel 1 - uCore0 controls the injectors 1 and 2 ###
* ### Variables declaration ###
* Note: The data are stored into the dataRAM of the channel 1. * Note: The Thold_tot variable defines the current profile time out. The active STARTx pin is expected to toggle in is low state before this time out.
* Note: The Thold_tot variable defines the current profile time out.
* The active STARTx pin is expected to toggle in is low state before this time out.
* ### Initialization phase ### * ### Initialization phase ###
init0: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1 init0: stgn gain12.6 sssc; * Set the gain of the opamp of the current measure block 1
ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1 ldjr1 eoinj0; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2 ldjr2 idle0; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
* ### Idle phase- the uPC loops here until start signal is present ### * ### Idle phase- the uPC loops here until start signal is present ###
idle0: cwer CheckStart start row2; * Define entry table for high start pin idle0: joslr inj1_start start1; * Perform an actuation on inj1 if start 1 (only) is active
stoc on sssc; * Turn ON offset compensation joslr inj2_start start2; * Perform an actuation on inj2 if start 2 (only) is active
WaitLoop: wait row2; * uPC is stuck here for almost the whole idle time jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
CheckStart: joslr inj1_start start1; * Jump to inj1 if start 1 is high
joslr inj2_start start2; * Jump to inj2 if start 2 is high
jmpr WaitLoop;
* ### Shortcuts definition per the injector to be actuated ### * ### Shortcuts definition per the injector to be actuated ###
inj1_start: dfsct hs1 hs2 ls1; * Set the 3 shortcuts: VBAT, VBOOST, LS inj1_start: dfsct hs1 hs2 ls1; * Set the 3 shortcuts: VBAT, VBOOST, LS
jmpr boost0; * Jump to launch phase jmpr boost0; * Jump to launch phase
@ -70,9 +23,7 @@ inj2_start: dfsct hs1 hs2 ls2; * Set the 3 shortcuts: VBAT,
jmpr boost0; * Jump to launch phase jmpr boost0; * Jump to launch phase
* ### Launch phase enable boost ### * ### Launch phase enable boost ###
boost0: stoc off sssc; * Turn OFF offset compensation boost0: load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
bias all on; * Enable all biasing structures, kept ON even during actuation
load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
cwer peak0 ocur row2; * Jump to peak phase when current is over threshold cwer peak0 ocur row2; * Jump to peak phase when current is over threshold
stf low b0; * set flag0 low to force the DC-DC converter in idle mode stf low b0; * set flag0 low to force the DC-DC converter in idle mode
stos off on on; * Turn VBAT off, BOOST on, LS on stos off on on; * Turn VBAT off, BOOST on, LS on
@ -124,25 +75,17 @@ eoinj0: stos off off off; * Turn VBAT off, BOOST off,
* ### Channel 1 - uCore1 controls the injectors 3 and 4 ### * ### Channel 1 - uCore1 controls the injectors 3 and 4 ###
* ### Variables declaration ###
* Note: The data that defines the profiles are shared between the two microcores.
* ### Initialization phase ### * ### Initialization phase ###
init1: stgn gain8.68 sssc; * Set the gain of the opamp of the current measure block 1 init1: stgn gain12.6 sssc; * Set the gain of the opamp of the current measure block 1
ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1 ldjr1 eoinj1; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2 ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
* ### Idle phase- the uPC loops here until start signal is present ###
idle1: cwer CheckStart1 start row2; * Define entry table for high start pin
stoc on sssc; * Turn ON offset compensation
WaitLoop1: wait row2; * uPC is stuck here for almost the whole idle time
CheckStart1:joslr inj3_start start3; * Jump to inj1 if start 1 is high
joslr inj4_start start4; * Jump to inj2 if start 2 is high
jmpr WaitLoop1;
* ### Idle phase- the uPC loops here until start signal is present ###
idle1: joslr inj3_start start3; * Perform an actuation on inj1 if start 1 (only) is active
joslr inj4_start start4; * Perform an actuation on inj2 if start 2 (only) is active
jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
* ### Shortcuts definition per the injector to be actuated ### * ### Shortcuts definition per the injector to be actuated ###
inj3_start: dfsct hs3 hs4 ls3; * Set the 3 shortcuts: VBAT, VBOOST, LS inj3_start: dfsct hs3 hs4 ls3; * Set the 3 shortcuts: VBAT, VBOOST, LS
@ -152,8 +95,7 @@ inj4_start: dfsct hs3 hs4 ls4; * Set the 3 shortcuts: VBAT,
jmpr boost1; * Jump to launch phase jmpr boost1; * Jump to launch phase
* ### Launch phase enable boost ### * ### Launch phase enable boost ###
boost1: stoc off sssc; * Turn OFF offset compensation boost1: load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
load Iboost dac_sssc _ofs; * Load the boost phase current threshold in the current DAC
cwer peak1 ocur row2; * Jump to peak phase when current is over threshold cwer peak1 ocur row2; * Jump to peak phase when current is over threshold
stf low b0; * set flag0 low to force the DC-DC converter in idle mode stf low b0; * set flag0 low to force the DC-DC converter in idle mode
stos off on on; * Turn VBAT off, BOOST on, LS on stos off on on; * Turn VBAT off, BOOST on, LS on
@ -199,4 +141,4 @@ eoinj1: stos off off off; * Turn VBAT off, BOOST off,
stf high b0; * set flag0 to high to release the DC-DC converter idle mode stf high b0; * set flag0 to high to release the DC-DC converter idle mode
jmpf jr2; * Jump back to idle phase jmpf jr2; * Jump back to idle phase
* ### End of Channel 1 - uCore1 code ### * ### End of Channel 1 - uCore1 code ###

3
firmware/hw_layer/mc33816/rusefi/MicrocodeCh1/dram1.def
View File

@ -6,3 +6,6 @@
#define Tbypass 5; #define Tbypass 5;
#define Thold_off 6; #define Thold_off 6;
#define Thold_tot 7; #define Thold_tot 7;
#define SCV_I_hold 9;
#define SCV_Thold_tot 10;
#define SCV_Thold_off 11;

74
firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/ch2.psc
View File

@ -1,47 +1,6 @@
********************************************************************************
* Example Code
*
* Copyright(C) 2019 NXP Semiconductors
* NXP Semiconductors Confidential and Proprietary
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* NXP products. This software is supplied "AS IS" without any warranties
* of any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights
* under any patent, copyright, mask work right, or any other intellectual
* property rights in or to any products. NXP Semiconductors reserves the
* right to make changes in the software without notification. NXP
* Semiconductors also makes no representation or warranty that such
* application will be suitable for the specified use without further testing
* or modification.
*
* IN NO EVENT WILL NXP SEMICONDUCTORS BE LIABLE, WHETHER IN CONTRACT,
* TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL
* OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY
* LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST
* PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED
* BY LAW. NXP SEMICONDUCTOR???S TOTAL LIABILITY FOR ALL COSTS, DAMAGES,
* CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THE
* SOFTWARE IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP SEMICONDUCTORS
* IN CONNECTION WITH THE SOFTWARE TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided
* that it is used in conjunction with NXP Semiconductors devices. This
* copyright, permission, and disclaimer notice must appear in all copies
* of this code.
********************************************************************************
#include "dram2.def"; #include "dram2.def";
* ### Channel 2 - uCore0 controls dc-dc ### * ### Channel 2 - uCore0 controls dc-dc ###
* ### Initialization phase ### * ### Initialization phase ###
init0: stgn gain5.8 ossc; * Set the gain of the opamp of the current measure block 4 init0: stgn gain5.8 ossc; * Set the gain of the opamp of the current measure block 4
load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L load Isense4_low dac_ossc _ofs; * Load Isense4_high current threshold in DAC 4L
@ -53,16 +12,20 @@ init0: stgn gain5.8 ossc; * Set the gain of the op
* ### Asynchronous phase ### * ### Asynchronous phase ###
dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register dcdc_on: load Vboost_high dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
stf high b1;
stdcctl async; * Enable asynchronous mode stdcctl async; * Enable asynchronous mode
wait row13; * Wait for one of the previously defined conditions wait row13; * Wait for one of the previously defined conditions
* ### Synchronous phase ### * ### Synchronous phase ###
dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register dcdc_off: load Vboost_low dac4h4n _ofs; * Load the upper Vboost threshold in vboost_dac register
stf low b1;
stdcctl sync; * Enable synchronous mode stdcctl sync; * Enable synchronous mode
wait row12; * Wait for one of the previously defined conditions wait row12; * Wait for one of the previously defined conditions
* ### Idle phase ### * ### Idle phase ###
dcdc_idle: stdcctl sync; * Enable synchronous mode dcdc_idle: stdcctl sync; * Enable synchronous mode
stf low b1;
stf high b1;
jocr dcdc_idle _f0; * jump to previous line while flag 0 is low jocr dcdc_idle _f0; * jump to previous line while flag 0 is low
jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high jmpr dcdc_on; * force the DC-DC converter on when flag 0 goes high
@ -71,35 +34,32 @@ dcdc_idle: stdcctl sync; * Enable synchronous mod
********************************************************************************* *********************************************************************************
* ### Channel 2 - uCore1 drives fuel pump ### * ### Channel 2 - uCore1 drives fuel pump ###
* PCV ONLY
* Note: The Tpeak_tot variable defines the current profile time out. The active STARTx pin is expected to toggle in is low state before this time out.
* ### Initialization phase ### * ### Initialization phase ###
init1: stgn gain19.4 ossc; * Set the gain of the opamp of the current measure block 1 init1: stgn gain19.3 ossc; * Set the gain of the opamp of the current measure block 1
ldjr1 eoact1; * Load the eoinj line label Code RAM address into the register jr1 ldjr1 eoact1; * Load the eoinj line label Code RAM address into the register jr1
ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2 ldjr2 idle1; * Load the idle line label Code RAM address into the register jr2
cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase cwef jr1 _start row1; * If the start signal goes low, go to eoinj phase
* ### Idle phase- the uPC loops here until start signal is present ### * ### Idle phase- the uPC loops here until start signal is present ###
idle1: joslr act5_start start5; * Perform an actuation on act5 if start 5 (only) is active idle1: joslr act6_start start6; * Perform an actuation on act6 if start 6 (only) is active
joslr act6_start start6; * Perform an actuation on act6 if start 6 (only) is active
jmpf jr1; * If more than 1 start active at the same time(or none), no actuation jmpf jr1; * If more than 1 start active at the same time(or none), no actuation
* ### Shortcuts definition per the injector to be actuated ###
act5_start: dfsct hs5 ls5 undef; * Set the 2 shortcuts: VBAT, LS
jmpr peak1; * Jump to launch phase
act6_start: dfsct hs5 ls6 undef; * Set the 2 shortcuts: VBAT, LS act6_start: dfsct hs5 ls6 undef; * Set the 2 shortcuts: VBAT, LS
jmpr peak1; * Jump to launch phase jmpr peak1; * Jump to launch phase
* ### Launch peak phase on bat ### * ### Launch peak phase on bat ###
peak1: load Ipeak dac_ossc _ofs; * Load the boost phase current threshold in the current DAC peak1: load PCV_Ipeak dac_ossc _ofs; * Load the boost phase current threshold in the current DAC
cwer hold1 cur3 row2; * Jump to peak phase when current is over threshold cwer hold1 cur3 row2; * Jump to hold phase when current is over threshold
stos on on keep; * Turn VBAT off, BOOST on, LS on stos on on keep; * Turn VBAT on, LS on
wait row12; * Wait for one of the previously defined conditions wait row12; * Wait for one of the previously defined conditions
* ### Hold phase on Vbat ### * ### Hold phase on Vbat ###
hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the total hold phase in counter 2 hold1: ldcd rst _ofs keep keep PCV_Thold_tot c1; * Load the length of the total hold phase in counter 1
load Ihold dac_ossc _ofs; * Load the hold current threshold in the DAC load PCV_Ihold dac_ossc _ofs; * Load the hold current threshold in the DAC
cwer eoact1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count cwer eoact1 tc1 row2; * Jump to eoinj phase when tc1 reaches end of count
cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count cwer hold_on1 tc2 row3; * Jump to hold_on when tc2 reaches end of count
cwer hold_off1 cur3 row4; * Jump to hold_off when current is over threshold cwer hold_off1 cur3 row4; * Jump to hold_off when current is over threshold
@ -107,11 +67,11 @@ hold1: ldcd rst _ofs keep keep Thold_tot c1; * Load the length of the tot
hold_on1: stos on on keep; * Turn VBAT on, LS on hold_on1: stos on on keep; * Turn VBAT on, LS on
wait row124; * Wait for one of the previously defined conditions wait row124; * Wait for one of the previously defined conditions
hold_off1: ldcd rst _ofs off on Thold_off c2; * Load the length of the hold_off phase in counter 1 and turn VBAT off, LS on hold_off1: ldcd rst _ofs off on PCV_Thold_off c2; * Load the length of the hold_off phase in counter 2 and turn VBAT off, LS on
wait row123; * Wait for one of the previously defined conditions wait row123; * Wait for one of the previously defined conditions
* ### End of injection phase ### * ### End of injection phase ###
eoact1: stos off off keep; * Turn VBAT off, LS off eoact1: stos off off keep; * Turn VBAT off, LS off
jmpf jr2; * Jump back to idle phase jmpf jr2; * Jump back to idle phase
* ### End of Channel 2 - uCore1 code ### * ### End of Channel 2 - uCore1 code ###

16
firmware/hw_layer/mc33816/rusefi/MicrocodeCh2/dram2.def
View File

@ -1,8 +1,8 @@
#define Vboost_low 0; #define Vboost_high 0;
#define Vboost_high 1; #define Vboost_low 1;
#define Isense4_low 2; #define Isense4_high 2;
#define Isense4_high 3; #define Isense4_low 3;
#define Thold_off 4; #define PCV_Ipeak 5;
#define Thold_tot 5; #define PCV_Ihold 6;
#define Ipeak 6; #define PCV_Thold_off 7;
#define Ihold 7; #define PCV_Thold_tot 8;

14
firmware/hw_layer/mc33816/rusefi/Registers/ch1_config_reg.bin
View File

@ -1,19 +1,19 @@
0000000000011000 0000000000001000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000001100000011 0000001100000011
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000011011 0000000001011000
1100101000010010 1000111001100010
0100101101001010 0111101100100011
0000000000000000
0000000000101100
0000000000000000
0000000000000000 0000000000000000
0000000000110001
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000001111111111
0000001111111111
0000000000000000 0000000000000000
0000000000000000 0000000000000000

14
firmware/hw_layer/mc33816/rusefi/Registers/ch2_config_reg.bin
View File

@ -1,19 +1,19 @@
0000000000011000 0000000000001000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000110000000000 0000110000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000101010 0000000000101011
0000110001111010 0010000110001100
1110111001110001 1101110010110110
0000000000000000
0000000000010100
0000000000000000
0000000000000000 0000000000000000
0000000000010000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000001111111111
0000001111111111
0000000000000000 0000000000000000
0000000000000000 0000000000000000

40
firmware/hw_layer/mc33816/rusefi/Registers/diag_config_reg.bin
View File

@ -1,33 +1,33 @@
0001110111011010 0000000000000000
0000000000001001 0000000000000000
0000000000011110 0000000000011110
0001110111011010 0000000000000000
0000000000001001 0000000000000000
0000000000011110 0000000000011110
0000001010001110 0000000000000000
0000000000001001 0000000000000000
0000000000011110 0000000000011110
0000001010001110 0000000000000000
0000000000001001 0000000000000000
0000000000011110 0000000000011110
0000001010001110 0000000000000000
0000000000001001 0000000000000000
0000000000011110 0000000000011110
0000001010001110 0000000000000000
0000000000001001 0000000000000000
0000000000011110 0000000000011110
0000000000011110 0000000000011110
0001110111011010 0000000000000000
0000000001101001 0000000000000000
0000000000011110 0000000000011110
0001110111011010 0000000000000000
0000000001101001 0000000000000000
0000000000011110 0000000000011110
0000001010001110 0000000000000000
0000000001101001 0000000000000000
0000000000011110 0000000000011110
0000001010001110 0000000000000000
0000000001101001 0000000000000000
0000000000011110 0000000000011110
0000000000000000 0000000000000000
0000000000000000 0000000000000000

20
firmware/hw_layer/mc33816/rusefi/Registers/dram1.bin
View File

@ -1,15 +1,15 @@
0000000011010100 0000000011110000
0000000001101001 0000000011110000
0000000001000001 0000000010001100
0000000100001110 0010000000000000
0000101110111000 0000000111110100
0000000100001110 0000000010110100
0000000100001110 0000000000111100
1110101001100000 1110101001100000
0000000000000000 0000000000000000
0000000000000000 0000000000111101
0000000000000000 0110000000000000
0000000000000000 0000000000111100
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000

24
firmware/hw_layer/mc33816/rusefi/Registers/dram1.hex
View File

@ -3,21 +3,21 @@
// Asic ID: MC33816 // Asic ID: MC33816
// Version: // Version:
// DRAM // DRAM
// Date: Thursday, December 26, 2019 // Date: Sunday, August 02, 2020
// Author: Andrey // Author: DEV
// //
0x00D4, 0x00F0,
0x0069, 0x00F0,
0x0041, 0x008C,
0x010E, 0x2000,
0x0BB8, 0x01F4,
0x010E, 0x00B4,
0x010E, 0x003C,
0xEA60, 0xEA60,
0x0000, 0x0000,
0x0000, 0x003D,
0x0000, 0x6000,
0x0000, 0x003C,
0x0000, 0x0000,
0x0000, 0x0000,
0x0000, 0x0000,

14
firmware/hw_layer/mc33816/rusefi/Registers/dram2.bin
View File

@ -1,12 +1,12 @@
0000000011001101 0000000011000001
0000000011010000 0000000010111111
0000000000100101 0000000000101111
0000000000011101
0000000000000000
0000000001000110
0000000000110111 0000000000110111
0000000100001110 0000000000111100
1110101001100000 1110101001100000
0000000001101001
0000000001000001
0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000

20
firmware/hw_layer/mc33816/rusefi/Registers/dram2.hex
View File

@ -3,18 +3,18 @@
// Asic ID: MC33816 // Asic ID: MC33816
// Version: // Version:
// DRAM // DRAM
// Date: Thursday, December 26, 2019 // Date: Sunday, August 02, 2020
// Author: Andrey // Author: DEV
// //
0x00CD, 0x00C1,
0x00D0, 0x00BF,
0x0025, 0x002F,
0x0037, 0x001D,
0x010E,
0xEA60,
0x0069,
0x0041,
0x0000, 0x0000,
0x0046,
0x0037,
0x003C,
0xEA60,
0x0000, 0x0000,
0x0000, 0x0000,
0x0000, 0x0000,

36
firmware/hw_layer/mc33816/rusefi/Registers/io_config_reg.bin
View File

@ -5,7 +5,7 @@
0000000001100011 0000000001100011
0000000110001100 0000000110001100
0000100000000000 0000100000000000
0000011000010000 0000010000010000
0000000001000001 0000000001000001
0000000010011000 0000000010011000
0000000000000000 0000000000000000
@ -16,29 +16,29 @@
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000010010
0000000000010010
0000000000010010
0000000000000000
0000000000010101
0000000000010101
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000010000000 0000000000000000
0000000010000000
0000000010000000
0000000000000001
0000000010000001
0000000001000001 0000000001000001
0000000000001000 0000000001000001
0000000001000001
0000000000000000
0000000000000100 0000000000000100
0000000000000001 0001000000000000
0000000010001100 0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0111111101111111
0111111101111111
0000000001111111
0000000000000000
0000000000000000 0000000000000000
0000000000100000
0000000000100000
0000000000101110
0000000000000000 0000000000000000

10
firmware/hw_layer/mc33816/rusefi/Registers/main_config_reg.bin
View File

@ -1,9 +1,9 @@
0000000000000011 0000000000000011
0001111111000000 0001111111111110
0000000000000000
0001001000000000
0000000000000000
0000000000000000 0000000000000000
0001000000000000
0000000000010111
0010000000000000
0000000000000001 0000000000000001
0000000000000000 0000000000000000
0000000000011111 0000000000011111
@ -12,6 +12,7 @@
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000001
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
@ -19,7 +20,6 @@
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
1001110000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000
0000000000000000 0000000000000000