diff --git a/misc/install/openocd/stm32f0x.cfg b/misc/install/openocd/stm32f0x.cfg
new file mode 100644
index 0000000000..e385128fb6
--- /dev/null
+++ b/misc/install/openocd/stm32f0x.cfg
@@ -0,0 +1,95 @@
+# script for stm32f0x family
+
+#
+# stm32 devices support SWD transports only.
+#
+source [find openocd/swj-dp.tcl]
+source [find openocd/mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+	set _FLASH_SIZE $FLASH_SIZE
+} else {
+	# autodetect size
+	set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0091
+  # Section 29.5.3
+   set _CPUTAPID 0x0bb11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32f0x_default_reset_start {} {
+	# Reset clock is HSI (8 MHz)
+	adapter speed 1000
+}
+
+proc stm32f0x_default_examine_end {} {
+	# Enable debug during low power modes (uses more power)
+	mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+
+	# Stop watchdog counters during halt
+	mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f0x_default_reset_init {} {
+	# Configure PLL to boost clock to HSI x 6 (48 MHz)
+	mww 0x40021004 0x00100000   ;# RCC_CFGR = PLLMUL[2]
+	mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
+	mww 0x40022000 0x00000011   ;# FLASH_ACR = PRFTBE | LATENCY[0]
+	sleep 10                    ;# Wait for PLL to lock
+	mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+	# Boost JTAG frequency
+	adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }
diff --git a/misc/install/openocd/stm32f103c8_blue_pill.cfg b/misc/install/openocd/stm32f103c8_blue_pill.cfg
new file mode 100644
index 0000000000..f4a5c9373d
--- /dev/null
+++ b/misc/install/openocd/stm32f103c8_blue_pill.cfg
@@ -0,0 +1,14 @@
+# STM32F103C8 "Blue Pill"
+
+# NOTE:
+# There is a fair bit of confusion about whether the "Blue Pill" has 128kB or 64kB flash size.
+# The most likely cause is that there exist a -C8 and a -CB variant of the STM32F103, where
+# the C8 has 64kB, the CB has 128kB as per specification. "Blue Pill" boards are manufactured
+# by a lot of different vendors, some may actually use the CB variant but from a cursory look
+# it very hard to tell them apart ("C8" and "CB" look very similar). Nevertheless, people have
+# tried using the full 128kB of flash on the C8 and found it to be working. Hence this board file
+# overrides the internal size detection. Be aware though that you may be using you particular
+# board outside of its specification. If in doubt, comment the following line.
+set FLASH_SIZE 0x20000
+
+source [find openocd/stm32f1x.cfg]
diff --git a/misc/install/openocd/stm32f1x.cfg b/misc/install/openocd/stm32f1x.cfg
new file mode 100644
index 0000000000..b32d2d24b1
--- /dev/null
+++ b/misc/install/openocd/stm32f1x.cfg
@@ -0,0 +1,89 @@
+# script for stm32f1x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find openocd/swj-dp.tcl]
+source [find openocd/mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f1x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some STM32F100s)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+# Allow overriding the Flash bank size
+if { [info exists FLASH_SIZE] } {
+    set _FLASH_SIZE $FLASH_SIZE
+} else {
+    # autodetect size
+    set _FLASH_SIZE 0
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter speed 1000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
diff --git a/misc/install/readme.md b/misc/install/readme.md
new file mode 100644
index 0000000000..cd7cf1ae3c
--- /dev/null
+++ b/misc/install/readme.md
@@ -0,0 +1 @@
+Subset of files from https://gnutoolchains.com/arm-eabi/openocd/
\ No newline at end of file
diff --git a/misc/install/run_openocd_f1.bat b/misc/install/run_openocd_f1.bat
new file mode 100644
index 0000000000..d73e7174ad
--- /dev/null
+++ b/misc/install/run_openocd_f1.bat
@@ -0,0 +1 @@
+openocd\openocd.exe -f openocd/stm32f103c8_blue_pill.cfg -c init -c reset