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This commit is contained in:
rusEfi 2014-11-06 15:03:13 -06:00
parent 5563729d8a
commit f063b38bdc
5 changed files with 60 additions and 32 deletions
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25
firmware/chibios/os/hal/src/usb.c
View File

@ -634,7 +634,12 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
return;
}
}
#if (USB_SET_ADDRESS_ACK_HANDLING == USB_SET_ADDRESS_ACK_HW)
if (usbp->setup[1] == USB_REQ_SET_ADDRESS) {
/* Zero-length packet sent by hardware */
return;
}
#endif
/* Transfer preparation. The request handler must have populated
correctly the fields ep0next, ep0n and ep0endcb using the macro
usbSetupTransfer().*/
@ -656,10 +661,14 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
/* No transmission phase, directly receiving the zero sized status
packet.*/
usbp->ep0state = USB_EP0_WAITING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareReceive(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartReceiveI(usbp, 0);
chSysUnlockFromIsr();
#else
usb_lld_end_setup(usbp, ep);
#endif
}
}
else {
@ -676,10 +685,14 @@ void _usb_ep0setup(USBDriver *usbp, usbep_t ep) {
/* No receive phase, directly sending the zero sized status
packet.*/
usbp->ep0state = USB_EP0_SENDING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareTransmit(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartTransmitI(usbp, 0);
chSysUnlockFromIsr();
#else
usb_lld_end_setup(usbp, ep);
#endif
}
}
}
@ -716,10 +729,14 @@ void _usb_ep0in(USBDriver *usbp, usbep_t ep) {
case USB_EP0_WAITING_TX0:
/* Transmit phase over, receiving the zero sized status packet.*/
usbp->ep0state = USB_EP0_WAITING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareReceive(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartReceiveI(usbp, 0);
chSysUnlockFromIsr();
#else
usb_lld_end_setup(usbp, ep);
#endif
return;
case USB_EP0_SENDING_STS:
/* Status packet sent, invoking the callback if defined.*/
@ -756,16 +773,22 @@ void _usb_ep0out(USBDriver *usbp, usbep_t ep) {
case USB_EP0_RX:
/* Receive phase over, sending the zero sized status packet.*/
usbp->ep0state = USB_EP0_SENDING_STS;
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
usbPrepareTransmit(usbp, 0, NULL, 0);
chSysLockFromIsr();
usbStartTransmitI(usbp, 0);
chSysUnlockFromIsr();
#else
usb_lld_end_setup(usbp, ep);
#endif
return;
case USB_EP0_WAITING_STS:
/* Status packet received, it must be zero sized, invoking the callback
if defined.*/
#if (USB_EP0_STATUS_STAGE == USB_EP0_STATUS_STAGE_SW)
if (usbGetReceiveTransactionSizeI(usbp, 0) != 0)
break;
#endif
if (usbp->ep0endcb != NULL)
usbp->ep0endcb(usbp);
usbp->ep0state = USB_EP0_WAITING_SETUP;

22
firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.c
View File

@ -35,28 +35,6 @@
#include "ch.h"
extern stkalign_t __main_stack_base__;
int getRemainingStack(Thread *otp) {
#if CH_DBG_ENABLE_STACK_CHECK
register struct intctx *r13 asm ("r13");
otp->activeStack = r13;
int rs;
if (dbg_isr_cnt > 0) {
// ISR context
rs = (stkalign_t *) (r13 - 1) - &__main_stack_base__;
} else {
rs = (stkalign_t *) (r13 - 1) - otp->p_stklimit;
}
otp->remainingStack = rs;
return rs;
#else
return 99999;
#endif /* CH_DBG_ENABLE_STACK_CHECK */
}
/*===========================================================================*/
/* Port interrupt handlers. */
/*===========================================================================*/

8
firmware/chibios/os/ports/GCC/ARMCMx/chcore_v7m.h
View File

@ -36,8 +36,6 @@
#ifndef _CHCORE_V7M_H_
#define _CHCORE_V7M_H_
#include "chdebug.h"
/*===========================================================================*/
/* Port constants. */
/*===========================================================================*/
@ -72,13 +70,13 @@
* @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
* @note In this port this value is conservatively set to 32 because the
* @note In this port this value is conservatively set to 64 because the
* function @p chSchDoReschedule() can have a stack frame, especially
* with compiler optimizations disabled. The value can be reduced
* when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
#define PORT_INT_REQUIRED_STACK 32
#define PORT_INT_REQUIRED_STACK 64
#endif
/**
@ -263,7 +261,7 @@ struct extctx {
regarm_t s14;
regarm_t s15;
regarm_t fpscr;
regarm_t fpccr;
regarm_t reserved;
#endif /* CORTEX_USE_FPU */
};

10
firmware/chibios/os/various/chprintf.c
View File

@ -217,9 +217,11 @@ void chvprintf(BaseSequentialStream *chp, const char *fmt, va_list ap) {
break;
#if CHPRINTF_USE_FLOAT
case 'f':
f = (float) va_arg(ap, double);
if (f < 0) {
*p++ = '-';
f = -f;
}
p = ftoa(p, f, precision);
break;
#endif
@ -255,9 +257,9 @@ unsigned_common:
chSequentialStreamPut(chp, (uint8_t)*s++);
i--;
}
do
do {
chSequentialStreamPut(chp, (uint8_t)filler);
while (++width != 0);
} while (++width != 0);
}
chSequentialStreamWrite(chp, (uint8_t*)s, i);
s += i;

27
firmware/hw_layer/stm32f4/mpu_util.cpp
View File

@ -9,6 +9,33 @@
#include "mpu_util.h"
#include "error_handling.h"
extern "C" {
int getRemainingStack(Thread *otp);
}
extern stkalign_t __main_stack_base__;
int getRemainingStack(Thread *otp) {
#if CH_DBG_ENABLE_STACK_CHECK
register struct intctx *r13 asm ("r13");
otp->activeStack = r13;
int rs;
if (dbg_isr_cnt > 0) {
// ISR context
rs = (stkalign_t *) (r13 - 1) - &__main_stack_base__;
} else {
rs = (stkalign_t *) (r13 - 1) - otp->p_stklimit;
}
otp->remainingStack = rs;
return rs;
#else
return 99999;
#endif /* CH_DBG_ENABLE_STACK_CHECK */
}
void baseHardwareInit(void) {
// looks like this holds a random value on start? Let's set a nice clean zero
DWT_CYCCNT = 0;