From f0ccd53f0d4662cb3a037f963bcc5fca8e9d0f7f Mon Sep 17 00:00:00 2001 From: rusefi Date: Tue, 8 Jan 2019 19:08:47 -0500 Subject: [PATCH] we need to find a way away from this manual sync approach :( --- .../TLE8110ED_breakout_board/TLE8110ED.bak | 394 --------- .../TLE8110ED.kicad_pcb | 181 ++++- .../TLE8110ED.kicad_pcb-bak | 750 ------------------ .../TLE8110ED_breakout_board/TLE8110ED.sch | 10 +- .../TLE8110ED_large trace.pro | 65 -- 5 files changed, 153 insertions(+), 1247 deletions(-) delete mode 100644 hardware/TLE8110ED_breakout_board/TLE8110ED.bak delete mode 100644 hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb-bak delete mode 100644 hardware/TLE8110ED_breakout_board/TLE8110ED_large trace.pro diff --git a/hardware/TLE8110ED_breakout_board/TLE8110ED.bak b/hardware/TLE8110ED_breakout_board/TLE8110ED.bak deleted file mode 100644 index 14219a0d75..0000000000 --- a/hardware/TLE8110ED_breakout_board/TLE8110ED.bak +++ /dev/null @@ -1,394 +0,0 @@ -EESchema Schematic File Version 2 -LIBS:TLE8110ED -LIBS:conn -LIBS:mechanical -LIBS:TLE8110ED-cache -EELAYER 25 0 -EELAYER END -$Descr A4 11693 8268 -encoding utf-8 -Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" -Comment1 "" -Comment2 "" -Comment3 "" -Comment4 "" -$EndDescr -$Comp -L TLE8110ED U1 -U 1 1 5C2D1911 -P 5800 3500 -F 0 "U1" H 5800 3550 60 0000 C CNN -F 1 "TLE8110ED" H 5800 3350 60 0000 C CNN -F 2 "TLE8110ED:PG-DSO-36-72" H 5800 3550 60 0001 C CNN -F 3 "" H 5800 3550 60 0001 C CNN - 1 5800 3500 - 1 0 0 -1 -$EndComp -$Comp -L Conn_01x18 J1 -U 1 1 5C2D19AC -P 3300 3550 -F 0 "J1" H 3300 4450 50 0000 C CNN -F 1 "Conn_01x18" H 3300 2550 50 0000 C CNN -F 2 "Pin_Headers:Pin_Header_Straight_1x18_Pitch2.54mm" H 3300 3550 50 0001 C CNN -F 3 "" H 3300 3550 50 0001 C CNN - 1 3300 3550 - -1 0 0 1 -$EndComp -$Comp -L Screw_Terminal_01x16 J2 -U 1 1 5C2D19ED -P 8450 3300 -F 0 "J2" H 8450 4100 50 0000 C CNN -F 1 "Screw_Terminal_01x16" H 8450 2400 50 0000 C CNN -F 2 "Connectors_Terminal_Blocks:TerminalBlock_Pheonix_PT-3.5mm_16pol" H 8450 3300 50 0001 C CNN -F 3 "" H 8450 3300 50 0001 C CNN - 1 8450 3300 - 1 0 0 -1 -$EndComp -Wire Wire Line - 8250 2600 8150 2600 -Wire Wire Line - 8150 2600 8150 2250 -Wire Wire Line - 8150 2250 6650 2250 -Wire Wire Line - 8250 2700 7450 2700 -Wire Wire Line - 7450 2700 7450 2400 -Wire Wire Line - 7450 2400 6650 2400 -Wire Wire Line - 8250 2800 7350 2800 -Wire Wire Line - 7350 2800 7350 2550 -Wire Wire Line - 7350 2550 6650 2550 -Wire Wire Line - 8250 2900 7250 2900 -Wire Wire Line - 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H 2150 1700 50 0000 C CNN -F 1 "Mounting_Hole" H 2150 1625 50 0000 C CNN -F 2 "" H 2150 1500 50 0001 C CNN -F 3 "" H 2150 1500 50 0001 C CNN - 1 2150 1500 - 1 0 0 -1 -$EndComp -$Comp -L Mounting_Hole MK? -U 1 1 5C2E7432 -P 2800 1500 -F 0 "MK?" H 2800 1700 50 0000 C CNN -F 1 "Mounting_Hole" H 2800 1625 50 0000 C CNN -F 2 "" H 2800 1500 50 0001 C CNN -F 3 "" H 2800 1500 50 0001 C CNN - 1 2800 1500 - 1 0 0 -1 -$EndComp -$Comp -L Mounting_Hole MK? -U 1 1 5C2E7487 -P 2200 2000 -F 0 "MK?" H 2200 2200 50 0000 C CNN -F 1 "Mounting_Hole" H 2200 2125 50 0000 C CNN -F 2 "" H 2200 2000 50 0001 C CNN -F 3 "" H 2200 2000 50 0001 C CNN - 1 2200 2000 - 1 0 0 -1 -$EndComp -$Comp -L Mounting_Hole MK? -U 1 1 5C2E74A8 -P 2800 1950 -F 0 "MK?" H 2800 2150 50 0000 C CNN -F 1 "Mounting_Hole" H 2800 2075 50 0000 C CNN -F 2 "" H 2800 1950 50 0001 C CNN -F 3 "" H 2800 1950 50 0001 C CNN - 1 2800 1950 - 1 0 0 -1 -$EndComp -$EndSCHEMATC diff --git a/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb b/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb index a487fae9e2..9c71968c27 100644 --- a/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb +++ b/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb @@ -2,10 +2,10 @@ (general (links 55) - (no_connects 0) - (area 119.964999 82.499999 178.485001 123.240001) + (no_connects 1) + (area 118.415 82.499999 180.77 125.619762) (thickness 1.6) - (drawings 40) + (drawings 76) (tracks 307) (zones 0) (modules 7) @@ -13,6 +13,13 @@ ) (page USLetter) + (title_block + (title "TLE8110ED breakout board") + (date 2019-01-06) + (rev 0.1) + (company rusEFI) + ) + (layers (0 F.Cu signal) (31 B.Cu signal) @@ -20,12 +27,12 @@ (33 F.Adhes user hide) (34 B.Paste user hide) (35 F.Paste user hide) - (36 B.SilkS user hide) + (36 B.SilkS user) (37 F.SilkS user) (38 B.Mask user) (39 F.Mask user) - (40 Dwgs.User user) - (41 Cmts.User user) + (40 Dwgs.User user hide) + (41 Cmts.User user hide) (42 Eco1.User user hide) (43 Eco2.User user hide) (44 Edge.Cuts user) @@ -63,7 +70,7 @@ (pad_to_mask_clearance 0) (aux_axis_origin 144.78 107.95) (grid_origin 144.78 107.95) - (visible_elements 7FFCDFFF) + (visible_elements 7FFFC609) (pcbplotparams (layerselection 0x00030_80000001) (usegerberextensions false) @@ -513,31 +520,139 @@ (pad 1 np_thru_hole circle (at 0 0 90) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask)) ) + (gr_text "TLE8110ED\nbreakout board" (at 122.428 106.299) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3)) (justify left)) + ) + (gr_text "rusEFI.com R0.1" (at 122.682 112.522) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.3)) (justify left)) + ) + (gr_text S_SO (at 171.45 115.824 270) (layer B.SilkS) (tstamp 5C32AEC3) + (effects (font (size 1.5 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117.094 270) (layer F.SilkS) (tstamp 5C2E71B3) + (effects (font (size 1.5 1.5) (thickness 0.3))) ) (gr_text In10 (at 151.13 116.205 270) (layer F.SilkS) (tstamp 5C2E71B1) (effects (font (size 1.5 1.5) (thickness 0.3))) @@ -569,34 +684,34 @@ (gr_text In1 (at 128.27 116.84 270) (layer F.SilkS) (tstamp 5C2E7182) (effects (font (size 1.5 1.5) (thickness 0.3))) ) - (gr_text Out10 (at 143.51 95.25 90) (layer F.SilkS) (tstamp 5C2E7121) + (gr_text Out10 (at 143.383 94.869 90) (layer F.SilkS) (tstamp 5C2E7121) (effects (font (size 1.5 1.5) (thickness 0.3))) ) - (gr_text Out9 (at 146.685 94.615 90) (layer F.SilkS) (tstamp 5C2E711F) + (gr_text Out9 (at 147.066 94.107 90) (layer F.SilkS) (tstamp 5C2E711F) (effects (font (size 1.5 1.5) (thickness 0.3))) ) - (gr_text Out8 (at 150.495 94.615 90) (layer F.SilkS) (tstamp 5C2E711A) + (gr_text Out8 (at 150.495 94.234 90) (layer F.SilkS) (tstamp 5C2E711A) (effects (font (size 1.5 1.5) (thickness 0.3))) ) - (gr_text Out7 (at 154.305 94.615 90) (layer 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5C2E7104) + (gr_text Out5 (at 161.163 94.234 90) (layer F.SilkS) (tstamp 5C2E7104) (effects (font (size 1.5 1.5) (thickness 0.3))) ) - (gr_text Out6 (at 157.48 94.615 90) (layer F.SilkS) (tstamp 5C2E70F6) + (gr_text Out6 (at 157.607 94.234 90) (layer F.SilkS) (tstamp 5C2E70F6) (effects (font (size 1.5 1.5) (thickness 0.3))) ) (gr_text GND6 (at 139.7 94.615 90) (layer F.SilkS) (tstamp 5C2E70CB) diff --git a/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb-bak b/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb-bak deleted file mode 100644 index 297432f8fa..0000000000 --- a/hardware/TLE8110ED_breakout_board/TLE8110ED.kicad_pcb-bak +++ /dev/null @@ -1,750 +0,0 @@ -(kicad_pcb (version 4) (host pcbnew 4.0.7) - - (general - (links 55) - (no_connects 0) - (area 119.964999 82.499999 178.485001 123.240001) - (thickness 1.6) - (drawings 4) - (tracks 292) - (zones 0) - (modules 3) - (nets 37) - ) - - (page USLetter) - (layers - (0 F.Cu signal) - (31 B.Cu signal) - (32 B.Adhes user) - (33 F.Adhes user) - (34 B.Paste user) - (35 F.Paste user) - (36 B.SilkS user) - (37 F.SilkS user) - (38 B.Mask user) - (39 F.Mask user) - (40 Dwgs.User user) - (41 Cmts.User user) - (42 Eco1.User user) - (43 Eco2.User user) - (44 Edge.Cuts user) - (45 Margin user) - (46 B.CrtYd user) - (47 F.CrtYd user) - (48 B.Fab user) - (49 F.Fab user) - ) - - (setup - (last_trace_width 0.25) - (trace_clearance 0.2) - (zone_clearance 0.508) - (zone_45_only no) - (trace_min 0.2) - (segment_width 0.2) - (edge_width 0.1) - (via_size 0.6) - (via_drill 0.4) - (via_min_size 0.4) - (via_min_drill 0.3) - (uvia_size 0.3) - (uvia_drill 0.1) - (uvias_allowed no) - (uvia_min_size 0.2) - (uvia_min_drill 0.1) - (pcb_text_width 0.3) - (pcb_text_size 1.5 1.5) - (mod_edge_width 0.15) - (mod_text_size 1 1) - (mod_text_width 0.15) - (pad_size 1.5 1.5) - (pad_drill 0.6) - (pad_to_mask_clearance 0) - (aux_axis_origin 0 0) - (grid_origin 144.78 107.95) - (visible_elements 7FFFFFFF) - (pcbplotparams - (layerselection 0x00030_80000001) - (usegerberextensions false) - (excludeedgelayer true) - (linewidth 0.100000) - (plotframeref false) - (viasonmask false) - (mode 1) - (useauxorigin false) - (hpglpennumber 1) - (hpglpenspeed 20) - (hpglpendiameter 15) - (hpglpenoverlay 2) - (psnegative false) - (psa4output false) - (plotreference true) - (plotvalue true) - (plotinvisibletext false) - (padsonsilk false) - (subtractmaskfromsilk false) - (outputformat 1) - (mirror false) - (drillshape 1) - (scaleselection 1) - (outputdirectory "")) - ) - - (net 0 "") - (net 1 "Net-(J1-Pad4)") - (net 2 "Net-(U1-Pad33)") - (net 3 "Net-(U1-Pad22)") - (net 4 /In5) - (net 5 /In4) - (net 6 /In3) - (net 7 /In2) - (net 8 /In1) - (net 9 /S_SO) - (net 10 /S_CLK) - (net 11 /S_CS) - (net 12 /VCC) - (net 13 /VDD) - (net 14 /~RST) - (net 15 /EN) - (net 16 /In10) - (net 17 /In9) - (net 18 /In8) - (net 19 /In7) - (net 20 /In6) - (net 21 /Out3) - (net 22 /Out2) - (net 23 /Out4) - (net 24 /Out5) - (net 25 /Out6) - (net 26 /Out7) - (net 27 /Out1) - (net 28 /Out8) - (net 29 /Out9) - (net 30 /Out10) - (net 31 /GND6) - (net 32 /GND5) - (net 33 /GND4) - (net 34 /GND3) - (net 35 /GND2) - (net 36 /GND1) - - (net_class Default "This is the default net class." - (clearance 0.2) - (trace_width 0.25) - (via_dia 0.6) - (via_drill 0.4) - (uvia_dia 0.3) - (uvia_drill 0.1) - (add_net /EN) - (add_net /GND1) - (add_net /GND2) - (add_net /GND3) - (add_net /GND4) - (add_net /GND5) - (add_net /GND6) - (add_net /In1) - (add_net /In10) - (add_net /In2) - (add_net /In3) - (add_net /In4) - (add_net /In5) - (add_net /In6) - (add_net /In7) - (add_net /In8) - (add_net /In9) - (add_net /Out1) - (add_net /Out10) - (add_net /Out2) - (add_net /Out3) - (add_net /Out4) - (add_net /Out5) - (add_net /Out6) - (add_net /Out7) - (add_net /Out8) - (add_net /Out9) - (add_net /S_CLK) - (add_net /S_CS) - (add_net /S_SO) - (add_net /VCC) - (add_net /VDD) - (add_net /~RST) - (add_net "Net-(J1-Pad4)") - (add_net "Net-(U1-Pad22)") - (add_net "Net-(U1-Pad33)") - ) - - (module Connectors_Terminal_Blocks:TerminalBlock_Pheonix_PT-3.5mm_16pol (layer F.Cu) (tedit 0) (tstamp 5C2D1B72) - (at 174.995 88.265 180) - (descr "16-way 3.5mm pitch terminal block, Phoenix PT series") - (path /5C2D19ED) - (fp_text reference J2 (at 26.25 -4.3 180) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Screw_Terminal_01x16 (at 10.53 -3.175 180) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -1.9 -3.3) (end 54.4 -3.3) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.9 4.7) (end -1.9 -3.3) (layer F.CrtYd) (width 0.05)) - (fp_line (start 54.4 4.7) (end -1.9 4.7) (layer F.CrtYd) (width 0.05)) - (fp_line (start 54.4 -3.3) (end 54.4 4.7) (layer F.CrtYd) (width 0.05)) - (fp_line (start 50.75 4.1) (end 50.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 47.25 4.1) (end 47.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 40.25 4.1) (end 40.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 43.75 4.1) (end 43.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 36.75 4.1) (end 36.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 33.25 4.1) (end 33.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 26.25 4.1) (end 26.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 29.75 4.1) (end 29.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 22.75 4.1) (end 22.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 8.75 4.1) (end 8.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 19.25 4.1) (end 19.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 15.75 4.1) (end 15.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 1.75 4.1) (end 1.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 5.25 4.1) (end 5.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 12.25 4.1) (end 12.25 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.75 3) (end 54.25 3) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.75 4.1) (end 54.25 4.1) (layer F.SilkS) (width 0.15)) - (fp_line (start -1.75 -3.1) (end -1.75 4.5) (layer F.SilkS) (width 0.15)) - (fp_line (start 54.25 4.5) (end 54.25 -3.1) (layer F.SilkS) (width 0.15)) - (fp_line (start 54.25 -3.1) (end -1.75 -3.1) (layer F.SilkS) (width 0.15)) - (pad 3 thru_hole circle (at 7 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 21 /Out3)) - (pad 2 thru_hole circle (at 3.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 22 /Out2)) - (pad 4 thru_hole circle (at 10.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 23 /Out4)) - (pad 5 thru_hole circle (at 14 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 24 /Out5)) - (pad 6 thru_hole circle (at 17.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 25 /Out6)) - (pad 7 thru_hole circle (at 21 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 26 /Out7)) - (pad 1 thru_hole rect (at 0 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 27 /Out1)) - (pad 8 thru_hole circle (at 24.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 28 /Out8)) - (pad 9 thru_hole circle (at 28 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 29 /Out9)) - (pad 10 thru_hole circle (at 31.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 30 /Out10)) - (pad 11 thru_hole circle (at 35 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 31 /GND6)) - (pad 12 thru_hole circle (at 38.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 32 /GND5)) - (pad 13 thru_hole circle (at 42 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 33 /GND4)) - (pad 14 thru_hole circle (at 45.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 34 /GND3)) - (pad 15 thru_hole circle (at 49 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 35 /GND2)) - (pad 16 thru_hole circle (at 52.5 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask) - (net 36 /GND1)) - (model Terminal_Blocks.3dshapes/TerminalBlock_Pheonix_PT-3.5mm_16pol.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module Pin_Headers:Pin_Header_Straight_1x18_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 5C2D1B5E) - (at 171.45 120.65 270) - (descr "Through hole straight pin header, 1x18, 2.54mm pitch, single row") - (tags "Through hole pin header THT 1x18 2.54mm single row") - (path /5C2D19AC) - (fp_text reference J1 (at 0 -2.33 270) (layer F.SilkS) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value Conn_01x18 (at -6.985 41.91 270) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 -1.27) (end 1.27 44.45) (layer F.Fab) (width 0.1)) - (fp_line (start 1.27 44.45) (end -1.27 44.45) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 44.45) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) - (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) - (fp_line (start -1.33 44.51) (end 1.33 44.51) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end -1.33 44.51) (layer F.SilkS) (width 0.12)) - (fp_line (start 1.33 1.27) (end 1.33 44.51) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) - (fp_line (start -1.8 -1.8) (end -1.8 44.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start -1.8 44.95) (end 1.8 44.95) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 44.95) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) - (fp_text user %R (at 0 21.59 360) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad 1 thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 9 /S_SO)) - (pad 2 thru_hole oval (at 0 2.54 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 10 /S_CLK)) - (pad 3 thru_hole oval (at 0 5.08 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 11 /S_CS)) - (pad 4 thru_hole oval (at 0 7.62 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 1 "Net-(J1-Pad4)")) - (pad 5 thru_hole oval (at 0 10.16 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 12 /VCC)) - (pad 6 thru_hole oval (at 0 12.7 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 13 /VDD)) - (pad 7 thru_hole oval (at 0 15.24 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 14 /~RST)) - (pad 8 thru_hole oval (at 0 17.78 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 15 /EN)) - (pad 9 thru_hole oval (at 0 20.32 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 16 /In10)) - (pad 10 thru_hole oval (at 0 22.86 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 17 /In9)) - (pad 11 thru_hole oval (at 0 25.4 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 18 /In8)) - (pad 12 thru_hole oval (at 0 27.94 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 19 /In7)) - (pad 13 thru_hole oval (at 0 30.48 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 20 /In6)) - (pad 14 thru_hole oval (at 0 33.02 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 4 /In5)) - (pad 15 thru_hole oval (at 0 35.56 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 5 /In4)) - (pad 16 thru_hole oval (at 0 38.1 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 6 /In3)) - (pad 17 thru_hole oval (at 0 40.64 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 7 /In2)) - (pad 18 thru_hole oval (at 0 43.18 270) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) - (net 8 /In1)) - (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x18_Pitch2.54mm.wrl - (at (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - - (module TLE8110ED:PG-DSO-36-72 (layer F.Cu) (tedit 5C2CDF8A) (tstamp 5C2D1BAF) - (at 148.5011 105.0036) - (path /5C2D1911) - (fp_text reference U1 (at -6.075 0 90) (layer F.SilkS) - (effects (font (size 1.2 1.2) (thickness 0.15))) - ) - (fp_text value TLE8110ED (at 0.5 2.8) (layer F.Fab) - (effects (font (size 0.8 0.7) (thickness 0.12))) - ) - (fp_circle (center -4.3 3.19) (end -4.5 3.19) (layer F.SilkS) (width 0.3)) - (fp_line (start -5.15 -5.75) (end -5.15 4.75) (layer F.SilkS) (width 0.15)) - (fp_line (start -4.15 5.75) (end 5.15 5.75) (layer F.SilkS) (width 0.15)) - (fp_line (start 5.15 5.75) (end 5.15 -5.75) (layer F.SilkS) (width 0.15)) - (fp_line (start 5.15 -5.75) (end -5.15 -5.75) (layer F.SilkS) (width 0.15)) - (pad 36 smd rect (at -4.25 -4.45) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask) - (net 33 /GND4)) - (pad 1 smd rect (at -4.25 4.45) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask) - (net 36 /GND1)) - (pad 35 smd rect (at -3.75 -4.45) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask) - (net 26 /Out7)) - (pad 2 smd rect (at -3.75 4.45) (size 0.25 1.6) (layers F.Cu F.Paste F.Mask) - (net 8 /In1)) - (pad 34 smd rect (at -3.25 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a521feb79d..ed392301e0 100644 --- a/hardware/TLE8110ED_breakout_board/TLE8110ED.sch +++ b/hardware/TLE8110ED_breakout_board/TLE8110ED.sch @@ -5,13 +5,13 @@ LIBS:mechanical LIBS:TLE8110ED-cache EELAYER 25 0 EELAYER END -$Descr A4 11693 8268 +$Descr USLetter 11000 8500 encoding utf-8 Sheet 1 1 -Title "" -Date "" -Rev "" -Comp "" +Title "TLE8110ED breakout board" +Date "2019-01-06" +Rev "0.1" +Comp "rusEFI" Comment1 "" Comment2 "" Comment3 "" diff --git a/hardware/TLE8110ED_breakout_board/TLE8110ED_large trace.pro b/hardware/TLE8110ED_breakout_board/TLE8110ED_large trace.pro deleted file mode 100644 index e2acca815e..0000000000 --- a/hardware/TLE8110ED_breakout_board/TLE8110ED_large trace.pro +++ /dev/null @@ -1,65 +0,0 @@ -update=Mon 31 Jul 2017 10:04:56 AM MDT -version=1 -last_client=kicad -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] -LibName1=power -LibName2=device -LibName3=switches -LibName4=relays -LibName5=motors -LibName6=transistors -LibName7=conn -LibName8=linear -LibName9=regul -LibName10=74xx -LibName11=cmos4000 -LibName12=adc-dac -LibName13=memory -LibName14=xilinx -LibName15=microcontrollers -LibName16=dsp -LibName17=microchip -LibName18=analog_switches -LibName19=motorola -LibName20=texas -LibName21=intel -LibName22=audio -LibName23=interface -LibName24=digital-audio -LibName25=philips -LibName26=display -LibName27=cypress -LibName28=siliconi -LibName29=opto -LibName30=atmel -LibName31=contrib -LibName32=valves