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S105: successed TS connection over CAN (#4933) 

* s105: fix CAN pinout

* s105: board.c with default GPIO settings (dumped from stock FW)

* s105: no HSE

* s105: override for CAN1

* s105: enable secondary LDO

* s105: only 512K of flash

* s105: we are very limited in flash: disable LUA, disable LCD

* S105: correct signature
This commit is contained in:
Andrey G 2023-01-04 01:29:53 +03:00 committed by GitHub
parent 15df54eeea
commit f45ce26a81
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 434 additions and 1 deletions
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123
firmware/config/boards/s105/board.c Normal file
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@ -0,0 +1,123 @@
/**
* @file boards/S105/board.c
*
* @date Jan 03, 2023
* @author Andrey Gusakov, 2023
*/
#include "hal.h"
/*==========================================================================*/
/* Driver local definitions. */
/*==========================================================================*/
/*==========================================================================*/
/* Driver exported variables. */
/*==========================================================================*/
/*==========================================================================*/
/* Driver local variables and types. */
/*==========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
gpio_setup_t PAData;
gpio_setup_t PBData;
gpio_setup_t PCData;
gpio_setup_t PDData;
gpio_setup_t PEData;
gpio_setup_t PFData;
gpio_setup_t PGData;
gpio_setup_t PHData;
gpio_setup_t PIData;
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
};
/*==========================================================================*/
/* Driver local functions. */
/*==========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
* registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
gpio_init(GPIOA, &gpio_default_config.PAData);
gpio_init(GPIOB, &gpio_default_config.PBData);
gpio_init(GPIOC, &gpio_default_config.PCData);
gpio_init(GPIOD, &gpio_default_config.PDData);
gpio_init(GPIOE, &gpio_default_config.PEData);
gpio_init(GPIOF, &gpio_default_config.PFData);
gpio_init(GPIOG, &gpio_default_config.PGData);
gpio_init(GPIOH, &gpio_default_config.PHData);
gpio_init(GPIOI, &gpio_default_config.PIData);
}
/*
* Early initialization code.
* This initialization must be performed just after stack setup and before
* any other initialization.
*/
void __early_init(void)
{
stm32_gpio_init();
stm32_clock_init();
}
/*
* Board-specific initialization code.
*/
void boardInit(void) {
}

289
firmware/config/boards/s105/board.h Normal file
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@ -0,0 +1,289 @@
/**
* @file boards/S105/board.h
*
* @date Jan 03, 2023
* @author Andrey Gusakov, 2023
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* Board identifier.
*/
#define BOARD_NAME "Soate S105"
/*
* Board frequencies.
* NOTE: The LSE and HSE crystals are not fitted by default on the board.
*/
#define STM32_LSECLK 32768
#define STM32_HSECLK 25000000
/*
* Board voltages.
* Required for performance limits calculation.
*/
#define STM32_VDD 330
/*
* IO pins assignments.
*/
#define GPIOC_OSC32_IN 14
#define GPIOC_OSC32_OUT 15
#define GPIOH_OSC_IN 0
#define GPIOH_OSC_OUT 1
/*
* I/O ports initial setup, this configuration is established soon after reset
* in the initialization code.
* Please refer to the STM32 Reference Manual for details.
*/
#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2))
#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2))
#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2))
#define PIN_AFIO_AF(n, v) ((v##U) << (((n) % 8) * 4))
/*
* Port A setup.
*
* Values are taked from runnig ECU with stock FW
* > mdw 0x40020000 10
* 0x40020000: 2aa8ffff 00000000 0ffc0000 24000000 00005f00 00000000 00000000 00000000
* 0x40020020: 00000000 00099770
* TODO: decode
*/
#define VAL_GPIOA_MODER (0x2aa8ffff)
#define VAL_GPIOA_OTYPER (0x00000000)
#define VAL_GPIOA_OSPEEDR (0x0ffc0000)
#define VAL_GPIOA_PUPDR (0x24000000)
#define VAL_GPIOA_ODR (0x00000000)
#define VAL_GPIOA_AFRL (0x00000000)
#define VAL_GPIOA_AFRH (0x00099770)
/*
* Port B setup.
*
* Values are taked from runnig ECU with stock FW
* > mdw 0x40020400 10
* 0x40020400: 102a018f 00004300 200a00c0 00000010 00000108 00000000 00000000 00000000
* 0x40020420: 00000000 00000133
* TODO: decode
*
* PB4 - LDO2_EN (Output, 1).
*
*/
#define VAL_GPIOB_MODER (0x102a018f)
#define VAL_GPIOB_OTYPER (0x00004300)
#define VAL_GPIOB_OSPEEDR (0x200a00c0)
#define VAL_GPIOB_PUPDR (0x00000010)
#define VAL_GPIOB_ODR (0x00000010)
#define VAL_GPIOB_AFRL (0x00000000)
#define VAL_GPIOB_AFRH (0x00000133)
/*
* Port C setup.
*
* Values are taked from runnig ECU with stock FW
* > mdw 0x40020800 10
* 0x40020800: 0000afff 000000c0 0000a000 00004000 0000d400 00000000 00000000 00000000
* 0x40020820: 22000000 00000000
* TODO: decode
*/
#define VAL_GPIOC_MODER (0x0000afff)
#define VAL_GPIOC_OTYPER (0x000000c0)
#define VAL_GPIOC_OSPEEDR (0x0000a000)
#define VAL_GPIOC_PUPDR (0x00004000)
#define VAL_GPIOC_ODR (0x00000000)
#define VAL_GPIOC_AFRL (0x22000000)
#define VAL_GPIOC_AFRH (0x00000000)
/*
* Port D setup.
*
* Values are taked from runnig ECU with stock FW
* > mdw 0x40020c00 10
* 0x40020c00: 55551111 00003f55 00aa2022 00000000 00000000 00000010 00000000 00000000
* 0x40020c20: 00000000 00000000
* TODO: decode
*/
#define VAL_GPIOD_MODER (0x55551111)
#define VAL_GPIOD_OTYPER (0x00003f55)
#define VAL_GPIOD_OSPEEDR (0x00aa2022)
#define VAL_GPIOD_PUPDR (0x00000000)
#define VAL_GPIOD_ODR (0x00000010)
#define VAL_GPIOD_AFRL (0x00000000)
#define VAL_GPIOD_AFRH (0x00000000)
/*
* Port E setup.
*
* Values are taked from runnig ECU with stock FW
* > mdw 0x40021000 10
* 0x40021000: 11111501 00005471 22202802 00000000 00000000 00001010 00000000 00000000
* 0x40021020: 00000000 00000000
* TODO: decode
*/
#define VAL_GPIOE_MODER (0x11111501)
#define VAL_GPIOE_OTYPER (0x00005471)
#define VAL_GPIOE_OSPEEDR (0x22202802)
#define VAL_GPIOE_PUPDR (0x00000000)
#define VAL_GPIOE_ODR (0x00001010)
#define VAL_GPIOE_AFRL (0x00000000)
#define VAL_GPIOE_AFRH (0x00000000)
/*
* Port F setup.
*
* Pins are not present on LQFP100
* All input with pull-up.
*/
#define VAL_GPIOF_MODER 0x00000000
#define VAL_GPIOF_OTYPER 0x00000000
#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF
#define VAL_GPIOF_PUPDR (PIN_PUDR_PULLUP(0) | \
PIN_PUDR_PULLUP(1) | \
PIN_PUDR_PULLUP(2) | \
PIN_PUDR_PULLUP(3) | \
PIN_PUDR_PULLUP(4) | \
PIN_PUDR_PULLUP(5) | \
PIN_PUDR_PULLUP(6) | \
PIN_PUDR_PULLUP(7) | \
PIN_PUDR_PULLUP(8) | \
PIN_PUDR_PULLUP(9) | \
PIN_PUDR_PULLUP(10) | \
PIN_PUDR_PULLUP(11) | \
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLUP(13) | \
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOF_ODR 0xFFFFFFFF
#define VAL_GPIOF_AFRL 0x00000000
#define VAL_GPIOF_AFRH 0x00000000
/*
* Port G setup.
*
* Pins are not present on LQFP100
* All input with pull-up.
*/
#define VAL_GPIOG_MODER 0x00000000
#define VAL_GPIOG_OTYPER 0x00000000
#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF
#define VAL_GPIOG_PUPDR (PIN_PUDR_PULLUP(0) | \
PIN_PUDR_PULLUP(1) | \
PIN_PUDR_PULLUP(2) | \
PIN_PUDR_PULLUP(3) | \
PIN_PUDR_PULLUP(4) | \
PIN_PUDR_PULLUP(5) | \
PIN_PUDR_PULLUP(6) | \
PIN_PUDR_PULLUP(7) | \
PIN_PUDR_PULLUP(8) | \
PIN_PUDR_PULLUP(9) | \
PIN_PUDR_PULLUP(10) | \
PIN_PUDR_PULLUP(11) | \
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLUP(13) | \
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOG_ODR 0xFFFFFFFF
#define VAL_GPIOG_AFRL 0x00000000
#define VAL_GPIOG_AFRH 0x00000000
/*
* Port H setup.
*
* All input with pull-up except:
* PH0 - GPIOH_OSC_IN (input floating).
* PH1 - GPIOH_OSC_OUT (input floating).
*/
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
PIN_MODE_INPUT(2) | \
PIN_MODE_INPUT(3) | \
PIN_MODE_INPUT(4) | \
PIN_MODE_INPUT(5) | \
PIN_MODE_INPUT(6) | \
PIN_MODE_INPUT(7) | \
PIN_MODE_INPUT(8) | \
PIN_MODE_INPUT(9) | \
PIN_MODE_INPUT(10) | \
PIN_MODE_INPUT(11) | \
PIN_MODE_INPUT(12) | \
PIN_MODE_INPUT(13) | \
PIN_MODE_INPUT(14) | \
PIN_MODE_INPUT(15))
#define VAL_GPIOH_OTYPER 0x00000000
#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF
#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \
PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \
PIN_PUDR_PULLUP(2) | \
PIN_PUDR_PULLUP(3) | \
PIN_PUDR_PULLUP(4) | \
PIN_PUDR_PULLUP(5) | \
PIN_PUDR_PULLUP(6) | \
PIN_PUDR_PULLUP(7) | \
PIN_PUDR_PULLUP(8) | \
PIN_PUDR_PULLUP(9) | \
PIN_PUDR_PULLUP(10) | \
PIN_PUDR_PULLUP(11) | \
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLUP(13) | \
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOH_ODR 0xFFFFFFFF
#define VAL_GPIOH_AFRL 0x00000000
#define VAL_GPIOH_AFRH 0x00000000
/*
* Port I setup.
*
* Pins are not present on LQFP100
* All input with pull-up.
*/
#define VAL_GPIOI_MODER 0x00000000
#define VAL_GPIOI_OTYPER 0x00000000
#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF
#define VAL_GPIOI_PUPDR (PIN_PUDR_PULLUP(0) | \
PIN_PUDR_PULLUP(1) | \
PIN_PUDR_PULLUP(2) | \
PIN_PUDR_PULLUP(3) | \
PIN_PUDR_PULLUP(4) | \
PIN_PUDR_PULLUP(5) | \
PIN_PUDR_PULLUP(6) | \
PIN_PUDR_PULLUP(7) | \
PIN_PUDR_PULLUP(8) | \
PIN_PUDR_PULLUP(9) | \
PIN_PUDR_PULLUP(10) | \
PIN_PUDR_PULLUP(11) | \
PIN_PUDR_PULLUP(12) | \
PIN_PUDR_PULLUP(13) | \
PIN_PUDR_PULLUP(14) | \
PIN_PUDR_PULLUP(15))
#define VAL_GPIOI_ODR 0xFFFFFFFF
#define VAL_GPIOI_AFRL 0x00000000
#define VAL_GPIOI_AFRH 0x00000000
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
#endif
void boardInit(void);
#ifdef __cplusplus
}
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */

15
firmware/config/boards/s105/board.mk
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@ -5,8 +5,23 @@ HALCONFDIR = $(BOARD_DIR)
# List of all the board related files.
BOARDCPPSRC = $(BOARD_DIR)/board_configuration.cpp
# This is S105 board
DDEFS += -DSHORT_BOARD_NAME=s105
# This board has no LSE and HSE oscillators
DDEFS += -DSTM32_HSE_ENABLED=FALSE
DDEFS += -DENABLE_AUTO_DETECT_HSE=FALSE
# This board has 512K STM32F407
DDEFS += -DMIN_FLASH_SIZE=512
#This board has no LED
DDEFS += -DLED_CRITICAL_ERROR_BRAIN_PIN=Gpio::Unassigned
# and no LCD
DDEFS += -DEFI_HD44780_LCD=FALSE
# No Lua support as we are limited in RAM and ROM
DDEFS += -DEFI_LUA=FALSE
#This board has no USB wired out
DDEFS += -DSTM32_USB_USE_OTG1=FALSE

6
firmware/config/boards/s105/board_configuration.cpp
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@ -10,3 +10,9 @@ void setBoardDefaultConfiguration() {
engineConfiguration->runningLedPin = Gpio::Unassigned;
engineConfiguration->warningLedPin = Gpio::Unassigned;
}
void setBoardConfigOverrides() {
//CAN 1 bus overwrites
engineConfiguration->canRxPin = Gpio::A11;
engineConfiguration->canTxPin = Gpio::A12;
}

2
firmware/config/boards/s105/connectors/s105.yaml
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@ -167,7 +167,7 @@ pins:
- pin: 54a
function: GNDA (MAF)
- pin: 60a
- pin: 62a
function: CAN bus high
type: can