H7 ADC triggered by hardware timer (#3028)
* config * allow changing adc speed * timer triggered ADC * ICU on nucleo * turn that off too * 10khz * make those default for all h7 * I can't type
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Matthew Kennedy
GitHub
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09192cfc4d
commit
f70c844c60
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@ -34,3 +34,18 @@
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#undef ENABLE_PERF_TRACE
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#define ENABLE_PERF_TRACE TRUE
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// H7 runs faster "slow" ADC to make up for reduced oversampling
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#define SLOW_ADC_RATE 1000
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#undef EFI_ICU_INPUTS
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#define EFI_ICU_INPUTS FALSE
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#undef HAL_TRIGGER_USE_PAL
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#define HAL_TRIGGER_USE_PAL TRUE
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#undef EFI_LOGIC_ANALYZER
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#define EFI_LOGIC_ANALYZER FALSE
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#undef HAL_VSS_USE_PAL
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#define HAL_VSS_USE_PAL TRUE
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@ -11,7 +11,9 @@
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#include "global.h"
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#include "adc_math.h"
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#ifndef SLOW_ADC_RATE
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#define SLOW_ADC_RATE 500
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#endif
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static inline bool isAdcChannelValid(adc_channel_e hwChannel) {
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if (hwChannel <= EFI_ADC_NONE) {
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@ -25,10 +25,10 @@ float getMcuTemperature() {
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}
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// ADC Clock is 25MHz
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// 32.5 sampling + 8.5 conversion = 41 cycles per sample total
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// 16 channels * 16x oversample = 256 samples per batch
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// (41 * 256) / 25MHz -> 419 microseconds to sample all channels
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#define ADC_SAMPLING_SLOW ADC_SMPR_SMP_32P5
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// 16.5 sampling + 8.5 conversion = 25 cycles per sample total
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// 16 channels * 4x oversample = 64 samples per batch
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// (25 * 64) / 25MHz -> 64 microseconds to sample all channels
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#define ADC_SAMPLING_SLOW ADC_SMPR_SMP_16P5
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// Sample the 16 channels that line up with the STM32F4/F7
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constexpr size_t slowChannelCount = 16;
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@ -36,13 +36,13 @@ constexpr size_t slowChannelCount = 16;
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// Conversion group for slow channels
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// This simply samples every channel in sequence
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static constexpr ADCConversionGroup convGroupSlow = {
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.circular = FALSE,
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.circular = true, // Continuous mode means we will auto re-trigger on every timer event
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.num_channels = slowChannelCount,
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.end_cb = nullptr,
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.error_cb = nullptr,
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.cfgr = 0,
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.cfgr2 = 15 << ADC_CFGR2_OVSR_Pos | // Oversample by 16x (register contains N-1)
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4 << ADC_CFGR2_OVSS_Pos | // shift the result right 4 bits to make a 16 bit result
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.cfgr = ADC_CFGR_EXTEN_0 | (4 << ADC_CFGR_EXTSEL_Pos), // External trigger ch4, rising edge: TIM3 TRGO
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.cfgr2 = 3 << ADC_CFGR2_OVSR_Pos | // Oversample by 4x (register contains N-1)
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2 << ADC_CFGR2_OVSS_Pos | // shift the result right 2 bits to make a 16 bit result out of the 18 bit internal sum (4x oversampled)
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ADC_CFGR2_ROVSE, // Enable oversampling
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.ccr = 0,
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.pcsel = 0xFFFFFFFF, // enable analog switches on all channels
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@ -93,10 +93,36 @@ static constexpr ADCConversionGroup convGroupSlow = {
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},
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};
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static bool didStart = false;
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bool readSlowAnalogInputs(adcsample_t* convertedSamples) {
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// Oversampling and right-shift happen in hardware, so we can sample directly to the output buffer
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msg_t result = adcConvert(&ADCD1, &convGroupSlow, convertedSamples, 1);
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// This only needs to happen once, as the timer will continue firing the ADC and writing to the buffer without our help
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if (didStart) {
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return true;
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}
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didStart = true;
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{
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chibios_rt::CriticalSectionLocker csl;
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// Oversampling and right-shift happen in hardware, so we can sample directly to the output buffer
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adcStartConversionI(&ADCD1, &convGroupSlow, convertedSamples, 1);
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}
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constexpr uint32_t samplingRate = 10000;
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constexpr uint32_t timerCountFrequency = samplingRate * 100;
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constexpr uint32_t timerPeriod = timerCountFrequency / samplingRate;
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static constexpr GPTConfig gptCfg = {
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timerCountFrequency,
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nullptr,
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TIM_CR2_MMS_1, // TRGO on update event
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0
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};
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// Start timer
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gptStart(&GPTD3, &gptCfg);
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gptStartContinuous(&GPTD3, timerPeriod);
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// Return true if OK
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return result == MSG_OK;
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return true;
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}
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@ -67,7 +67,7 @@
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* @brief Enables the ICU subsystem.
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*/
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#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
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#define HAL_USE_ICU TRUE
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#define HAL_USE_ICU FALSE
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#endif
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/**
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@ -264,7 +264,7 @@
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*/
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#define STM32_GPT_USE_TIM1 FALSE
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#define STM32_GPT_USE_TIM2 FALSE
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#define STM32_GPT_USE_TIM3 FALSE
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#define STM32_GPT_USE_TIM3 TRUE
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#define STM32_GPT_USE_TIM4 FALSE
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#define STM32_GPT_USE_TIM5 FALSE
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#define STM32_GPT_USE_TIM6 TRUE
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@ -306,9 +306,9 @@
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/*
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* ICU driver system settings.
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*/
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#define STM32_ICU_USE_TIM1 TRUE
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#define STM32_ICU_USE_TIM2 TRUE
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#define STM32_ICU_USE_TIM3 TRUE
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#define STM32_ICU_USE_TIM1 FALSE
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#define STM32_ICU_USE_TIM2 FALSE
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#define STM32_ICU_USE_TIM3 FALSE
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#define STM32_ICU_USE_TIM4 FALSE
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#define STM32_ICU_USE_TIM5 FALSE
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#define STM32_ICU_USE_TIM8 FALSE
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