rusefi/firmware/hw_layer/ports
Andrey Gusakov 13a02795a6 pins: SPI use common names
Master output -> MOSI, Master input -> MISO, clock -> CLK
2025-02-13 13:23:13 -05:00
..
at32 pins: SPI use common names 2025-02-13 13:23:13 -05:00
cypress pins: SPI use common names 2025-02-13 13:23:13 -05:00
kinetis pins: SPI use common names 2025-02-13 13:23:13 -05:00
stm32 pins: SPI use common names 2025-02-13 13:23:13 -05:00
arm_common.cpp
chconf_common.h only:fancy! 2024-05-24 12:26:42 -04:00
mpu_util.h stm32_reset_cause: handle POR/PDR reset cause 2025-01-22 08:29:49 -05:00
mpu_watchdog.h fix watchdog https://github.com/rusefi/rusefi/issues/1339 2025-01-23 16:38:21 -05:00
rusefi_halconf.h stm32 own build-in watchdog #1339 2025-02-12 18:29:58 -05:00