319 lines
6.1 KiB
C
319 lines
6.1 KiB
C
/*
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* @file rusefi_hw_enums.h
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*
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* @date Jun 2, 2019
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* @author Andrey Belomutskiy, (c) 2012-2020
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*/
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#pragma once
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// todo: migrate/unify with pin_output_mode_e? rename? something is messy here
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// this enum is currently only used for SPI pins
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typedef enum __attribute__ ((__packed__)) {
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// todo: here we have a rare example of stm32-specific enum, todo: make this not stm32 specific?
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PO_DEFAULT = 0,
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PO_OPENDRAIN = 4, // PAL_STM32_OTYPE_OPENDRAIN
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PO_PULLUP = 32, // PAL_STM32_PUDR_PULLUP
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PO_PULLDOWN = 64 // PAL_STM32_PUPDR_PULLDOWN
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} pin_mode_e;
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/**
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* Hardware pin. This enum is platform-specific.
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*/
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typedef enum __attribute__ ((__packed__)) {
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GPIO_UNASSIGNED = 0,
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// only used as return value of 'parseBrainPin' function do we really this this logic special value at all?!
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GPIO_INVALID = 1,
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GPIOA_0 = 2,
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GPIOA_1 = 3,
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GPIOA_2 = 4,
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GPIOA_3 = 5,
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GPIOA_4 = 6,
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GPIOA_5 = 7,
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GPIOA_6 = 8,
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GPIOA_7 = 9,
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GPIOA_8 = 10,
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GPIOA_9 = 11,
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GPIOA_10 = 12,
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GPIOA_11 = 13,
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GPIOA_12 = 14,
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GPIOA_13 = 15,
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GPIOA_14 = 16,
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GPIOA_15 = 17,
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GPIOB_0 = 18,
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GPIOB_1 = 19,
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GPIOB_2 = 20,
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GPIOB_3 = 21,
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GPIOB_4 = 22,
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GPIOB_5 = 23,
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GPIOB_6 = 24,
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GPIOB_7 = 25,
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GPIOB_8 = 26,
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GPIOB_9 = 27,
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GPIOB_10 = 28,
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GPIOB_11 = 29,
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GPIOB_12 = 30,
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GPIOB_13 = 31,
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GPIOB_14 = 32,
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GPIOB_15 = 33,
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GPIOC_0 = 34,
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GPIOC_1 = 35,
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GPIOC_2 = 36,
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GPIOC_3 = 37,
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GPIOC_4 = 38,
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GPIOC_5 = 39,
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GPIOC_6 = 40,
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GPIOC_7 = 41,
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GPIOC_8 = 42,
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GPIOC_9 = 43,
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GPIOC_10 = 44,
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GPIOC_11 = 45,
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GPIOC_12 = 46,
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GPIOC_13 = 47,
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GPIOC_14 = 48,
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GPIOC_15 = 49,
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GPIOD_0 = 50,
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GPIOD_1 = 51,
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GPIOD_2 = 52,
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GPIOD_3 = 53,
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GPIOD_4 = 54,
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GPIOD_5 = 55,
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GPIOD_6 = 56,
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GPIOD_7 = 57,
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GPIOD_8 = 58,
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GPIOD_9 = 59,
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GPIOD_10 = 60,
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GPIOD_11 = 61,
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GPIOD_12 = 62,
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GPIOD_13 = 63,
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GPIOD_14 = 64,
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GPIOD_15 = 65,
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GPIOE_0 = 66,
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GPIOE_1 = 67,
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GPIOE_2 = 68,
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GPIOE_3 = 69,
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GPIOE_4 = 70,
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GPIOE_5 = 71,
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GPIOE_6 = 72,
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GPIOE_7 = 73,
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GPIOE_8 = 74,
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GPIOE_9 = 75,
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GPIOE_10 = 76,
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GPIOE_11 = 77,
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GPIOE_12 = 78,
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GPIOE_13 = 79,
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GPIOE_14 = 80,
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GPIOE_15 = 81,
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GPIOF_0 = 82,
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GPIOF_1 = 83,
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GPIOF_2 = 84,
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GPIOF_3 = 85,
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GPIOF_4 = 86,
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GPIOF_5 = 87,
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GPIOF_6 = 88,
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GPIOF_7 = 89,
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GPIOF_8 = 90,
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GPIOF_9 = 91,
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GPIOF_10 = 92,
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GPIOF_11 = 93,
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GPIOF_12 = 94,
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GPIOF_13 = 95,
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GPIOF_14 = 96,
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GPIOF_15 = 97,
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GPIOG_0 = 98,
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GPIOG_1 = 99,
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GPIOG_2 = 100,
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GPIOG_3 = 101,
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GPIOG_4 = 102,
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GPIOG_5 = 103,
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GPIOG_6 = 104,
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GPIOG_7 = 105,
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GPIOG_8 = 106,
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GPIOG_9 = 107,
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GPIOG_10 = 108,
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GPIOG_11 = 109,
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GPIOG_12 = 110,
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GPIOG_13 = 111,
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GPIOG_14 = 112,
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GPIOG_15 = 113,
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GPIOH_0 = 114,
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GPIOH_1 = 115,
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GPIOH_2 = 116,
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GPIOH_3 = 117,
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GPIOH_4 = 118,
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GPIOH_5 = 119,
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GPIOH_6 = 120,
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GPIOH_7 = 121,
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GPIOH_8 = 122,
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GPIOH_9 = 123,
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GPIOH_10 = 124,
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GPIOH_11 = 125,
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GPIOH_12 = 126,
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GPIOH_13 = 127,
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GPIOH_14 = 128,
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GPIOH_15 = 129,
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/* Used by 176-pin STM32 MCUs */
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GPIOI_0 = 130,
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GPIOI_1 = 131,
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GPIOI_2 = 132,
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GPIOI_3 = 133,
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GPIOI_4 = 134,
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GPIOI_5 = 135,
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GPIOI_6 = 136,
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GPIOI_7 = 137,
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GPIOI_8 = 138,
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GPIOI_9 = 139,
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GPIOI_10 = 140,
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GPIOI_11 = 141,
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GPIOI_12 = 142,
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GPIOI_13 = 143,
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GPIOI_14 = 144,
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GPIOI_15 = 145,
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/* MC33972 pins go right after on_chip pins */
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MC33972_PIN_1 = 146,
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MC33972_PIN_21 = 166,
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MC33972_PIN_22 = 167,
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TLE8888_PIN_1 = 168,
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TLE8888_PIN_2 = 169,
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TLE8888_PIN_3 = 170,
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TLE8888_PIN_4 = 171,
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TLE8888_PIN_5 = 172,
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TLE8888_PIN_6 = 173,
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TLE8888_PIN_7 = 174,
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TLE8888_PIN_8 = 175,
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TLE8888_PIN_9 = 176,
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TLE8888_PIN_10 = 177,
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TLE8888_PIN_11 = 178,
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TLE8888_PIN_12 = 179,
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TLE8888_PIN_13 = 180,
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TLE8888_PIN_14 = 181,
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TLE8888_PIN_15 = 182,
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TLE8888_PIN_16 = 183,
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TLE8888_PIN_17 = 184,
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TLE8888_PIN_18 = 185,
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TLE8888_PIN_19 = 186,
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TLE8888_PIN_20 = 187,
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TLE8888_PIN_21 = 188,
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TLE8888_PIN_22 = 189,
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TLE8888_PIN_23 = 190,
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TLE8888_PIN_24 = 191,
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TLE8888_PIN_25 = 192,
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TLE8888_PIN_26 = 193,
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TLE8888_PIN_27 = 194,
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TLE8888_PIN_28 = 195,
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TLE8888_PIN_MR = 196,
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TLE8888_PIN_KEY = 197,
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TLE8888_PIN_WAKE = 198,
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/* TLE6240 pins */
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TLE6240_PIN_1 = 199,
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TLE6240_PIN_2 = 200,
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TLE6240_PIN_3 = 201,
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TLE6240_PIN_4 = 202,
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TLE6240_PIN_5 = 203,
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TLE6240_PIN_6 = 204,
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TLE6240_PIN_7 = 205,
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TLE6240_PIN_8 = 206,
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TLE6240_PIN_9 = 207,
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TLE6240_PIN_10 = 208,
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TLE6240_PIN_11 = 209,
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TLE6240_PIN_12 = 210,
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TLE6240_PIN_13 = 211,
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TLE6240_PIN_14 = 212,
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TLE6240_PIN_15 = 213,
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TLE6240_PIN_16 = 214,
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/* L9779 */
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L9779_IGN_1 = 215,
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L9779_IGN_2 = 216,
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L9779_IGN_3 = 217,
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L9779_IGN_4 = 218,
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L9779_OUT_1 = 219,
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L9779_OUT_2 = 220,
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L9779_OUT_3 = 221,
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L9779_OUT_4 = 222,
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L9779_OUT_5 = 223,
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L9779_OUT_6 = 224,
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L9779_OUT_7 = 225,
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L9779_OUT_8 = 226,
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L9779_OUT_9 = 227,
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L9779_OUT_10 = 228,
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L9779_OUT_11 = 229,
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L9779_OUT_12 = 230,
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L9779_OUT_13 = 231,
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L9779_OUT_14 = 232,
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L9779_OUT_15 = 233,
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L9779_OUT_16 = 234,
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L9779_OUT_17 = 235,
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L9779_OUT_18 = 236,
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L9779_OUT_19 = 237,
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L9779_OUT_20 = 238,
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L9779_OUT_A = 239,
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L9779_OUT_B = 240,
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L9779_OUT_C = 241,
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L9779_OUT_D = 242,
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L9779_OUT_25 = 243,
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L9779_OUT_26 = 244,
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L9779_OUT_27 = 245,
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L9779_OUT_28 = 246,
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L9779_OUT_MRD = 247,
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L9779_PIN_KEY = 248,
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} brain_pin_e;
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/* Please keep updating these defines */
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#define BRAIN_PIN_ONCHIP_LAST GPIOI_15
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#define BRAIN_PIN_ONCHIP_PINS (BRAIN_PIN_ONCHIP_LAST - GPIOA_0 + 1)
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#define BRAIN_PIN_LAST L9779_PIN_KEY
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#define BRAIN_PIN_TOTAL_PINS (BRAIN_PIN_LAST - GPIOA_0 + 1)
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/**
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* Frankenso analog #1 PC2 ADC12
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* Frankenso analog #2 PC1 ADC11
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* Frankenso analog #3 PA0 ADC0
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* Frankenso analog #4 PC3 ADC13
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* Frankenso analog #5 PA2 ADC2
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* Frankenso analog #6 PA1 ADC1
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* Frankenso analog #7 PA4 ADC4
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* Frankenso analog #8 PA3 ADC3
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* Frankenso analog #9 PA7 ADC7
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* Frankenso analog #10 PA6 ADC6
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* Frankenso analog #11 PC5 ADC15
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* Frankenso analog #12 PC4 ADC14
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*/
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typedef enum __attribute__ ((__packed__)) {
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EFI_ADC_NONE = 0,
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EFI_ADC_0 = 1, // PA0
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EFI_ADC_1 = 2, // PA1
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EFI_ADC_2 = 3, // PA2
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EFI_ADC_3 = 4, // PA3
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EFI_ADC_4 = 5, // PA4
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EFI_ADC_5 = 6, // PA5
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EFI_ADC_6 = 7, // PA6
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EFI_ADC_7 = 8, // PA7
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EFI_ADC_8 = 9, // PB0
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EFI_ADC_9 = 10, // PB1
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EFI_ADC_10 = 11, // PC0
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EFI_ADC_11 = 12, // PC1
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EFI_ADC_12 = 13, // PC2
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EFI_ADC_13 = 14, // PC3
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EFI_ADC_14 = 15, // PC4
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EFI_ADC_15 = 16, // PC5
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EFI_ADC_LAST_CHANNEL = 17, // Please keep this in sync with the last valid channel index!
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EFI_ADC_ERROR = 50,
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} adc_channel_e;
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