561 lines
12 KiB
C++
561 lines
12 KiB
C++
#include "pch.h"
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#include "gpio/gpio_ext.h"
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#include "gpio/tle9104.h"
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#if defined(BOARD_TLE9104_COUNT) && BOARD_TLE9104_COUNT > 0
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/*
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* TODO list:
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* - support driving outputs over SPI
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* - count communication errors, POR events, etc
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* - support WD functionality
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* - implement direct-io mapping test. Check if user provides correct direct_io data
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*/
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/*==========================================================================*/
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/* Driver local definitions. */
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/*==========================================================================*/
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#define DRIVER_NAME "tle9104"
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/* TODO: aling with WD settings */
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#define TLE9104_POLL_INTERVAL_MS 100
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static bool drv_task_ready = false;
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typedef enum {
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TLE9104_DISABLED = 0,
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TLE9104_WAIT_INIT,
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TLE9104_READY,
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TLE9104_FAILED
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} tle9104_drv_state;
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/* IN MOSI and MISO a read is defined with a s0 and a write is defined with a 1. */
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#define TLE9104_WR_REG(addr, val) (BIT(15) | (((addr) & 0x0f) << 8) | ((val) & 0xff))
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#define TLE9104_RD_REG(addr) (((addr) & 0x0f) << 8)
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#define TLE9104_GET_VAL(rx) ((rx) & 0xff)
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#define TLE9104_GET_ADDR(rx) (((rx) >> 8) & 0x0f)
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#define TLE9104_PARITY_MASK(val) ((val) & (~BIT(14)))
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#define TLE9104_FAULT_GLOBAL BIT(12)
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#define TLE9104_FAULT_COMM BIT(13)
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#define TLE9104_REG_CTRL 0x00
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#define TLE9104_REG_CFG 0x01
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#define TLE9104_REG_OFF_DIAG_CFG 0x02
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#define TLE9104_REG_ON_DIAG_CFG 0x03
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#define TLE9104_REG_DIAG_OUT_1_2_ON 0x04
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#define TLE9104_REG_DIAG_OUT_3_4_ON 0x05
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#define TLE9104_REG_DIAG_OFF 0x06
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#define TLE9104_REG_GLOBAL_STATUS 0x07
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#define TLE9104_REG_ICVID 0x08
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/*==========================================================================*/
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/* Driver exported variables. */
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/*==========================================================================*/
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/*==========================================================================*/
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/* Driver local variables and types. */
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/*==========================================================================*/
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struct Tle9104 : public GpioChip {
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int init() override;
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int writePad(size_t pin, int value) override;
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brain_pin_diag_e getDiag(size_t pin) override;
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void debug() override;
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int updateDiagState();
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int updateStatus();
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const tle9104_config* cfg;
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tle9104_drv_state drv_state;
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private:
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int spi_validate(uint16_t rx);
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int spi_rw_array(const uint16_t *tx, uint16_t *rx, int n);
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int spi_rw(uint16_t tx, uint16_t *rx);
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int read_reg(uint8_t addr, uint8_t *val);
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int write_reg(uint8_t addr, uint8_t val);
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int chip_init();
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OutputPin m_en;
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OutputPin m_resn;
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/* diagnostic registers */
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uint8_t diag_off;
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uint8_t diag_on12;
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uint8_t diag_on34;
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/* statistic */
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int por_cnt;
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int wdr_cnt;
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int init_req_cnt;
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int fault_cnt;
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int fault_comm_cnt;
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int spi_address_err_cnt;
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int spi_cnt;
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int spi_parity_err_cnt;
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};
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static Tle9104 chips[BOARD_TLE9104_COUNT];
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/*==========================================================================*/
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/* Driver local functions. */
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/*==========================================================================*/
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static bool parityBit(uint16_t val) {
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// (1 + number of bits set) mod 2 = parity bit
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int count = 1 + __builtin_popcount(val);
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return count % 2;
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#if 0
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while (val != 0) {
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if (val & 0x01) {
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count++;
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}
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val = val >> 1;
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}
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return (count % 2) == 1;
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#endif
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}
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int Tle9104::spi_validate(uint16_t rx)
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{
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/* with parity bit included */
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bool parityOk = !parityBit(rx);
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if (!parityOk) {
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spi_parity_err_cnt++;
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return -1;
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}
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if (rx & TLE9104_FAULT_GLOBAL) {
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fault_cnt++;
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}
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if (rx & TLE9104_FAULT_COMM) {
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fault_comm_cnt++;
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}
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return 0;
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}
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int Tle9104::spi_rw(uint16_t tx, uint16_t *rx) {
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SPIDriver *spi = cfg->spi_bus;
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spi_cnt++;
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// set the parity bit appropriately
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tx |= parityBit(tx) << 14;
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/* Acquire ownership of the bus. */
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spiAcquireBus(spi);
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/* Setup transfer parameters. */
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spiStart(spi, &cfg->spi_config);
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/* Slave Select assertion. */
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spiSelect(spi);
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/* Atomic transfer operations. */
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uint16_t rxd = spiPolledExchange(spi, tx);
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/* Slave Select de-assertion. */
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spiUnselect(spi);
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/* Ownership release. */
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spiReleaseBus(spi);
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/* with parity bit included */
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int ret = spi_validate(rxd);
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if (ret < 0) {
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return ret;
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}
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/* TODO: check Fault Global and Fault Communication flags */
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// return data
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if (rx) {
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*rx = rxd;
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}
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return 0;
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}
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int Tle9104::spi_rw_array(const uint16_t *tx, uint16_t *rx, int n)
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{
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int ret = 0;
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SPIDriver *spi = cfg->spi_bus;
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if ((n <= 0) || (tx == nullptr)) {
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return -2;
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}
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/* Acquire ownership of the bus. */
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spiAcquireBus(spi);
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/* Setup transfer parameters. */
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spiStart(spi, &cfg->spi_config);
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for (int i = 0; i < n; i++) {
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spi_cnt++;
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/* Slave Select assertion. */
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spiSelect(spi);
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/* data transfer */
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uint16_t rxdata = spiPolledExchange(spi, tx[i]);
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if (rx)
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rx[i] = rxdata;
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/* Slave Select de-assertion. */
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spiUnselect(spi);
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/* validate reply */
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ret = spi_validate(rxdata);
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if (ret < 0)
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break;
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if (i >= 1) {
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/* validate that we received correct answer to previous tx */
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if (TLE9104_GET_ADDR(tx[i - 1] != TLE9104_GET_ADDR(rxdata))) {
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spi_address_err_cnt++;
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ret = -2;
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break;
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}
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}
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}
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/* Ownership release. */
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spiReleaseBus(spi);
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/* no errors for now */
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return ret;
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}
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int Tle9104::read_reg(uint8_t addr, uint8_t *val) {
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int ret;
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ret = spi_rw(TLE9104_RD_REG(addr), nullptr);
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if (ret) {
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return ret;
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}
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uint16_t rxd;
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ret = spi_rw(TLE9104_RD_REG(addr), &rxd);
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if (ret) {
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return ret;
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}
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if (val) {
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*val = TLE9104_GET_VAL(rxd);
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}
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return 0;
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}
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int Tle9104::write_reg(uint8_t addr, uint8_t val) {
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// R/W bit is 1 for write
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return spi_rw(TLE9104_WR_REG(addr, val), nullptr);
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}
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int Tle9104::chip_init() {
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int ret;
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init_req_cnt++;
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// disable comms watchdog, enable direct drive on all 4 channels
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// TODO: should we enable comms watchdog?
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ret = write_reg(TLE9104_REG_CFG, 0x0F);
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if (ret) {
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return ret;
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}
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// clear any suprious diag states from startup: first call resets, second reads true state
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ret = updateDiagState();
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if (ret) {
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return ret;
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}
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ret = updateDiagState();
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if (ret) {
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return ret;
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}
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// set output enable, clear all other flags
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ret = write_reg(TLE9104_REG_GLOBAL_STATUS, BIT(7));
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if (ret) {
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return ret;
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}
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drv_state = TLE9104_READY;
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return 0;
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}
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/*==========================================================================*/
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/* Driver thread. */
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/*==========================================================================*/
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SEMAPHORE_DECL(tle9104_wake, 10 /* or BOARD_TLE9104_COUNT ? */);
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static THD_WORKING_AREA(tle9104_thread_1_wa, 256);
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static THD_FUNCTION(tle9104_driver_thread, p)
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{
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int i;
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msg_t msg;
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(void)p;
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chRegSetThreadName(DRIVER_NAME);
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while(1) {
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msg = chSemWaitTimeout(&tle9104_wake, TIME_MS2I(TLE9104_POLL_INTERVAL_MS));
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/* should we care about msg == MSG_TIMEOUT? */
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(void)msg;
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for (i = 0; i < BOARD_TLE9104_COUNT; i++) {
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int ret;
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Tle9104& chip = chips[i];
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if (!chip.cfg ||
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(chip.drv_state == TLE9104_DISABLED) ||
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(chip.drv_state == TLE9104_FAILED))
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continue;
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ret = chip.updateDiagState();
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if (ret) {
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/* set state to TLE6240_FAILED? */
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}
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ret = chip.updateStatus();
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if (ret) {
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/* set state to TLE6240_FAILED? */
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}
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}
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}
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}
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/*==========================================================================*/
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/* Driver exported functions. */
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/*==========================================================================*/
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int Tle9104::writePad(size_t pin, int value) {
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// Inverted since TLE9104 is active low (low level to turn on output)
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if (value) {
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palClearPad(cfg->direct_io[pin].port, cfg->direct_io[pin].pad);
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} else {
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palSetPad(cfg->direct_io[pin].port, cfg->direct_io[pin].pad);
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}
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return 0;
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}
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int Tle9104::updateDiagState() {
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int ret;
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/* TODO: implement and use spi_rw_array() */
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ret = read_reg(TLE9104_REG_DIAG_OUT_1_2_ON, &diag_on12);
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if (ret) {
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return ret;
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}
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ret = read_reg(TLE9104_REG_DIAG_OUT_3_4_ON, &diag_on34);
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if (ret) {
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return ret;
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}
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ret = read_reg(TLE9104_REG_DIAG_OFF, &diag_off);
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if (ret) {
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return ret;
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}
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// clear diag states
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ret = write_reg(TLE9104_REG_DIAG_OUT_1_2_ON, 0);
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if (ret) {
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return ret;
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}
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ret = write_reg(TLE9104_REG_DIAG_OUT_3_4_ON, 0);
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if (ret) {
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return ret;
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}
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ret = write_reg(TLE9104_REG_DIAG_OFF, 0);
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if (ret) {
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return ret;
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}
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return 0;
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}
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int Tle9104::updateStatus() {
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int ret;
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uint8_t status;
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ret = read_reg(TLE9104_REG_GLOBAL_STATUS, &status);
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if (ret) {
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return ret;
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}
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/* Device was reset since last cleared */
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if (status & BIT(0)) {
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por_cnt++;
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need_init = true;
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}
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/* Communication watchdog timeout occurred */
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if (status & BIT(2)) {
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wdr_cnt++;
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need_init = true;
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}
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if (need_init) {
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ret = chip_init();
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if (ret == 0) {
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need_init = false;
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}
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}
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return 0;
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}
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brain_pin_diag_e Tle9104::getDiag(size_t pin) {
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uint8_t off_diag;
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uint8_t on_diag;
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switch (pin) {
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case 0:
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on_diag = diag_on12;
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off_diag = diag_off;
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break;
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case 1:
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on_diag = diag_on12 >> 3;
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off_diag = diag_off >> 2;
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break;
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case 2:
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on_diag = diag_on34;
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off_diag = diag_off >> 4;
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break;
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case 3:
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on_diag = diag_on34 >> 3;
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off_diag = diag_off >> 6;
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break;
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default:
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return PIN_UNKNOWN;
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}
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// on diag has 3 bits
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on_diag = on_diag & 0x7;
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// of diag has 2 bits
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off_diag = off_diag & 0x3;
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int result = 0;
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// Decode on-state faults
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switch (on_diag) {
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case 2:
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result |= PIN_SHORT_TO_BAT;
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break;
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case 3:
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// overtemp and overcurrent
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result |= PIN_DRIVER_OVERTEMP;
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[[fallthrough]];
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case 4:
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result |= PIN_OVERLOAD;
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break;
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case 5:
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result |= PIN_DRIVER_OVERTEMP;
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break;
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}
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// Decode off-state faults
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switch (off_diag) {
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case 2:
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result |= PIN_OPEN;
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break;
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case 3:
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result |= PIN_SHORT_TO_GND;
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break;
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}
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return (brain_pin_diag_e)result;
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}
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void Tle9104::debug() {
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efiPrintf("spi transfers %d with patiry error %d with wrong address %d communication fault counter %d\n",
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spi_cnt, spi_parity_err_cnt, spi_address_err_cnt, fault_comm_cnt);
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efiPrintf("fault counter %d communication fault counter %d\n",
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fault_cnt, fault_comm_cnt);
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efiPrintf("POR counter %d reinit counter %d WD counter %d\n",
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por_cnt, init_req_cnt, wdr_cnt);
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}
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int Tle9104::init() {
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int ret;
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m_resn.initPin(DRIVER_NAME " RESN", cfg->resn);
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m_en.initPin(DRIVER_NAME " EN", cfg->en);
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// disable outputs
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m_en.setValue(false);
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// Reset the chip
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m_resn.setValue(false);
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/* TODO: ensure all direct_io pins valid, otherwise support manipulationg output states over SPI */
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for (int i = 0; i < 4; i++) {
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gpio_pin_markUsed(cfg->direct_io[i].port, cfg->direct_io[i].pad, DRIVER_NAME " Direct IO");
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palSetPadMode(cfg->direct_io[i].port, cfg->direct_io[i].pad, PAL_MODE_OUTPUT_PUSHPULL);
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// Ensure all outputs are off
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writePad(i, false);
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}
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if (isBrainPinValid(cfg->resn)) {
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chThdSleepMilliseconds(1);
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m_resn.setValue(true);
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chThdSleepMilliseconds(1);
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}
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// read ID register
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uint8_t id;
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ret = read_reg(TLE9104_REG_ICVID, &id);
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if (ret) {
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return ret;
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}
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// No chip detected if ID is wrong
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if (id != 0xB1) {
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return -1;
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}
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ret = chip_init();
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if (ret) {
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return ret;
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}
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// Set hardware enable
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m_en.setValue(true);
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if (!drv_task_ready) {
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chThdCreateStatic(tle9104_thread_1_wa, sizeof(tle9104_thread_1_wa),
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PRIO_GPIOCHIP, tle9104_driver_thread, nullptr);
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drv_task_ready = true;
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}
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return 0;
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}
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int tle9104_add(Gpio base, int index, const tle9104_config* cfg) {
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Tle9104& chip = chips[index];
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/* already added? */
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if (chip.cfg != NULL) {
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return -1;
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}
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chip.cfg = cfg;
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chip.drv_state = TLE9104_WAIT_INIT;
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return gpiochip_register(base, DRIVER_NAME, chip, 4);
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}
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#else // BOARD_TLE9104_COUNT > 0
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int tle9104_add(Gpio, int, const tle9104_config*) {
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return -1;
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}
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#endif // BOARD_TLE9104_COUNT
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