135 lines
3.6 KiB
C++
135 lines
3.6 KiB
C++
/**
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* @file at32_can.cpp
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* @brief Low level common AT32 code
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*
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* @date Nov 19, 2023
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* @author Andrey Gusakov, (c) 2023
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*/
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#include "pch.h"
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#if EFI_CAN_SUPPORT
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// Values below calculated with http://www.bittiming.can-wiki.info/
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// Pick ST micro bxCAN
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#if (STM32_PCLK1 == 144000000)
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// Clock rate of 144mhz for AT32F435
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// These have an 85.7% sample point
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// CAN_BTR_BRP - Baud Rate Prescaler
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// CAN_BTR_SJW - Resynchronization Jump Width
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// CAN_BTR_TS1 - Time Segment 1
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// CAN_BTR_TS2 - Time Segment 2
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#define CAN_BTR_50 (CAN_BTR_BRP(160 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1))
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#define CAN_BTR_83 (CAN_BTR_BRP(96 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1)) /* not accurate */
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#define CAN_BTR_100 (CAN_BTR_BRP(80 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1))
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#define CAN_BTR_125 (CAN_BTR_BRP(64 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1))
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#define CAN_BTR_250 (CAN_BTR_BRP(32 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1))
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#define CAN_BTR_500 (CAN_BTR_BRP(16 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1))
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#define CAN_BTR_1k0 (CAN_BTR_BRP(8 - 1) | CAN_BTR_SJW(18 - 1) | CAN_BTR_TS1(15 - 1) | CAN_BTR_TS2(2 - 1))
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#endif
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#define STM32FxMCR (CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP)
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static const CANConfig canConfig50 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_50
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};
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static const CANConfig canConfig83 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_83
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};
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static const CANConfig canConfig100 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_100
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};
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static const CANConfig canConfig125 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_125
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};
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static const CANConfig canConfig250 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_250
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};
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static const CANConfig canConfig500 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_500
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};
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static const CANConfig canConfig1000 = {
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.mcr = STM32FxMCR,
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.btr = CAN_BTR_1k0
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};
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static bool isValidCan1RxPin(brain_pin_e pin) {
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return pin == Gpio::A11 || pin == Gpio::B8 || pin == Gpio::D0 || pin == Gpio::G0;
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}
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static bool isValidCan1TxPin(brain_pin_e pin) {
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return pin == Gpio::A12 || pin == Gpio::B9 || pin == Gpio::D1 || pin == Gpio::G1;
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}
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static bool isValidCan2RxPin(brain_pin_e pin) {
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return pin == Gpio::B5 || pin == Gpio::B12 || pin == Gpio::G11;
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}
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static bool isValidCan2TxPin(brain_pin_e pin) {
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return pin == Gpio::B6 || pin == Gpio::B13 || pin == Gpio::G12;
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}
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bool isValidCanTxPin(brain_pin_e pin) {
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return isValidCan1TxPin(pin) || isValidCan2TxPin(pin);
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}
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bool isValidCanRxPin(brain_pin_e pin) {
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return isValidCan1RxPin(pin) || isValidCan2RxPin(pin);
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}
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CANDriver* detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx) {
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if (pinRx == Gpio::Unassigned || pinTx == Gpio::Unassigned) {
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return nullptr;
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}
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#if STM32_CAN_USE_CAN1 || STM32_CAN_USE_FDCAN1
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if (isValidCan1RxPin(pinRx) && isValidCan1TxPin(pinTx))
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return &CAND1;
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#endif
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#if STM32_CAN_USE_CAN2 || STM32_CAN_USE_FDCAN2
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if (isValidCan2RxPin(pinRx) && isValidCan2TxPin(pinTx))
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return &CAND2;
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#endif
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criticalError("invalid CAN pins tx %s and rx %s", hwPortname(pinTx), hwPortname(pinRx));
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return nullptr;
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}
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const CANConfig * findCanConfig(can_baudrate_e rate) {
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switch (rate) {
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case B50KBPS:
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return &canConfig50;
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case B83KBPS:
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return &canConfig83;
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case B100KBPS:
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return &canConfig100;
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case B125KBPS:
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return &canConfig125;
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case B250KBPS:
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return &canConfig250;
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case B1MBPS:
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return &canConfig1000;
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case B500KBPS:
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default:
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return &canConfig500;
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}
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}
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void canHwInfo(CANDriver* cand)
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{
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/* TODO: */
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(void)cand;
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}
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#endif /* EFI_CAN_SUPPORT */ |