SAM3S8 SMC
Static Memory Controller (SMC) User Interface
Registers
Address | Register | Name | Access | Reset |
---|---|---|---|---|
0x400E0000 | SMC Setup Register (CS_number = 0) | SMC_SETUP0 | read-write | 0x01010101 |
0x400E0004 | SMC Pulse Register (CS_number = 0) | SMC_PULSE0 | read-write | 0x01010101 |
0x400E0008 | SMC Cycle Register (CS_number = 0) | SMC_CYCLE0 | read-write | 0x00030003 |
0x400E000C | SMC Mode Register (CS_number = 0) | SMC_MODE0 | read-write | 0x10000003 |
0x400E0010 | SMC Setup Register (CS_number = 1) | SMC_SETUP1 | read-write | 0x01010101 |
0x400E0014 | SMC Pulse Register (CS_number = 1) | SMC_PULSE1 | read-write | 0x01010101 |
0x400E0018 | SMC Cycle Register (CS_number = 1) | SMC_CYCLE1 | read-write | 0x00030003 |
0x400E001C | SMC Mode Register (CS_number = 1) | SMC_MODE1 | read-write | 0x10000003 |
0x400E0020 | SMC Setup Register (CS_number = 2) | SMC_SETUP2 | read-write | 0x01010101 |
0x400E0024 | SMC Pulse Register (CS_number = 2) | SMC_PULSE2 | read-write | 0x01010101 |
0x400E0028 | SMC Cycle Register (CS_number = 2) | SMC_CYCLE2 | read-write | 0x00030003 |
0x400E002C | SMC Mode Register (CS_number = 2) | SMC_MODE2 | read-write | 0x10000003 |
0x400E0030 | SMC Setup Register (CS_number = 3) | SMC_SETUP3 | read-write | 0x01010101 |
0x400E0034 | SMC Pulse Register (CS_number = 3) | SMC_PULSE3 | read-write | 0x01010101 |
0x400E0038 | SMC Cycle Register (CS_number = 3) | SMC_CYCLE3 | read-write | 0x00030003 |
0x400E003C | SMC Mode Register (CS_number = 3) | SMC_MODE3 | read-write | 0x10000003 |
0x400E0040 | SMC Setup Register (CS_number = 4) | SMC_SETUP4 | read-write | 0x01010101 |
0x400E0044 | SMC Pulse Register (CS_number = 4) | SMC_PULSE4 | read-write | 0x01010101 |
0x400E0048 | SMC Cycle Register (CS_number = 4) | SMC_CYCLE4 | read-write | 0x00030003 |
0x400E004C | SMC Mode Register (CS_number = 4) | SMC_MODE4 | read-write | 0x10000003 |
0x400E0080 | SMC OCMS MODE Register | SMC_OCMS | read-write | 0x00000000 |
0x400E0084 | SMC OCMS KEY1 Register | SMC_KEY1 | write-only | 0x00000000 |
0x400E0088 | SMC OCMS KEY2 Register | SMC_KEY2 | write-only | 0x00000000 |
0x400E00E4 | SMC Write Protect Mode Register | SMC_WPMR | read-write | 0x00000000 |
0x400E00E8 | SMC Write Protect Status Register | SMC_WPSR | read-only | 0x00000000 |
Register Fields
SMC SMC Setup Register (CS_number = 0)
Name: SMC_SETUP0
Access: read-write
Address: 0x400E0000
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | NCS_RD_SETUP | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | NRD_SETUP | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | NCS_WR_SETUP | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | NWE_SETUP |
- NWE_SETUP: NWE Setup Length
- NCS_WR_SETUP: NCS Setup Length in WRITE Access
- NRD_SETUP: NRD Setup Length
- NCS_RD_SETUP: NCS Setup Length in READ Access
-
-
-
-
SMC SMC Pulse Register (CS_number = 0)
Name: SMC_PULSE0
Access: read-write
Address: 0x400E0004
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | NCS_RD_PULSE | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | NRD_PULSE | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | NCS_WR_PULSE | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | NWE_PULSE |
- NWE_PULSE: NWE Pulse Length
- NCS_WR_PULSE: NCS Pulse Length in WRITE Access
- NRD_PULSE: NRD Pulse Length
- NCS_RD_PULSE: NCS Pulse Length in READ Access
-
-
-
-
SMC SMC Cycle Register (CS_number = 0)
Name: SMC_CYCLE0
Access: read-write
Address: 0x400E0008
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | NRD_CYCLE |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NRD_CYCLE | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | NWE_CYCLE |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NWE_CYCLE |
- NWE_CYCLE: Total Write Cycle Length
- NRD_CYCLE: Total Read Cycle Length
-
-
SMC SMC Mode Register (CS_number = 0)
Name: SMC_MODE0
Access: read-write
Address: 0x400E000C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | PS | - | - | - | PMEN | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | TDF_MODE | TDF_CYCLES | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DBW | - | - | - | - | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE |
-
READ_MODE
Value Name Description 0 - The read operation is controlled by the NCS signal. 1 - The read operation is controlled by the NRD signal. -
WRITE_MODE
Value Name Description 0 - The write operation is controlled by the NCS signal. 1 - The write operation is controlled by the NWE signal. - EXNW_MODE: NWAIT Mode
Value Name Description 0x0 DISABLED Disabled 0x2 FROZEN Frozen Mode 0x3 READY Ready Mode - DBW: Data Bus Width
Value Name Description 0x0 8_BIT 8-bit bus 0x1 16_BIT 16-bit bus 0x2 32_BIT 32-bit bus - TDF_CYCLES: Data Float Time
- TDF_MODE: TDF Optimization
Value Name Description 0 - TDF optimization is disabled. 1 - TDF optimization is enabled. - PMEN: Page Mode Enabled
Value Name Description 0 - Standard read is applied. 1 - Asynchronous burst read in page mode is applied on the corresponding chip select. - PS: Page Size
Value Name Description 0x0 4_BYTE 4-byte page 0x1 8_BYTE 8-byte page 0x2 16_BYTE 16-byte page 0x3 32_BYTE 32-byte page
-
SMC SMC Setup Register (CS_number = 1)
Name: SMC_SETUP1
Access: read-write
Address: 0x400E0010
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | NCS_RD_SETUP | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | NRD_SETUP | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | NCS_WR_SETUP | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | NWE_SETUP |
- NWE_SETUP: NWE Setup Length
- NCS_WR_SETUP: NCS Setup Length in WRITE Access
- NRD_SETUP: NRD Setup Length
- NCS_RD_SETUP: NCS Setup Length in READ Access
-
-
-
-
SMC SMC Pulse Register (CS_number = 1)
Name: SMC_PULSE1
Access: read-write
Address: 0x400E0014
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | NCS_RD_PULSE | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | NRD_PULSE | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | NCS_WR_PULSE | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | NWE_PULSE |
- NWE_PULSE: NWE Pulse Length
- NCS_WR_PULSE: NCS Pulse Length in WRITE Access
- NRD_PULSE: NRD Pulse Length
- NCS_RD_PULSE: NCS Pulse Length in READ Access
-
-
-
-
SMC SMC Cycle Register (CS_number = 1)
Name: SMC_CYCLE1
Access: read-write
Address: 0x400E0018
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | NRD_CYCLE |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NRD_CYCLE | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | NWE_CYCLE |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NWE_CYCLE |
- NWE_CYCLE: Total Write Cycle Length
- NRD_CYCLE: Total Read Cycle Length
-
-
SMC SMC Mode Register (CS_number = 1)
Name: SMC_MODE1
Access: read-write
Address: 0x400E001C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | PS | - | - | - | PMEN | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | TDF_MODE | TDF_CYCLES | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DBW | - | - | - | - | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE |
-
READ_MODE
Value Name Description 0 - The read operation is controlled by the NCS signal. 1 - The read operation is controlled by the NRD signal. -
WRITE_MODE
Value Name Description 0 - The write operation is controlled by the NCS signal. 1 - The write operation is controlled by the NWE signal. - EXNW_MODE: NWAIT Mode
Value Name Description 0x0 DISABLED Disabled 0x2 FROZEN Frozen Mode 0x3 READY Ready Mode - DBW: Data Bus Width
Value Name Description 0x0 8_BIT 8-bit bus 0x1 16_BIT 16-bit bus 0x2 32_BIT 32-bit bus - TDF_CYCLES: Data Float Time
- TDF_MODE: TDF Optimization
Value Name Description 0 - TDF optimization is disabled. 1 - TDF optimization is enabled. - PMEN: Page Mode Enabled
Value Name Description 0 - Standard read is applied. 1 - Asynchronous burst read in page mode is applied on the corresponding chip select. - PS: Page Size
Value Name Description 0x0 4_BYTE 4-byte page 0x1 8_BYTE 8-byte page 0x2 16_BYTE 16-byte page 0x3 32_BYTE 32-byte page
-
SMC SMC Setup Register (CS_number = 2)
Name: SMC_SETUP2
Access: read-write
Address: 0x400E0020
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | NCS_RD_SETUP | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | NRD_SETUP | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | NCS_WR_SETUP | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | NWE_SETUP |
- NWE_SETUP: NWE Setup Length
- NCS_WR_SETUP: NCS Setup Length in WRITE Access
- NRD_SETUP: NRD Setup Length
- NCS_RD_SETUP: NCS Setup Length in READ Access
-
-
-
-
SMC SMC Pulse Register (CS_number = 2)
Name: SMC_PULSE2
Access: read-write
Address: 0x400E0024
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | NCS_RD_PULSE | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | NRD_PULSE | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | NCS_WR_PULSE | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | NWE_PULSE |
- NWE_PULSE: NWE Pulse Length
- NCS_WR_PULSE: NCS Pulse Length in WRITE Access
- NRD_PULSE: NRD Pulse Length
- NCS_RD_PULSE: NCS Pulse Length in READ Access
-
-
-
-
SMC SMC Cycle Register (CS_number = 2)
Name: SMC_CYCLE2
Access: read-write
Address: 0x400E0028
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | NRD_CYCLE |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NRD_CYCLE | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | NWE_CYCLE |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NWE_CYCLE |
- NWE_CYCLE: Total Write Cycle Length
- NRD_CYCLE: Total Read Cycle Length
-
-
SMC SMC Mode Register (CS_number = 2)
Name: SMC_MODE2
Access: read-write
Address: 0x400E002C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | PS | - | - | - | PMEN | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | TDF_MODE | TDF_CYCLES | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DBW | - | - | - | - | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE |
-
READ_MODE
Value Name Description 0 - The read operation is controlled by the NCS signal. 1 - The read operation is controlled by the NRD signal. -
WRITE_MODE
Value Name Description 0 - The write operation is controlled by the NCS signal. 1 - The write operation is controlled by the NWE signal. - EXNW_MODE: NWAIT Mode
Value Name Description 0x0 DISABLED Disabled 0x2 FROZEN Frozen Mode 0x3 READY Ready Mode - DBW: Data Bus Width
Value Name Description 0x0 8_BIT 8-bit bus 0x1 16_BIT 16-bit bus 0x2 32_BIT 32-bit bus - TDF_CYCLES: Data Float Time
- TDF_MODE: TDF Optimization
Value Name Description 0 - TDF optimization is disabled. 1 - TDF optimization is enabled. - PMEN: Page Mode Enabled
Value Name Description 0 - Standard read is applied. 1 - Asynchronous burst read in page mode is applied on the corresponding chip select. - PS: Page Size
Value Name Description 0x0 4_BYTE 4-byte page 0x1 8_BYTE 8-byte page 0x2 16_BYTE 16-byte page 0x3 32_BYTE 32-byte page
-
SMC SMC Setup Register (CS_number = 3)
Name: SMC_SETUP3
Access: read-write
Address: 0x400E0030
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | NCS_RD_SETUP | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | NRD_SETUP | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | NCS_WR_SETUP | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | NWE_SETUP |
- NWE_SETUP: NWE Setup Length
- NCS_WR_SETUP: NCS Setup Length in WRITE Access
- NRD_SETUP: NRD Setup Length
- NCS_RD_SETUP: NCS Setup Length in READ Access
-
-
-
-
SMC SMC Pulse Register (CS_number = 3)
Name: SMC_PULSE3
Access: read-write
Address: 0x400E0034
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | NCS_RD_PULSE | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | NRD_PULSE | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | NCS_WR_PULSE | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | NWE_PULSE |
- NWE_PULSE: NWE Pulse Length
- NCS_WR_PULSE: NCS Pulse Length in WRITE Access
- NRD_PULSE: NRD Pulse Length
- NCS_RD_PULSE: NCS Pulse Length in READ Access
-
-
-
-
SMC SMC Cycle Register (CS_number = 3)
Name: SMC_CYCLE3
Access: read-write
Address: 0x400E0038
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | NRD_CYCLE |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NRD_CYCLE | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | NWE_CYCLE |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NWE_CYCLE |
- NWE_CYCLE: Total Write Cycle Length
- NRD_CYCLE: Total Read Cycle Length
-
-
SMC SMC Mode Register (CS_number = 3)
Name: SMC_MODE3
Access: read-write
Address: 0x400E003C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | PS | - | - | - | PMEN | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | TDF_MODE | TDF_CYCLES | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DBW | - | - | - | - | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE |
-
READ_MODE
Value Name Description 0 - The read operation is controlled by the NCS signal. 1 - The read operation is controlled by the NRD signal. -
WRITE_MODE
Value Name Description 0 - The write operation is controlled by the NCS signal. 1 - The write operation is controlled by the NWE signal. - EXNW_MODE: NWAIT Mode
Value Name Description 0x0 DISABLED Disabled 0x2 FROZEN Frozen Mode 0x3 READY Ready Mode - DBW: Data Bus Width
Value Name Description 0x0 8_BIT 8-bit bus 0x1 16_BIT 16-bit bus 0x2 32_BIT 32-bit bus - TDF_CYCLES: Data Float Time
- TDF_MODE: TDF Optimization
Value Name Description 0 - TDF optimization is disabled. 1 - TDF optimization is enabled. - PMEN: Page Mode Enabled
Value Name Description 0 - Standard read is applied. 1 - Asynchronous burst read in page mode is applied on the corresponding chip select. - PS: Page Size
Value Name Description 0x0 4_BYTE 4-byte page 0x1 8_BYTE 8-byte page 0x2 16_BYTE 16-byte page 0x3 32_BYTE 32-byte page
-
SMC SMC Setup Register (CS_number = 4)
Name: SMC_SETUP4
Access: read-write
Address: 0x400E0040
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | NCS_RD_SETUP | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | NRD_SETUP | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | NCS_WR_SETUP | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | NWE_SETUP |
- NWE_SETUP: NWE Setup Length
- NCS_WR_SETUP: NCS Setup Length in WRITE Access
- NRD_SETUP: NRD Setup Length
- NCS_RD_SETUP: NCS Setup Length in READ Access
-
-
-
-
SMC SMC Pulse Register (CS_number = 4)
Name: SMC_PULSE4
Access: read-write
Address: 0x400E0044
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | NCS_RD_PULSE | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | NRD_PULSE | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | NCS_WR_PULSE | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | NWE_PULSE |
- NWE_PULSE: NWE Pulse Length
- NCS_WR_PULSE: NCS Pulse Length in WRITE Access
- NRD_PULSE: NRD Pulse Length
- NCS_RD_PULSE: NCS Pulse Length in READ Access
-
-
-
-
SMC SMC Cycle Register (CS_number = 4)
Name: SMC_CYCLE4
Access: read-write
Address: 0x400E0048
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | NRD_CYCLE |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
NRD_CYCLE | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | NWE_CYCLE |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NWE_CYCLE |
- NWE_CYCLE: Total Write Cycle Length
- NRD_CYCLE: Total Read Cycle Length
-
-
SMC SMC Mode Register (CS_number = 4)
Name: SMC_MODE4
Access: read-write
Address: 0x400E004C
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | PS | - | - | - | PMEN | |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | TDF_MODE | TDF_CYCLES | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | DBW | - | - | - | - | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | EXNW_MODE | - | - | WRITE_MODE | READ_MODE |
-
READ_MODE
Value Name Description 0 - The read operation is controlled by the NCS signal. 1 - The read operation is controlled by the NRD signal. -
WRITE_MODE
Value Name Description 0 - The write operation is controlled by the NCS signal. 1 - The write operation is controlled by the NWE signal. - EXNW_MODE: NWAIT Mode
Value Name Description 0x0 DISABLED Disabled 0x2 FROZEN Frozen Mode 0x3 READY Ready Mode - DBW: Data Bus Width
Value Name Description 0x0 8_BIT 8-bit bus 0x1 16_BIT 16-bit bus 0x2 32_BIT 32-bit bus - TDF_CYCLES: Data Float Time
- TDF_MODE: TDF Optimization
Value Name Description 0 - TDF optimization is disabled. 1 - TDF optimization is enabled. - PMEN: Page Mode Enabled
Value Name Description 0 - Standard read is applied. 1 - Asynchronous burst read in page mode is applied on the corresponding chip select. - PS: Page Size
Value Name Description 0x0 4_BYTE 4-byte page 0x1 8_BYTE 8-byte page 0x2 16_BYTE 16-byte page 0x3 32_BYTE 32-byte page
-
SMC SMC OCMS MODE Register
Name: SMC_OCMS
Access: read-write
Address: 0x400E0080
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | CS3SE | CS2SE | CS1SE | CS0SE |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | SMSE |
- SMSE: Static Memory Controller Scrambling Enable
Value Name Description 0 - Disable Scrambling for SMC access. 1 - Enable Scrambling for SMC access. - CS0SE: Chip Select (x = 0 to 3) Scrambling Enable
Value Name Description 0 - Disable Scrambling for CSx. 1 - Enable Scrambling for CSx. - CS1SE: Chip Select (x = 0 to 3) Scrambling Enable
Value Name Description 0 - Disable Scrambling for CSx. 1 - Enable Scrambling for CSx. - CS2SE: Chip Select (x = 0 to 3) Scrambling Enable
Value Name Description 0 - Disable Scrambling for CSx. 1 - Enable Scrambling for CSx. - CS3SE: Chip Select (x = 0 to 3) Scrambling Enable
Value Name Description 0 - Disable Scrambling for CSx. 1 - Enable Scrambling for CSx.
SMC SMC OCMS KEY1 Register
Name: SMC_KEY1
Access: write-only
Address: 0x400E0084
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY1 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY1 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
KEY1 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY1 |
- KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1
-
SMC SMC OCMS KEY2 Register
Name: SMC_KEY2
Access: write-only
Address: 0x400E0088
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY2 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY2 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
KEY2 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY2 |
- KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2
-
SMC SMC Write Protect Mode Register
Name: SMC_WPMR
Access: read-write
Address: 0x400E00E4
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
WPKEY | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WPKEY | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WPKEY | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | WPEN |
- WPEN: Write Protect Enable
Value Name Description 0 - Disables the Write Protect if WPKEY corresponds to 0x534D43 ("SMC" in ASCII). 1 - Enables the Write Protect if WPKEY corresponds to 0x534D43 ("SMC" in ASCII). - WPKEY: Write Protect KEY
-
SMC SMC Write Protect Status Register
Name: SMC_WPSR
Access: read-only
Address: 0x400E00E8
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
WPVSRC | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
WPVSRC | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | WPVS |
- WPVS: Write Protect Enable
Value Name Description 0 - No Write Protect Violation has occurred since the last read of the SMC_WPSR register. 1 - A Write Protect Violation occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. - WPVSRC: Write Protect Violation Source
-