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Merge branch 'sam-usart-mode-fix' into ide-1.5.x

This commit is contained in:
Cristian Maglie 2015-01-19 13:43:42 +01:00
parent 07d1abfe43 00f23d3aad
commit 0e013406bc
4 changed files with 133 additions and 50 deletions
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14
hardware/arduino/sam/cores/arduino/UARTClass.cpp
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@ -35,12 +35,18 @@ UARTClass::UARTClass( Uart *pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer *p
// Public Methods //////////////////////////////////////////////////////////////
void UARTClass::begin( const uint32_t dwBaudRate )
void UARTClass::begin(const uint32_t dwBaudRate)
{
begin( dwBaudRate, UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL );
begin(dwBaudRate, Mode_8N1);
}
void UARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
void UARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)
{
uint32_t modeReg = static_cast<uint32_t>(config) & 0x00000E00;
init(dwBaudRate, modeReg | UART_MR_CHMODE_NORMAL);
}
void UARTClass::init(const uint32_t dwBaudRate, const uint32_t modeReg)
{
// Configure PMC
pmc_enable_periph_clk( _dwId );
@ -52,7 +58,7 @@ void UARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
_pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
// Configure mode
_pUart->UART_MR = config;
_pUart->UART_MR = modeReg;
// Configure baudrate (asynchronous, no oversampling)
_pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4;

36
hardware/arduino/sam/cores/arduino/UARTClass.h
View File

@ -25,22 +25,27 @@
// Includes Atmel CMSIS
#include <chip.h>
#define SERIAL_8N1 UARTClass::Mode_8N1
#define SERIAL_8E1 UARTClass::Mode_8E1
#define SERIAL_8O1 UARTClass::Mode_8O1
#define SERIAL_8M1 UARTClass::Mode_8M1
#define SERIAL_8S1 UARTClass::Mode_8S1
class UARTClass : public HardwareSerial
{
protected:
RingBuffer *_rx_buffer;
RingBuffer *_tx_buffer;
protected:
Uart* _pUart;
IRQn_Type _dwIrq;
uint32_t _dwId;
public:
enum UARTModes {
Mode_8N1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO,
Mode_8E1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_EVEN,
Mode_8O1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_ODD,
Mode_8M1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_MARK,
Mode_8S1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_SPACE,
};
UARTClass(Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
void begin(const uint32_t dwBaudRate);
void begin(const uint32_t dwBaudRate, const uint32_t config);
void begin(const uint32_t dwBaudRate, const UARTModes config);
void end(void);
int available(void);
int availableForWrite(void);
@ -56,6 +61,17 @@ class UARTClass : public HardwareSerial
void IrqHandler(void);
operator bool() { return true; }; // UART always active
protected:
void init(const uint32_t dwBaudRate, const uint32_t config);
RingBuffer *_rx_buffer;
RingBuffer *_tx_buffer;
Uart* _pUart;
IRQn_Type _dwIrq;
uint32_t _dwId;
};
#endif // _UART_CLASS_

18
hardware/arduino/sam/cores/arduino/USARTClass.cpp
View File

@ -32,8 +32,22 @@ USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffe
// Public Methods //////////////////////////////////////////////////////////////
void USARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
void USARTClass::begin(const uint32_t dwBaudRate)
{
UARTClass::begin(dwBaudRate, config);
begin(dwBaudRate, Mode_8N1);
}
void USARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)
{
uint32_t modeReg = static_cast<uint32_t>(config);
modeReg |= US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHMODE_NORMAL;
init(dwBaudRate, modeReg);
}
void USARTClass::begin(const uint32_t dwBaudRate, const USARTModes config)
{
uint32_t modeReg = static_cast<uint32_t>(config);
modeReg |= US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHMODE_NORMAL;
init(dwBaudRate, modeReg);
}

115
hardware/arduino/sam/cores/arduino/USARTClass.h
View File

@ -26,46 +26,93 @@
#include <chip.h>
// Define config for Serial.begin(baud, config);
#define SERIAL_5N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_6N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_7N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_8N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_5N1 USARTClass::Mode_5N1
#define SERIAL_6N1 USARTClass::Mode_6N1
#define SERIAL_7N1 USARTClass::Mode_7N1
#define SERIAL_5N2 USARTClass::Mode_5N2
#define SERIAL_6N2 USARTClass::Mode_6N2
#define SERIAL_7N2 USARTClass::Mode_7N2
#define SERIAL_8N2 USARTClass::Mode_8N2
#define SERIAL_5E1 USARTClass::Mode_5E1
#define SERIAL_6E1 USARTClass::Mode_6E1
#define SERIAL_7E1 USARTClass::Mode_7E1
#define SERIAL_5E2 USARTClass::Mode_5E2
#define SERIAL_6E2 USARTClass::Mode_6E2
#define SERIAL_7E2 USARTClass::Mode_7E2
#define SERIAL_8E2 USARTClass::Mode_8E2
#define SERIAL_5O1 USARTClass::Mode_5O1
#define SERIAL_6O1 USARTClass::Mode_6O1
#define SERIAL_7O1 USARTClass::Mode_7O1
#define SERIAL_5O2 USARTClass::Mode_5O2
#define SERIAL_6O2 USARTClass::Mode_6O2
#define SERIAL_7O2 USARTClass::Mode_7O2
#define SERIAL_8O2 USARTClass::Mode_8O2
#define SERIAL_5M1 USARTClass::Mode_5M1
#define SERIAL_6M1 USARTClass::Mode_6M1
#define SERIAL_7M1 USARTClass::Mode_7M1
#define SERIAL_5M2 USARTClass::Mode_5M2
#define SERIAL_6M2 USARTClass::Mode_6M2
#define SERIAL_7M2 USARTClass::Mode_7M2
#define SERIAL_8M2 USARTClass::Mode_8M2
#define SERIAL_5S1 USARTClass::Mode_5S1
#define SERIAL_6S1 USARTClass::Mode_6S1
#define SERIAL_7S1 USARTClass::Mode_7S1
#define SERIAL_5S2 USARTClass::Mode_5S2
#define SERIAL_6S2 USARTClass::Mode_6S2
#define SERIAL_7S2 USARTClass::Mode_7S2
#define SERIAL_8S2 USARTClass::Mode_8S2
#define SERIAL_5N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_6N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_7N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_8N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_5E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_6E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_7E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_8E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_5E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_6E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_7E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_8E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_5O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_6O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_7O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_8O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_5O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_6O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_7O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
#define SERIAL_8O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
class USARTClass : public UARTClass
{
public:
// 8x1 bit modes are inherited from UARTClass
enum USARTModes {
Mode_5N1 = US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
Mode_6N1 = US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
Mode_7N1 = US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
Mode_5N2 = US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
Mode_6N2 = US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
Mode_7N2 = US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
Mode_8N2 = US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
Mode_5E1 = US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
Mode_6E1 = US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
Mode_7E1 = US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
Mode_5E2 = US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
Mode_6E2 = US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
Mode_7E2 = US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
Mode_8E2 = US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
Mode_5O1 = US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
Mode_6O1 = US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
Mode_7O1 = US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
Mode_5O2 = US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
Mode_6O2 = US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
Mode_7O2 = US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
Mode_8O2 = US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
Mode_5M1 = US_MR_CHRL_5_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
Mode_6M1 = US_MR_CHRL_6_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
Mode_7M1 = US_MR_CHRL_7_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
Mode_5M2 = US_MR_CHRL_5_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
Mode_6M2 = US_MR_CHRL_6_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
Mode_7M2 = US_MR_CHRL_7_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
Mode_8M2 = US_MR_CHRL_8_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
Mode_5S1 = US_MR_CHRL_5_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
Mode_6S1 = US_MR_CHRL_6_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
Mode_7S1 = US_MR_CHRL_7_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
Mode_5S2 = US_MR_CHRL_5_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
Mode_6S2 = US_MR_CHRL_6_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
Mode_7S2 = US_MR_CHRL_7_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
Mode_8S2 = US_MR_CHRL_8_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
};
USARTClass(Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
void begin(const uint32_t dwBaudRate);
void begin(const uint32_t dwBaudRate, const USARTModes config);
void begin(const uint32_t dwBaudRate, const UARTModes config);
protected:
Usart* _pUsart;
public:
USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer );
void begin( const uint32_t dwBaudRate , const uint32_t config );
using UARTClass::begin; // Needed only for polymorphic methods
};
#endif // _USART_CLASS_