mirror of https://github.com/noisymime/Arduino.git
Merge remote-tracking branch 'origin/new-extension' into new-extension
This commit is contained in:
Cristian Maglie
commit
8d83eb79a9
File diff suppressed because it is too large
Load Diff
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@ -52,6 +52,55 @@ typedef struct {
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/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
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#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
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#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
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/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
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#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
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#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
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#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */
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#define ADC_MR_TRGSEL_Pos 1
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#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
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#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */
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#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */
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#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */
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#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */
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#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
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#define ADC_MR_LOWRES_BITS_10 (0x0u << 4) /**< \brief (ADC_MR) 10-bit resolution */
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#define ADC_MR_LOWRES_BITS_8 (0x1u << 4) /**< \brief (ADC_MR) 8-bit resolution */
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#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
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#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */
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#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */
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#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */
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#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */
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#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */
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#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */
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#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */
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#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */
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#define ADC_MR_PRESCAL_Pos 8
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#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
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#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
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#define ADC_MR_STARTUP_Pos 16
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#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
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#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */
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#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */
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#define ADC_MR_TRACKTIM_Pos 24
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#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */
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#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos)))
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#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */
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#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */
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#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */
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/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
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#define ADC_SEQR1_USCH1_Pos 0
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#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
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@ -3,6 +3,17 @@
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#ifndef _SAM3N_
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#define _SAM3N_
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/* Device characteristics */
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#define CHIP_FREQ_SLCK_RC_MIN (20000U)
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#define CHIP_FREQ_SLCK_RC (32000U)
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#define CHIP_FREQ_SLCK_RC_MAX (44000U)
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#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U)
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#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U)
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#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U)
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#define CHIP_FREQ_CPU_MAX (48000000U)
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#define CHIP_FLASH_WAIT_STATE (3U)
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#if defined __SAM3N1A__
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#include "sam3n1a.h"
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#elif defined __SAM3N1B__
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@ -6,7 +6,7 @@
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*
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* \par Purpose
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*
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* This file provides basic support for Cortex-M processor based
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* This file provides basic support for Cortex-M processor based
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* microcontrollers.
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*
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* \note
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@ -31,44 +31,44 @@ extern "C" {
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|
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#ifdef __GNUC__
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/* Cortex-M3 core handlers */
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extern void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void UsageFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void SVC_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void DebugMon_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void PendSV_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void SysTick_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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/* Peripherals handlers */
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extern void SUPC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void RSTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void RTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void RTT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void PMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void EFC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void UART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void UART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void PIOA_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void PIOB_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void PIOC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void USART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void USART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TWI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TWI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void SPI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TC2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TC3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TC4_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void TC5_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void ADC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void DACC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
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void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void EFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void DACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
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#endif /* __GNUC__ */
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#ifdef __ICCARM__
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@ -116,9 +116,10 @@ extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler")
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/**
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* \brief Default interrupt handler for unused IRQs.
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*/
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void Dummy_Handler( void )
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void Dummy_Handler(void)
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{
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while ( 1 ) {}
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while (1) {
|
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}
|
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}
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|
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/* @cond 0 */
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|
|
|
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|
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@ -6,7 +6,7 @@
|
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*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
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|
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@ -29,47 +29,47 @@ extern "C" {
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typedef void (*IntFunc) (void);
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|
||||
/* Default empty handler */
|
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extern void Dummy_Handler( void ) ;
|
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void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) ;
|
||||
extern void NMI_Handler( void ) ;
|
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extern void HardFault_Handler( void ) ;
|
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extern void MemManage_Handler( void ) ;
|
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extern void BusFault_Handler( void ) ;
|
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extern void UsageFault_Handler( void ) ;
|
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extern void SVC_Handler( void ) ;
|
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extern void DebugMon_Handler( void ) ;
|
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extern void PendSV_Handler( void ) ;
|
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extern void SysTick_Handler( void ) ;
|
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void Reset_Handler(void);
|
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void NMI_Handler(void);
|
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void HardFault_Handler(void);
|
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void MemManage_Handler(void);
|
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void BusFault_Handler(void);
|
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void UsageFault_Handler(void);
|
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void SVC_Handler(void);
|
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void DebugMon_Handler(void);
|
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void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void SUPC_IrqHandler( void ) ;
|
||||
extern void RSTC_IrqHandler( void ) ;
|
||||
extern void RTC_IrqHandler( void ) ;
|
||||
extern void RTT_IrqHandler( void ) ;
|
||||
extern void WDT_IrqHandler( void ) ;
|
||||
extern void PMC_IrqHandler( void ) ;
|
||||
extern void EFC_IrqHandler( void ) ;
|
||||
extern void UART0_IrqHandler( void ) ;
|
||||
extern void UART1_IrqHandler( void ) ;
|
||||
extern void PIOA_IrqHandler( void ) ;
|
||||
extern void PIOB_IrqHandler( void ) ;
|
||||
extern void PIOC_IrqHandler( void ) ;
|
||||
extern void USART0_IrqHandler( void ) ;
|
||||
extern void USART1_IrqHandler( void ) ;
|
||||
extern void TWI0_IrqHandler( void ) ;
|
||||
extern void TWI1_IrqHandler( void ) ;
|
||||
extern void SPI_IrqHandler( void ) ;
|
||||
extern void TC0_IrqHandler( void ) ;
|
||||
extern void TC1_IrqHandler( void ) ;
|
||||
extern void TC2_IrqHandler( void ) ;
|
||||
extern void TC3_IrqHandler( void ) ;
|
||||
extern void TC4_IrqHandler( void ) ;
|
||||
extern void TC5_IrqHandler( void ) ;
|
||||
extern void ADC_IrqHandler( void ) ;
|
||||
extern void DACC_IrqHandler( void ) ;
|
||||
extern void PWM_IrqHandler( void ) ;
|
||||
void SUPC_IrqHandler(void);
|
||||
void RSTC_IrqHandler(void);
|
||||
void RTC_IrqHandler(void);
|
||||
void RTT_IrqHandler(void);
|
||||
void WDT_IrqHandler(void);
|
||||
void PMC_IrqHandler(void);
|
||||
void EFC_IrqHandler(void);
|
||||
void UART0_IrqHandler(void);
|
||||
void UART1_IrqHandler(void);
|
||||
void PIOA_IrqHandler(void);
|
||||
void PIOB_IrqHandler(void);
|
||||
void PIOC_IrqHandler(void);
|
||||
void USART0_IrqHandler(void);
|
||||
void USART1_IrqHandler(void);
|
||||
void TWI0_IrqHandler(void);
|
||||
void TWI1_IrqHandler(void);
|
||||
void SPI_IrqHandler(void);
|
||||
void TC0_IrqHandler(void);
|
||||
void TC1_IrqHandler(void);
|
||||
void TC2_IrqHandler(void);
|
||||
void TC3_IrqHandler(void);
|
||||
void TC4_IrqHandler(void);
|
||||
void TC5_IrqHandler(void);
|
||||
void ADC_IrqHandler(void);
|
||||
void DACC_IrqHandler(void);
|
||||
void PWM_IrqHandler(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -80,4 +80,3 @@ extern void PWM_IrqHandler( void ) ;
|
|||
/* @endcond */
|
||||
|
||||
#endif /* EXCEPTIONS_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -12,9 +12,8 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3n.h"
|
||||
#include "system_sam3n.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
|
|
@ -28,114 +27,108 @@ extern uint32_t _sstack;
|
|||
extern uint32_t _estack;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
extern int main(void);
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
|
||||
void ResetException( void ) ;
|
||||
extern void __libc_init_array( void ) ;
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__((section(".vectors")))
|
||||
__attribute__ ((section(".vectors")))
|
||||
IntFunc exception_table[] = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc)(&_estack),
|
||||
Reset_Handler,
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc) (&_estack),
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
Dummy_Handler, /* 10 Reserved */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
Dummy_Handler, /* 18 Reserved */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
Dummy_Handler, /* 22 Reserved */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DACC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
Dummy_Handler, /* 10 Reserved */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
Dummy_Handler, /* 18 Reserved */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
Dummy_Handler, /* 22 Reserved */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DACC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
Dummy_Handler /* 32 not used */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest ;
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext ;
|
||||
pDest = &_srelocate ;
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if ( pSrc != pDest )
|
||||
{
|
||||
for ( ; pDest < &_erelocate ; )
|
||||
{
|
||||
*pDest++ = *pSrc++ ;
|
||||
}
|
||||
}
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for ( pDest = &_szero ; pDest < &_ezero ; )
|
||||
{
|
||||
*pDest++ = 0;
|
||||
}
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *)&_sfixed;
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array() ;
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main() ;
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while ( 1 ) ;
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,103 +12,99 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3n.h"
|
||||
#include "system_sam3n.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
typedef void( *intfunc )( void );
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
extern void __iar_program_start( void ) ;
|
||||
extern int __low_level_init( void ) ;
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0. */
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const intvec_elem __vector_table[] =
|
||||
{
|
||||
{ .__ptr = __sfe( "CSTACK" ) },
|
||||
Reset_Handler,
|
||||
const intvec_elem __vector_table[] = {
|
||||
{.__ptr = __sfe("CSTACK")},
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
Dummy_Handler, /* 10 Reserved */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
Dummy_Handler, /* 18 Reserved */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
Dummy_Handler, /* 22 Reserved */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DACC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
Dummy_Handler /* 32 not used */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
Dummy_Handler, /* 10 Reserved */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
Dummy_Handler, /* 18 Reserved */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
Dummy_Handler, /* 22 Reserved */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DACC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
Dummy_Handler /* 32 not used */
|
||||
};
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern int __low_level_init( void )
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t* pSrc = __section_begin( ".intvec" ) ;
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
return 1 ; /* if return 0, the data sections will not be initialized. */
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* on chip startup.
|
||||
*
|
||||
* $asf_license$
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -27,126 +27,159 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Clock settings (48MHz) */
|
||||
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define BOARD_PLLR (CKGR_PLLR_STUCKTO1 \
|
||||
| CKGR_PLLR_MUL(0x3) \
|
||||
| CKGR_PLLR_PLLCOUNT(0x3f) \
|
||||
| CKGR_PLLR_DIV(0x1))
|
||||
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLL_CLK)
|
||||
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define SYS_BOARD_PLLR (CKGR_PLLR_STUCKTO1 \
|
||||
| CKGR_PLLR_MUL(0x3) \
|
||||
| CKGR_PLLR_PLLCOUNT(0x3f) \
|
||||
| CKGR_PLLR_DIV(0x1))
|
||||
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLL_CLK)
|
||||
|
||||
/* Clock Definitions */
|
||||
#define XTAL32 ( 32768UL) /* 32k crystal frequency */
|
||||
#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
|
||||
#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
|
||||
#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
|
||||
#define MAINCK_XTAL_HZ (12000000UL) /* External crystal frequency */
|
||||
#define MCK_HZ (48000000UL) /* Processor frequency */
|
||||
#define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */
|
||||
#define SYS_FREQ_XTAL_XTAL12M (12000000UL) /* External 12M crystal frequency */
|
||||
|
||||
#define SYS_FREQ_FWS_0 (21000000UL) /* Maximum operating frequency when FWS is 0 */
|
||||
#define SYS_FREQ_FWS_1 (32000000UL) /* Maximum operating frequency when FWS is 1 */
|
||||
#define SYS_FREQ_FWS_2 (48000000UL) /* Maximum operating frequency when FWS is 2 */
|
||||
|
||||
|
||||
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37U) /* Key to unlock MOR register */
|
||||
|
||||
/* FIXME: should be generated by sock */
|
||||
uint32_t SystemCoreClock = EFRC_OSC;
|
||||
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
/**
|
||||
* \brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
extern void SystemInit( void )
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
|
||||
/* Initialize main oscillator */
|
||||
if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
|
||||
{
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
|
||||
}
|
||||
/* Initialize main oscillator */
|
||||
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
|
||||
}
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
|
||||
PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Initialize PLL */
|
||||
PMC->CKGR_PLLR = BOARD_PLLR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCK));
|
||||
/* Initialize PLL */
|
||||
PMC->CKGR_PLLR = SYS_BOARD_PLLR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCK)) {
|
||||
}
|
||||
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) |
|
||||
PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = BOARD_MCKR ;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = SYS_BOARD_MCKR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
SystemCoreClock = MCK_HZ;
|
||||
SystemCoreClock = CHIP_FREQ_CPU_MAX;
|
||||
}
|
||||
|
||||
extern void SystemCoreClockUpdate( void )
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void)
|
||||
{
|
||||
/* Set FWS for Embedded Flash Access according operating frequency*/
|
||||
if(SystemCoreClock < SYS_FREQ_FWS_0){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_1){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
}else{
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT
|
||||
/*Disable the watchdog */
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
|
||||
SystemCoreClock = OSC32_CLK;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = ERC_OSC;
|
||||
}
|
||||
SystemCoreClock = SYS_FREQ_XTAL_32K;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_SLCK_RC;
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHZ:
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHZ:
|
||||
SystemCoreClock *= 2;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHZ:
|
||||
SystemCoreClock *= 3;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_PLL_CLK: /* PLL clock */
|
||||
case PMC_MCKR_CSS_PLL_CLK: /* PLL clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHZ:
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHZ:
|
||||
SystemCoreClock *= 2;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHZ:
|
||||
SystemCoreClock *= 3;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLR) >> CKGR_PLLR_MUL_Pos) & 0x7FF) + 1);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLR) >> CKGR_PLLR_DIV_Pos) & 0x0FF));
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLR) & CKGR_PLLR_MUL_Msk) >>
|
||||
CKGR_PLLR_MUL_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLR) & CKGR_PLLR_DIV_Msk) >>
|
||||
CKGR_PLLR_DIV_Pos));
|
||||
break;
|
||||
}
|
||||
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
|
||||
SystemCoreClock /= 3;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
SystemCoreClock /= 3U;
|
||||
} else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
|
||||
PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
@ -156,4 +189,3 @@ extern void SystemCoreClockUpdate( void )
|
|||
#endif
|
||||
/**INDENT-ON**/
|
||||
/* @endcond */
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -34,13 +34,18 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
|||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -51,4 +56,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/* @endcond */
|
||||
|
||||
#endif /* SYSTEM_SAM3N_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,17 @@
|
|||
#ifndef _SAM3S_
|
||||
#define _SAM3S_
|
||||
|
||||
/* Device characteristics */
|
||||
#define CHIP_FREQ_SLCK_RC_MIN (20000U)
|
||||
#define CHIP_FREQ_SLCK_RC (32000U)
|
||||
#define CHIP_FREQ_SLCK_RC_MAX (44000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U)
|
||||
#define CHIP_FREQ_CPU_MAX (64000000U)
|
||||
|
||||
#define CHIP_FLASH_WAIT_STATE (3U)
|
||||
|
||||
#if defined __SAM3S1A__
|
||||
#include "sam3s1a.h"
|
||||
#elif defined __SAM3S1B__
|
||||
|
|
|
|||
|
|
@ -31,55 +31,55 @@ extern "C" {
|
|||
|
||||
#ifdef __GNUC__
|
||||
/* Cortex-M3 core handlers */
|
||||
//extern void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
//extern void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UsageFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SVC_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DebugMon_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PendSV_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SysTick_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
//void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
//void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void ACC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void ADC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void CRCCU_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DAC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EEFC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MCI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOA_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOB_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RSTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SPI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SSC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SUPC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC4_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC5_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USBD_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EEFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USBD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __ICCARM__
|
||||
/* Cortex-M3 core handlers */
|
||||
#pragma weak Reset_Handler=Dummy_Handler
|
||||
//#pragma weak Reset_Handler=Dummy_Handler
|
||||
#pragma weak NMI_Handler=Dummy_Handler
|
||||
//#pragma weak HardFault_Handler=Dummy_Handler
|
||||
#pragma weak MemManage_Handler=Dummy_Handler
|
||||
|
|
@ -128,9 +128,10 @@ extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler")
|
|||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler( void )
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while ( 1 ) {}
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
@ -140,4 +141,3 @@ void Dummy_Handler( void )
|
|||
#endif
|
||||
/**INDENT-ON**/
|
||||
/* @endcond */
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -26,56 +26,56 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Function prototype for exception table items (interrupt handler). */
|
||||
typedef void( *IntFunc )( void ) ;
|
||||
typedef void (*IntFunc) (void);
|
||||
|
||||
/* Default empty handler */
|
||||
extern void Dummy_Handler( void ) ;
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) ;
|
||||
extern void NMI_Handler( void ) ;
|
||||
extern void HardFault_Handler( void ) ;
|
||||
extern void MemManage_Handler( void ) ;
|
||||
extern void BusFault_Handler( void ) ;
|
||||
extern void UsageFault_Handler( void ) ;
|
||||
extern void SVC_Handler( void ) ;
|
||||
extern void DebugMon_Handler( void ) ;
|
||||
extern void PendSV_Handler( void ) ;
|
||||
extern void SysTick_Handler( void ) ;
|
||||
void Reset_Handler(void);
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void ACC_IrqHandler( void ) ;
|
||||
extern void ADC_IrqHandler( void ) ;
|
||||
extern void CRCCU_IrqHandler( void ) ;
|
||||
extern void DAC_IrqHandler( void ) ;
|
||||
extern void EEFC_IrqHandler( void ) ;
|
||||
extern void MCI_IrqHandler( void ) ;
|
||||
extern void PIOA_IrqHandler( void ) ;
|
||||
extern void PIOB_IrqHandler( void ) ;
|
||||
extern void PIOC_IrqHandler( void ) ;
|
||||
extern void PMC_IrqHandler( void ) ;
|
||||
extern void PWM_IrqHandler( void ) ;
|
||||
extern void RSTC_IrqHandler( void ) ;
|
||||
extern void RTC_IrqHandler( void ) ;
|
||||
extern void RTT_IrqHandler( void ) ;
|
||||
extern void SMC_IrqHandler( void ) ;
|
||||
extern void SPI_IrqHandler( void ) ;
|
||||
extern void SSC_IrqHandler( void ) ;
|
||||
extern void SUPC_IrqHandler( void ) ;
|
||||
extern void TC0_IrqHandler( void ) ;
|
||||
extern void TC1_IrqHandler( void ) ;
|
||||
extern void TC2_IrqHandler( void ) ;
|
||||
extern void TC3_IrqHandler( void ) ;
|
||||
extern void TC4_IrqHandler( void ) ;
|
||||
extern void TC5_IrqHandler( void ) ;
|
||||
extern void TWI0_IrqHandler( void ) ;
|
||||
extern void TWI1_IrqHandler( void ) ;
|
||||
extern void UART0_IrqHandler( void ) ;
|
||||
extern void UART1_IrqHandler( void ) ;
|
||||
extern void USART0_IrqHandler( void ) ;
|
||||
extern void USART1_IrqHandler( void ) ;
|
||||
extern void USBD_IrqHandler( void ) ;
|
||||
extern void WDT_IrqHandler( void ) ;
|
||||
void ACC_IrqHandler(void);
|
||||
void ADC_IrqHandler(void);
|
||||
void CRCCU_IrqHandler(void);
|
||||
void DAC_IrqHandler(void);
|
||||
void EEFC_IrqHandler(void);
|
||||
void MCI_IrqHandler(void);
|
||||
void PIOA_IrqHandler(void);
|
||||
void PIOB_IrqHandler(void);
|
||||
void PIOC_IrqHandler(void);
|
||||
void PMC_IrqHandler(void);
|
||||
void PWM_IrqHandler(void);
|
||||
void RSTC_IrqHandler(void);
|
||||
void RTC_IrqHandler(void);
|
||||
void RTT_IrqHandler(void);
|
||||
void SMC_IrqHandler(void);
|
||||
void SPI_IrqHandler(void);
|
||||
void SSC_IrqHandler(void);
|
||||
void SUPC_IrqHandler(void);
|
||||
void TC0_IrqHandler(void);
|
||||
void TC1_IrqHandler(void);
|
||||
void TC2_IrqHandler(void);
|
||||
void TC3_IrqHandler(void);
|
||||
void TC4_IrqHandler(void);
|
||||
void TC5_IrqHandler(void);
|
||||
void TWI0_IrqHandler(void);
|
||||
void TWI1_IrqHandler(void);
|
||||
void UART0_IrqHandler(void);
|
||||
void UART1_IrqHandler(void);
|
||||
void USART0_IrqHandler(void);
|
||||
void USART1_IrqHandler(void);
|
||||
void USBD_IrqHandler(void);
|
||||
void WDT_IrqHandler(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -86,4 +86,3 @@ extern void WDT_IrqHandler( void ) ;
|
|||
/* @endcond */
|
||||
|
||||
#endif /* EXCEPTIONS_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -12,14 +12,13 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3s.h"
|
||||
#include "system_sam3s.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
/* Stack Configuration */
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8),section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE] ;
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8), section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE];
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
|
|
@ -31,115 +30,111 @@ extern uint32_t _szero;
|
|||
extern uint32_t _ezero;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
extern int main( void ) ;
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
extern void __libc_init_array( void ) ;
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__((section(".vectors")))
|
||||
__attribute__ ((section(".vectors")))
|
||||
IntFunc exception_table[] = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc)(&pdwStack[STACK_SIZE-1]),
|
||||
Reset_Handler,
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc) (&pdwStack[STACK_SIZE - 1]),
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EEFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
SMC_IrqHandler, /* 10 SMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
MCI_IrqHandler, /* 18 MCI */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
SSC_IrqHandler, /* 22 SSC */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DAC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IrqHandler, /* 33 Analog Comparator */
|
||||
USBD_IrqHandler, /* 34 USB Device Port */
|
||||
Dummy_Handler /* 35 not used */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EEFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
SMC_IrqHandler, /* 10 SMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
MCI_IrqHandler, /* 18 MCI */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
SSC_IrqHandler, /* 22 SSC */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DAC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IrqHandler, /* 33 Analog Comparator */
|
||||
USBD_IrqHandler, /* 34 USB Device Port */
|
||||
Dummy_Handler /* 35 not used */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest ;
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext ;
|
||||
pDest = &_srelocate ;
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if ( pSrc != pDest )
|
||||
{
|
||||
for ( ; pDest < &_erelocate ; )
|
||||
{
|
||||
*pDest++ = *pSrc++ ;
|
||||
}
|
||||
}
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for ( pDest = &_szero ; pDest < &_ezero ; )
|
||||
{
|
||||
*pDest++ = 0;
|
||||
}
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *)&_sfixed;
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array() ;
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main() ;
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while ( 1 ) ;
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15,107 +15,99 @@
|
|||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
|
||||
typedef void( *intfunc )( void );
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
extern void __iar_program_start( void ) ;
|
||||
extern int __low_level_init( void ) ;
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0. */
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const intvec_elem __vector_table[] =
|
||||
{
|
||||
{ .__ptr = __sfe( "CSTACK" ) },
|
||||
{Reset_Handler},
|
||||
const intvec_elem __vector_table[] = {
|
||||
{.__ptr = __sfe("CSTACK")},
|
||||
{Reset_Handler},
|
||||
|
||||
{NMI_Handler},
|
||||
{HardFault_Handler},
|
||||
{MemManage_Handler},
|
||||
{BusFault_Handler},
|
||||
{UsageFault_Handler},
|
||||
{0}, {0}, {0}, {0}, /* Reserved */
|
||||
{SVC_Handler},
|
||||
{DebugMon_Handler},
|
||||
{0}, /* Reserved */
|
||||
{PendSV_Handler},
|
||||
{SysTick_Handler},
|
||||
{NMI_Handler},
|
||||
{HardFault_Handler},
|
||||
{MemManage_Handler},
|
||||
{BusFault_Handler},
|
||||
{UsageFault_Handler},
|
||||
{0}, {0}, {0}, {0}, /* Reserved */
|
||||
{SVC_Handler},
|
||||
{DebugMon_Handler},
|
||||
{0}, /* Reserved */
|
||||
{PendSV_Handler},
|
||||
{SysTick_Handler},
|
||||
|
||||
/* Configurable interrupts */
|
||||
{SUPC_IrqHandler}, /* 0 Supply Controller */
|
||||
{RSTC_IrqHandler}, /* 1 Reset Controller */
|
||||
{RTC_IrqHandler}, /* 2 Real Time Clock */
|
||||
{RTT_IrqHandler}, /* 3 Real Time Timer */
|
||||
{WDT_IrqHandler}, /* 4 Watchdog Timer */
|
||||
{PMC_IrqHandler}, /* 5 PMC */
|
||||
{EEFC_IrqHandler}, /* 6 EEFC */
|
||||
{Dummy_Handler}, /* 7 Reserved */
|
||||
{UART0_IrqHandler}, /* 8 UART0 */
|
||||
{UART1_IrqHandler}, /* 9 UART1 */
|
||||
{SMC_IrqHandler}, /* 10 SMC */
|
||||
{PIOA_IrqHandler}, /* 11 Parallel IO Controller A */
|
||||
{PIOB_IrqHandler}, /* 12 Parallel IO Controller B */
|
||||
{PIOC_IrqHandler}, /* 13 Parallel IO Controller C */
|
||||
{USART0_IrqHandler}, /* 14 USART 0 */
|
||||
{USART1_IrqHandler}, /* 15 USART 1 */
|
||||
{Dummy_Handler}, /* 16 Reserved */
|
||||
{Dummy_Handler}, /* 17 Reserved */
|
||||
{MCI_IrqHandler}, /* 18 MCI */
|
||||
{TWI0_IrqHandler}, /* 19 TWI 0 */
|
||||
{TWI1_IrqHandler}, /* 20 TWI 1 */
|
||||
{SPI_IrqHandler}, /* 21 SPI */
|
||||
{SSC_IrqHandler}, /* 22 SSC */
|
||||
{TC0_IrqHandler}, /* 23 Timer Counter 0 */
|
||||
{TC1_IrqHandler}, /* 24 Timer Counter 1 */
|
||||
{TC2_IrqHandler}, /* 25 Timer Counter 2 */
|
||||
{TC3_IrqHandler}, /* 26 Timer Counter 3 */
|
||||
{TC4_IrqHandler}, /* 27 Timer Counter 4 */
|
||||
{TC5_IrqHandler}, /* 28 Timer Counter 5 */
|
||||
{ADC_IrqHandler}, /* 29 ADC controller */
|
||||
{DAC_IrqHandler}, /* 30 DAC controller */
|
||||
{PWM_IrqHandler}, /* 31 PWM */
|
||||
{CRCCU_IrqHandler}, /* 32 CRC Calculation Unit */
|
||||
{ACC_IrqHandler}, /* 33 Analog Comparator */
|
||||
{USBD_IrqHandler}, /* 34 USB Device Port */
|
||||
{Dummy_Handler} /* 35 not used */
|
||||
/* Configurable interrupts */
|
||||
{SUPC_IrqHandler}, /* 0 Supply Controller */
|
||||
{RSTC_IrqHandler}, /* 1 Reset Controller */
|
||||
{RTC_IrqHandler}, /* 2 Real Time Clock */
|
||||
{RTT_IrqHandler}, /* 3 Real Time Timer */
|
||||
{WDT_IrqHandler}, /* 4 Watchdog Timer */
|
||||
{PMC_IrqHandler}, /* 5 PMC */
|
||||
{EEFC_IrqHandler}, /* 6 EEFC */
|
||||
{Dummy_Handler}, /* 7 Reserved */
|
||||
{UART0_IrqHandler}, /* 8 UART0 */
|
||||
{UART1_IrqHandler}, /* 9 UART1 */
|
||||
{SMC_IrqHandler}, /* 10 SMC */
|
||||
{PIOA_IrqHandler}, /* 11 Parallel IO Controller A */
|
||||
{PIOB_IrqHandler}, /* 12 Parallel IO Controller B */
|
||||
{PIOC_IrqHandler}, /* 13 Parallel IO Controller C */
|
||||
{USART0_IrqHandler}, /* 14 USART 0 */
|
||||
{USART1_IrqHandler}, /* 15 USART 1 */
|
||||
{Dummy_Handler}, /* 16 Reserved */
|
||||
{Dummy_Handler}, /* 17 Reserved */
|
||||
{MCI_IrqHandler}, /* 18 MCI */
|
||||
{TWI0_IrqHandler}, /* 19 TWI 0 */
|
||||
{TWI1_IrqHandler}, /* 20 TWI 1 */
|
||||
{SPI_IrqHandler}, /* 21 SPI */
|
||||
{SSC_IrqHandler}, /* 22 SSC */
|
||||
{TC0_IrqHandler}, /* 23 Timer Counter 0 */
|
||||
{TC1_IrqHandler}, /* 24 Timer Counter 1 */
|
||||
{TC2_IrqHandler}, /* 25 Timer Counter 2 */
|
||||
{TC3_IrqHandler}, /* 26 Timer Counter 3 */
|
||||
{TC4_IrqHandler}, /* 27 Timer Counter 4 */
|
||||
{TC5_IrqHandler}, /* 28 Timer Counter 5 */
|
||||
{ADC_IrqHandler}, /* 29 ADC controller */
|
||||
{DAC_IrqHandler}, /* 30 DAC controller */
|
||||
{PWM_IrqHandler}, /* 31 PWM */
|
||||
{CRCCU_IrqHandler}, /* 32 CRC Calculation Unit */
|
||||
{ACC_IrqHandler}, /* 33 Analog Comparator */
|
||||
{USBD_IrqHandler}, /* 34 USB Device Port */
|
||||
{Dummy_Handler} /* 35 not used */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern int __low_level_init( void )
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t* pSrc = __section_begin( ".intvec" ) ;
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < (uint32_t)IRAM_ADDR+(uint32_t)IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= (uint32_t)(1 << SCB_VTOR_TBLBASE_Pos) ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < (uint32_t) IRAM_ADDR + (uint32_t) IRAM_SIZE)) {
|
||||
SCB->VTOR |= (uint32_t) (1 << SCB_VTOR_TBLBASE_Pos);
|
||||
}
|
||||
|
||||
return 1 ; /* if return 0, the data sections will not be initialized. */
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* on chip startup.
|
||||
*
|
||||
* $asf_license$
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -26,102 +26,110 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Clock Settings (64MHz) */
|
||||
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
|
||||
#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0xfU) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3fU) \
|
||||
| CKGR_PLLAR_DIVA(0x3U))
|
||||
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
||||
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
|
||||
#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0xfU) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3fU) \
|
||||
| CKGR_PLLAR_DIVA(0x3U))
|
||||
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
||||
|
||||
/* Clock Definitions */
|
||||
#define XTAL32 ( 32768UL) /* 32k crystal frequency */
|
||||
#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
|
||||
#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
|
||||
#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
|
||||
#define MAINCK_XTAL_HZ (12000000UL) /* External crystal frequency */
|
||||
#define MCK_HZ (64000000UL) /* Processor frequency */
|
||||
#define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */
|
||||
#define SYS_FREQ_XTAL_XTAL12M (12000000UL) /* External 12M crystal frequency */
|
||||
|
||||
#define SYS_FREQ_FWS_0 (17000000UL) /* Maximum operating frequency when FWS is 0 */
|
||||
#define SYS_FREQ_FWS_1 (30000000UL) /* Maximum operating frequency when FWS is 1 */
|
||||
#define SYS_FREQ_FWS_2 (54000000UL) /* Maximum operating frequency when FWS is 2 */
|
||||
|
||||
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
|
||||
|
||||
/* FIXME: should be generated by sock */
|
||||
uint32_t SystemCoreClock = EFRC_OSC;
|
||||
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
/**
|
||||
* \brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
extern void SystemInit( void )
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(3U);
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
|
||||
/* Initialize main oscillator */
|
||||
if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
|
||||
{
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37U) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {}
|
||||
}
|
||||
/* Initialize main oscillator */
|
||||
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37U) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {}
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
|
||||
}
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
|
||||
PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {}
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
|
||||
}
|
||||
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = BOARD_MCKR ;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = SYS_BOARD_MCKR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
SystemCoreClock = MCK_HZ;
|
||||
SystemCoreClock = CHIP_FREQ_CPU_MAX;
|
||||
}
|
||||
|
||||
extern void SystemCoreClockUpdate( void )
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void)
|
||||
{
|
||||
/* Set FWS for Embedded Flash Access according operating frequency*/
|
||||
if(SystemCoreClock < SYS_FREQ_FWS_0){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_1){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
}else{
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT
|
||||
/*Disable the watchdog */
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch (PMC->PMC_MCKR & (uint32_t)PMC_MCKR_CSS_Msk) {
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
|
||||
SystemCoreClock = OSC32_CLK;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = ERC_OSC;
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) {
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
|
||||
SystemCoreClock = SYS_FREQ_XTAL_32K;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_SLCK_RC;
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
|
|
@ -136,13 +144,37 @@ extern void SystemCoreClockUpdate( void )
|
|||
break;
|
||||
}
|
||||
}
|
||||
if ((uint32_t)(PMC->PMC_MCKR & (uint32_t)PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FFU) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FFU));
|
||||
break;
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
else {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_MULB_Pos) & 0x7FFU) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_DIVB_Pos) & 0x0FFU));
|
||||
if ((uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
|
||||
CKGR_PLLAR_MULA_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
|
||||
CKGR_PLLAR_DIVA_Pos));
|
||||
} else {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
|
||||
CKGR_PLLBR_MULB_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>
|
||||
CKGR_PLLBR_DIVB_Pos));
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
|
@ -151,8 +183,7 @@ extern void SystemCoreClockUpdate( void )
|
|||
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
|
||||
SystemCoreClock /= 3U;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
}
|
||||
|
|
@ -164,4 +195,3 @@ extern void SystemCoreClockUpdate( void )
|
|||
#endif
|
||||
/**INDENT-ON**/
|
||||
/* @endcond */
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -34,13 +34,18 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
|||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -51,4 +56,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/* @endcond */
|
||||
|
||||
#endif /* SYSTEM_SAM3S_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,17 @@
|
|||
#ifndef _SAM3S8_
|
||||
#define _SAM3S8_
|
||||
|
||||
/* Device characteristics */
|
||||
#define CHIP_FREQ_SLCK_RC_MIN (20000U)
|
||||
#define CHIP_FREQ_SLCK_RC (32000U)
|
||||
#define CHIP_FREQ_SLCK_RC_MAX (44000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U)
|
||||
#define CHIP_FREQ_CPU_MAX (64000000U)
|
||||
|
||||
#define CHIP_FLASH_WAIT_STATE (3U)
|
||||
|
||||
#if defined __SAM3SD8A__
|
||||
#include "sam3sd8a.h"
|
||||
#elif defined __SAM3SD8B__
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \note
|
||||
|
|
@ -31,50 +31,50 @@ extern "C" {
|
|||
|
||||
#ifdef __GNUC__
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UsageFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SVC_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DebugMon_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PendSV_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SysTick_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void ACC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void ADC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void CRCCU_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DAC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EEFC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MCI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOA_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOB_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RSTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SPI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SSC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SUPC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC4_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC5_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USBD_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EEFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USBD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __ICCARM__
|
||||
|
|
@ -128,9 +128,10 @@ extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler")
|
|||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler( void )
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while ( 1 ) {}
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -26,56 +26,56 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Function prototype for exception table items (interrupt handler). */
|
||||
typedef void( *IntFunc )( void ) ;
|
||||
typedef void (*IntFunc) (void);
|
||||
|
||||
/* Default empty handler */
|
||||
extern void Dummy_Handler( void ) ;
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) ;
|
||||
extern void NMI_Handler( void ) ;
|
||||
extern void HardFault_Handler( void ) ;
|
||||
extern void MemManage_Handler( void ) ;
|
||||
extern void BusFault_Handler( void ) ;
|
||||
extern void UsageFault_Handler( void ) ;
|
||||
extern void SVC_Handler( void ) ;
|
||||
extern void DebugMon_Handler( void ) ;
|
||||
extern void PendSV_Handler( void ) ;
|
||||
extern void SysTick_Handler( void ) ;
|
||||
void Reset_Handler(void);
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void ACC_IrqHandler( void ) ;
|
||||
extern void ADC_IrqHandler( void ) ;
|
||||
extern void CRCCU_IrqHandler( void ) ;
|
||||
extern void DAC_IrqHandler( void ) ;
|
||||
extern void EEFC_IrqHandler( void ) ;
|
||||
extern void MCI_IrqHandler( void ) ;
|
||||
extern void PIOA_IrqHandler( void ) ;
|
||||
extern void PIOB_IrqHandler( void ) ;
|
||||
extern void PIOC_IrqHandler( void ) ;
|
||||
extern void PMC_IrqHandler( void ) ;
|
||||
extern void PWM_IrqHandler( void ) ;
|
||||
extern void RSTC_IrqHandler( void ) ;
|
||||
extern void RTC_IrqHandler( void ) ;
|
||||
extern void RTT_IrqHandler( void ) ;
|
||||
extern void SMC_IrqHandler( void ) ;
|
||||
extern void SPI_IrqHandler( void ) ;
|
||||
extern void SSC_IrqHandler( void ) ;
|
||||
extern void SUPC_IrqHandler( void ) ;
|
||||
extern void TC0_IrqHandler( void ) ;
|
||||
extern void TC1_IrqHandler( void ) ;
|
||||
extern void TC2_IrqHandler( void ) ;
|
||||
extern void TC3_IrqHandler( void ) ;
|
||||
extern void TC4_IrqHandler( void ) ;
|
||||
extern void TC5_IrqHandler( void ) ;
|
||||
extern void TWI0_IrqHandler( void ) ;
|
||||
extern void TWI1_IrqHandler( void ) ;
|
||||
extern void UART0_IrqHandler( void ) ;
|
||||
extern void UART1_IrqHandler( void ) ;
|
||||
extern void USART0_IrqHandler( void ) ;
|
||||
extern void USART1_IrqHandler( void ) ;
|
||||
extern void USBD_IrqHandler( void ) ;
|
||||
extern void WDT_IrqHandler( void ) ;
|
||||
void ACC_IrqHandler(void);
|
||||
void ADC_IrqHandler(void);
|
||||
void CRCCU_IrqHandler(void);
|
||||
void DAC_IrqHandler(void);
|
||||
void EEFC_IrqHandler(void);
|
||||
void MCI_IrqHandler(void);
|
||||
void PIOA_IrqHandler(void);
|
||||
void PIOB_IrqHandler(void);
|
||||
void PIOC_IrqHandler(void);
|
||||
void PMC_IrqHandler(void);
|
||||
void PWM_IrqHandler(void);
|
||||
void RSTC_IrqHandler(void);
|
||||
void RTC_IrqHandler(void);
|
||||
void RTT_IrqHandler(void);
|
||||
void SMC_IrqHandler(void);
|
||||
void SPI_IrqHandler(void);
|
||||
void SSC_IrqHandler(void);
|
||||
void SUPC_IrqHandler(void);
|
||||
void TC0_IrqHandler(void);
|
||||
void TC1_IrqHandler(void);
|
||||
void TC2_IrqHandler(void);
|
||||
void TC3_IrqHandler(void);
|
||||
void TC4_IrqHandler(void);
|
||||
void TC5_IrqHandler(void);
|
||||
void TWI0_IrqHandler(void);
|
||||
void TWI1_IrqHandler(void);
|
||||
void UART0_IrqHandler(void);
|
||||
void UART1_IrqHandler(void);
|
||||
void USART0_IrqHandler(void);
|
||||
void USART1_IrqHandler(void);
|
||||
void USBD_IrqHandler(void);
|
||||
void WDT_IrqHandler(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -86,4 +86,3 @@ extern void WDT_IrqHandler( void ) ;
|
|||
/* @endcond */
|
||||
|
||||
#endif /* EXCEPTIONS_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -12,14 +12,13 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3s8.h"
|
||||
#include "system_sam3sd8.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
/* Stack Configuration */
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8),section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE] ;
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8), section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE];
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
|
|
@ -31,115 +30,111 @@ extern uint32_t _szero;
|
|||
extern uint32_t _ezero;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
extern int main( void ) ;
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
extern void __libc_init_array( void ) ;
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__((section(".vectors")))
|
||||
__attribute__ ((section(".vectors")))
|
||||
IntFunc exception_table[] = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc)(&pdwStack[STACK_SIZE-1]),
|
||||
Reset_Handler,
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc) (&pdwStack[STACK_SIZE - 1]),
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EEFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
SMC_IrqHandler, /* 10 SMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
MCI_IrqHandler, /* 18 MCI */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
SSC_IrqHandler, /* 22 SSC */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DAC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IrqHandler, /* 33 Analog Comparator */
|
||||
USBD_IrqHandler, /* 34 USB Device Port */
|
||||
Dummy_Handler /* 35 not used */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EEFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
SMC_IrqHandler, /* 10 SMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
MCI_IrqHandler, /* 18 MCI */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
SSC_IrqHandler, /* 22 SSC */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DAC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IrqHandler, /* 33 Analog Comparator */
|
||||
USBD_IrqHandler, /* 34 USB Device Port */
|
||||
Dummy_Handler /* 35 not used */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest ;
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext ;
|
||||
pDest = &_srelocate ;
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if ( pSrc != pDest )
|
||||
{
|
||||
for ( ; pDest < &_erelocate ; )
|
||||
{
|
||||
*pDest++ = *pSrc++ ;
|
||||
}
|
||||
}
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for ( pDest = &_szero ; pDest < &_ezero ; )
|
||||
{
|
||||
*pDest++ = 0;
|
||||
}
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *)&_sfixed;
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array() ;
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main() ;
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while ( 1 ) ;
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,106 +12,102 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3s8.h"
|
||||
#include "system_sam3sd8.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
typedef void( *intfunc )( void );
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
extern void __iar_program_start( void ) ;
|
||||
extern int __low_level_init( void ) ;
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0. */
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const intvec_elem __vector_table[] =
|
||||
{
|
||||
{ .__ptr = __sfe( "CSTACK" ) },
|
||||
Reset_Handler,
|
||||
const intvec_elem __vector_table[] = {
|
||||
{.__ptr = __sfe("CSTACK")},
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EEFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
SMC_IrqHandler, /* 10 SMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
MCI_IrqHandler, /* 18 MCI */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
SSC_IrqHandler, /* 22 SSC */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DAC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IrqHandler, /* 33 Analog Comparator */
|
||||
USBD_IrqHandler, /* 34 USB Device Port */
|
||||
Dummy_Handler /* 35 not used */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EEFC_IrqHandler, /* 6 EEFC */
|
||||
Dummy_Handler, /* 7 Reserved */
|
||||
UART0_IrqHandler, /* 8 UART0 */
|
||||
UART1_IrqHandler, /* 9 UART1 */
|
||||
SMC_IrqHandler, /* 10 SMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 14 USART 0 */
|
||||
USART1_IrqHandler, /* 15 USART 1 */
|
||||
Dummy_Handler, /* 16 Reserved */
|
||||
Dummy_Handler, /* 17 Reserved */
|
||||
MCI_IrqHandler, /* 18 MCI */
|
||||
TWI0_IrqHandler, /* 19 TWI 0 */
|
||||
TWI1_IrqHandler, /* 20 TWI 1 */
|
||||
SPI_IrqHandler, /* 21 SPI */
|
||||
SSC_IrqHandler, /* 22 SSC */
|
||||
TC0_IrqHandler, /* 23 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 24 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 25 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 26 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 27 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 28 Timer Counter 5 */
|
||||
ADC_IrqHandler, /* 29 ADC controller */
|
||||
DAC_IrqHandler, /* 30 DAC controller */
|
||||
PWM_IrqHandler, /* 31 PWM */
|
||||
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
|
||||
ACC_IrqHandler, /* 33 Analog Comparator */
|
||||
USBD_IrqHandler, /* 34 USB Device Port */
|
||||
Dummy_Handler /* 35 not used */
|
||||
};
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern int __low_level_init( void )
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t* pSrc = __section_begin( ".intvec" ) ;
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
return 1 ; /* if return 0, the data sections will not be initialized. */
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* on chip startup.
|
||||
*
|
||||
* $asf_license$
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -27,133 +27,164 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Clock settings (64MHz) */
|
||||
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0xf) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3f) \
|
||||
| CKGR_PLLAR_DIVA(0x3))
|
||||
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
||||
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0xf) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3f) \
|
||||
| CKGR_PLLAR_DIVA(0x3))
|
||||
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
||||
|
||||
/* Clock Definitions */
|
||||
#define XTAL32 ( 32768UL) /* 32k crystal frequency */
|
||||
#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
|
||||
#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
|
||||
#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
|
||||
#define MAINCK_XTAL_HZ (12000000UL) /* External crystal frequency */
|
||||
#define MCK_HZ (64000000UL) /* Processor frequency */
|
||||
#define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */
|
||||
#define SYS_FREQ_XTAL_XTAL12M (12000000UL) /* External 12M crystal frequency */
|
||||
|
||||
#define SYS_FREQ_FWS_0 (21000000UL) /* Maximum operating frequency when FWS is 0 */
|
||||
#define SYS_FREQ_FWS_1 (35000000UL) /* Maximum operating frequency when FWS is 1 */
|
||||
#define SYS_FREQ_FWS_2 (60000000UL) /* Maximum operating frequency when FWS is 2 */
|
||||
|
||||
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
|
||||
|
||||
/* FIXME: should be generated by sock */
|
||||
uint32_t SystemCoreClock = EFRC_OSC;
|
||||
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
/**
|
||||
* \brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
extern void SystemInit( void )
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
|
||||
/* Initialize main oscillator */
|
||||
if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
|
||||
{
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
|
||||
}
|
||||
/* Initialize main oscillator */
|
||||
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN |
|
||||
CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
|
||||
}
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA));
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
|
||||
}
|
||||
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = BOARD_MCKR ;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = SYS_BOARD_MCKR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
SystemCoreClock = MCK_HZ;
|
||||
SystemCoreClock = CHIP_FREQ_CPU_MAX;
|
||||
}
|
||||
|
||||
extern void SystemCoreClockUpdate( void )
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void)
|
||||
{
|
||||
/* Set FWS for Embedded Flash Access according operating frequency*/
|
||||
if(SystemCoreClock < SYS_FREQ_FWS_0){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_1){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
}else{
|
||||
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT
|
||||
/*Disable the watchdog */
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
|
||||
SystemCoreClock = OSC32_CLK;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = ERC_OSC;
|
||||
}
|
||||
SystemCoreClock = SYS_FREQ_XTAL_32K;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_SLCK_RC;
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2;
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3;
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2;
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3;
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FF) + 1);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FF));
|
||||
}
|
||||
else {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_MULB_Pos) & 0x7FF) + 1);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_DIVB_Pos) & 0x0FF));
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
|
||||
CKGR_PLLAR_MULA_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
|
||||
CKGR_PLLAR_DIVA_Pos));
|
||||
} else {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
|
||||
CKGR_PLLBR_MULB_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>
|
||||
CKGR_PLLBR_DIVB_Pos));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
|
||||
SystemCoreClock /= 3;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
SystemCoreClock /= 3U;
|
||||
} else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
|
||||
PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -34,13 +34,18 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
|||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -51,4 +56,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/* @endcond */
|
||||
|
||||
#endif /* SYSTEM_SAM3SD8_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,17 @@
|
|||
#ifndef _SAM3U_
|
||||
#define _SAM3U_
|
||||
|
||||
/* Device characteristics */
|
||||
#define CHIP_FREQ_SLCK_RC_MIN (20000U)
|
||||
#define CHIP_FREQ_SLCK_RC (32000U)
|
||||
#define CHIP_FREQ_SLCK_RC_MAX (44000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U)
|
||||
#define CHIP_FREQ_CPU_MAX (96000000U)
|
||||
|
||||
#define CHIP_FLASH_WAIT_STATE (3U)
|
||||
|
||||
#if defined __SAM3U1C__
|
||||
#include "sam3u1c.h"
|
||||
#elif defined __SAM3U1E__
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \note
|
||||
|
|
@ -31,48 +31,48 @@ extern "C" {
|
|||
|
||||
#ifdef __GNUC__
|
||||
/* Cortex-M3 core handlers */
|
||||
//extern void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
//extern void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UsageFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SVC_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DebugMon_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PendSV_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SysTick_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
//void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
//void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void SUPC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RSTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EFC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EFC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UART_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOA_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOB_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MCI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SPI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SSC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void ADC12B_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void ADC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DMAC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UDPHS_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EFC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EFC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UART_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void ADC12B_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DMAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UDPHS_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __ICCARM__
|
||||
|
|
@ -124,9 +124,10 @@ extern void UDPHS_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler
|
|||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler( void )
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while ( 1 ) {}
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
@ -136,4 +137,3 @@ void Dummy_Handler( void )
|
|||
#endif
|
||||
/**INDENT-ON**/
|
||||
/* @endcond */
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -26,54 +26,54 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Function prototype for exception table items (interrupt handler). */
|
||||
typedef void( *IntFunc )( void ) ;
|
||||
typedef void (*IntFunc) (void);
|
||||
|
||||
/* Default empty handler */
|
||||
extern void Dummy_Handler( void ) ;
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) ;
|
||||
extern void NMI_Handler( void ) ;
|
||||
extern void HardFault_Handler( void ) ;
|
||||
extern void MemManage_Handler( void ) ;
|
||||
extern void BusFault_Handler( void ) ;
|
||||
extern void UsageFault_Handler( void ) ;
|
||||
extern void SVC_Handler( void ) ;
|
||||
extern void DebugMon_Handler( void ) ;
|
||||
extern void PendSV_Handler( void ) ;
|
||||
extern void SysTick_Handler( void ) ;
|
||||
void Reset_Handler(void);
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void SUPC_IrqHandler( void ) ;
|
||||
extern void RSTC_IrqHandler( void ) ;
|
||||
extern void RTC_IrqHandler( void ) ;
|
||||
extern void RTT_IrqHandler( void ) ;
|
||||
extern void WDT_IrqHandler( void ) ;
|
||||
extern void PMC_IrqHandler( void ) ;
|
||||
extern void EFC0_IrqHandler( void ) ;
|
||||
extern void EFC1_IrqHandler( void ) ;
|
||||
extern void UART_IrqHandler( void ) ;
|
||||
extern void SMC_IrqHandler( void ) ;
|
||||
extern void PIOA_IrqHandler( void ) ;
|
||||
extern void PIOB_IrqHandler( void ) ;
|
||||
extern void PIOC_IrqHandler( void ) ;
|
||||
extern void USART0_IrqHandler( void ) ;
|
||||
extern void USART1_IrqHandler( void ) ;
|
||||
extern void USART2_IrqHandler( void ) ;
|
||||
extern void USART3_IrqHandler( void ) ;
|
||||
extern void MCI_IrqHandler( void ) ;
|
||||
extern void TWI0_IrqHandler( void ) ;
|
||||
extern void TWI1_IrqHandler( void ) ;
|
||||
extern void SPI_IrqHandler( void ) ;
|
||||
extern void SSC_IrqHandler( void ) ;
|
||||
extern void TC0_IrqHandler( void ) ;
|
||||
extern void TC1_IrqHandler( void ) ;
|
||||
extern void TC2_IrqHandler( void ) ;
|
||||
extern void PWM_IrqHandler( void ) ;
|
||||
extern void ADC12B_IrqHandler( void ) ;
|
||||
extern void ADC_IrqHandler( void ) ;
|
||||
extern void DMAC_IrqHandler( void ) ;
|
||||
extern void UDPHS_IrqHandler( void ) ;
|
||||
void SUPC_IrqHandler(void);
|
||||
void RSTC_IrqHandler(void);
|
||||
void RTC_IrqHandler(void);
|
||||
void RTT_IrqHandler(void);
|
||||
void WDT_IrqHandler(void);
|
||||
void PMC_IrqHandler(void);
|
||||
void EFC0_IrqHandler(void);
|
||||
void EFC1_IrqHandler(void);
|
||||
void UART_IrqHandler(void);
|
||||
void SMC_IrqHandler(void);
|
||||
void PIOA_IrqHandler(void);
|
||||
void PIOB_IrqHandler(void);
|
||||
void PIOC_IrqHandler(void);
|
||||
void USART0_IrqHandler(void);
|
||||
void USART1_IrqHandler(void);
|
||||
void USART2_IrqHandler(void);
|
||||
void USART3_IrqHandler(void);
|
||||
void MCI_IrqHandler(void);
|
||||
void TWI0_IrqHandler(void);
|
||||
void TWI1_IrqHandler(void);
|
||||
void SPI_IrqHandler(void);
|
||||
void SSC_IrqHandler(void);
|
||||
void TC0_IrqHandler(void);
|
||||
void TC1_IrqHandler(void);
|
||||
void TC2_IrqHandler(void);
|
||||
void PWM_IrqHandler(void);
|
||||
void ADC12B_IrqHandler(void);
|
||||
void ADC_IrqHandler(void);
|
||||
void DMAC_IrqHandler(void);
|
||||
void UDPHS_IrqHandler(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -84,4 +84,3 @@ extern void UDPHS_IrqHandler( void ) ;
|
|||
/* @endcond */
|
||||
|
||||
#endif /* EXCEPTIONS_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -12,14 +12,13 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3u.h"
|
||||
#include "system_sam3u.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
/* Stack Configuration */
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8),section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE] ;
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8), section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE];
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
|
|
@ -31,109 +30,105 @@ extern uint32_t _szero;
|
|||
extern uint32_t _ezero;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
extern int main( void ) ;
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
extern void __libc_init_array( void ) ;
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__((section(".vectors")))
|
||||
__attribute__ ((section(".vectors")))
|
||||
IntFunc exception_table[] = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc)(&pdwStack[STACK_SIZE-1]),
|
||||
Reset_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc) (&pdwStack[STACK_SIZE - 1]),
|
||||
Reset_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EEFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EEFC 1 */
|
||||
UART_IrqHandler, /* 8 UART0 */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
PIOA_IrqHandler, /* 10 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 11 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 12 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 13 USART 0 */
|
||||
USART1_IrqHandler, /* 14 USART 1 */
|
||||
USART2_IrqHandler, /* 15 USART 2 */
|
||||
USART3_IrqHandler, /* 16 USART 3 */
|
||||
MCI_IrqHandler, /* 17 MCI */
|
||||
TWI0_IrqHandler, /* 18 TWI 0 */
|
||||
TWI1_IrqHandler, /* 19 TWI 1 */
|
||||
SPI_IrqHandler, /* 20 SPI */
|
||||
SSC_IrqHandler, /* 21 SSC */
|
||||
TC0_IrqHandler, /* 22 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 23 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 24 Timer Counter 2 */
|
||||
PWM_IrqHandler, /* 25 PWM */
|
||||
ADC12B_IrqHandler, /* 26 ADC12B controller */
|
||||
ADC_IrqHandler, /* 27 ADC controller */
|
||||
DMAC_IrqHandler, /* 28 DMA controller */
|
||||
UDPHS_IrqHandler, /* 29 USB High Speed Port */
|
||||
Dummy_Handler /* 30 not used */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EEFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EEFC 1 */
|
||||
UART_IrqHandler, /* 8 UART0 */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
PIOA_IrqHandler, /* 10 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 11 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 12 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 13 USART 0 */
|
||||
USART1_IrqHandler, /* 14 USART 1 */
|
||||
USART2_IrqHandler, /* 15 USART 2 */
|
||||
USART3_IrqHandler, /* 16 USART 3 */
|
||||
MCI_IrqHandler, /* 17 MCI */
|
||||
TWI0_IrqHandler, /* 18 TWI 0 */
|
||||
TWI1_IrqHandler, /* 19 TWI 1 */
|
||||
SPI_IrqHandler, /* 20 SPI */
|
||||
SSC_IrqHandler, /* 21 SSC */
|
||||
TC0_IrqHandler, /* 22 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 23 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 24 Timer Counter 2 */
|
||||
PWM_IrqHandler, /* 25 PWM */
|
||||
ADC12B_IrqHandler, /* 26 ADC12B controller */
|
||||
ADC_IrqHandler, /* 27 ADC controller */
|
||||
DMAC_IrqHandler, /* 28 DMA controller */
|
||||
UDPHS_IrqHandler, /* 29 USB High Speed Port */
|
||||
Dummy_Handler /* 30 not used */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest ;
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext ;
|
||||
pDest = &_srelocate ;
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if ( pSrc != pDest )
|
||||
{
|
||||
for ( ; pDest < &_erelocate ; )
|
||||
{
|
||||
*pDest++ = *pSrc++ ;
|
||||
}
|
||||
}
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for ( pDest = &_szero ; pDest < &_ezero ; )
|
||||
{
|
||||
*pDest++ = 0;
|
||||
}
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *)&_sfixed;
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM0_ADDR) && ((uint32_t)pSrc < IRAM0_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array() ;
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main() ;
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while ( 1 ) ;
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,105 +12,97 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "board.h"
|
||||
#include "system_sam3u.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
typedef void( *intfunc )( void );
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
extern void __iar_program_start( void ) ;
|
||||
extern int __low_level_init( void ) ;
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0. */
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const intvec_elem __vector_table[] =
|
||||
{
|
||||
{ .__ptr = __sfe( "CSTACK" ) },
|
||||
Reset_Handler,
|
||||
const intvec_elem __vector_table[] = {
|
||||
{.__ptr = __sfe("CSTACK")},
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EEFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EEFC 1 */
|
||||
UART_IrqHandler, /* 8 UART0 */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
PIOA_IrqHandler, /* 10 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 11 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 12 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 13 USART 0 */
|
||||
USART1_IrqHandler, /* 14 USART 1 */
|
||||
USART2_IrqHandler, /* 15 USART 2 */
|
||||
USART3_IrqHandler, /* 16 USART 3 */
|
||||
MCI_IrqHandler, /* 17 MCI */
|
||||
TWI0_IrqHandler, /* 18 TWI 0 */
|
||||
TWI1_IrqHandler, /* 19 TWI 1 */
|
||||
SPI_IrqHandler, /* 20 SPI */
|
||||
SSC_IrqHandler, /* 21 SSC */
|
||||
TC0_IrqHandler, /* 22 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 23 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 24 Timer Counter 2 */
|
||||
PWM_IrqHandler, /* 25 PWM */
|
||||
ADC12B_IrqHandler, /* 26 ADC12B controller */
|
||||
ADC_IrqHandler, /* 27 ADC controller */
|
||||
DMAC_IrqHandler, /* 28 DMA controller */
|
||||
UDPHS_IrqHandler, /* 29 USB High Speed Port */
|
||||
Dummy_Handler /* 30 not used */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EEFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EEFC 1 */
|
||||
UART_IrqHandler, /* 8 UART0 */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
PIOA_IrqHandler, /* 10 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 11 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 12 Parallel IO Controller C */
|
||||
USART0_IrqHandler, /* 13 USART 0 */
|
||||
USART1_IrqHandler, /* 14 USART 1 */
|
||||
USART2_IrqHandler, /* 15 USART 2 */
|
||||
USART3_IrqHandler, /* 16 USART 3 */
|
||||
MCI_IrqHandler, /* 17 MCI */
|
||||
TWI0_IrqHandler, /* 18 TWI 0 */
|
||||
TWI1_IrqHandler, /* 19 TWI 1 */
|
||||
SPI_IrqHandler, /* 20 SPI */
|
||||
SSC_IrqHandler, /* 21 SSC */
|
||||
TC0_IrqHandler, /* 22 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 23 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 24 Timer Counter 2 */
|
||||
PWM_IrqHandler, /* 25 PWM */
|
||||
ADC12B_IrqHandler, /* 26 ADC12B controller */
|
||||
ADC_IrqHandler, /* 27 ADC controller */
|
||||
DMAC_IrqHandler, /* 28 DMA controller */
|
||||
UDPHS_IrqHandler, /* 29 USB High Speed Port */
|
||||
Dummy_Handler /* 30 not used */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern int __low_level_init( void )
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t* pSrc = __section_begin( ".intvec" ) ;
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM0_ADDR) && ((uint32_t)pSrc < IRAM0_ADDR+IRAM_SIZE) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < IRAM0_ADDR + IRAM_SIZE)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
return 1 ; /* if return 0, the data sections will not be initialized. */
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* on chip startup.
|
||||
*
|
||||
* $asf_license$
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -27,134 +27,172 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Clock settings (96MHz) */
|
||||
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0x7) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3f) \
|
||||
| CKGR_PLLAR_DIVA(0x1))
|
||||
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
||||
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0x7) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3f) \
|
||||
| CKGR_PLLAR_DIVA(0x1))
|
||||
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
|
||||
|
||||
/* Clock Definitions */
|
||||
#define XTAL32 ( 32768UL) /* 32k crystal frequency */
|
||||
#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
|
||||
#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
|
||||
#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
|
||||
#define UTMIPLL (480000000UL) /* UTMI PLL frequency */
|
||||
#define MAINCK_XTAL_HZ (12000000UL) /* External crystal frequency */
|
||||
#define MCK_HZ (96000000UL) /* Processor frequency */
|
||||
#define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */
|
||||
#define SYS_FREQ_XTAL_XTAL12M (12000000UL) /* External 12M crystal frequency */
|
||||
#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */
|
||||
|
||||
#define SYS_FREQ_FWS_0 (24000000UL) /* Maximum operating frequency when FWS is 0 */
|
||||
#define SYS_FREQ_FWS_1 (40000000UL) /* Maximum operating frequency when FWS is 1 */
|
||||
#define SYS_FREQ_FWS_2 (72000000UL) /* Maximum operating frequency when FWS is 2 */
|
||||
#define SYS_FREQ_FWS_3 (84000000UL) /* Maximum operating frequency when FWS is 3 */
|
||||
|
||||
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
|
||||
|
||||
/* FIXME: should be generated by sock */
|
||||
uint32_t SystemCoreClock = EFRC_OSC;
|
||||
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
/**
|
||||
* \brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
extern void SystemInit( void )
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
|
||||
/* Initialize main oscillator */
|
||||
if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
|
||||
{
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
|
||||
}
|
||||
/* Initialize main oscillator */
|
||||
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
|
||||
}
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
|
||||
PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA));
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
|
||||
}
|
||||
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = BOARD_MCKR ;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = SYS_BOARD_MCKR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
SystemCoreClock = MCK_HZ;
|
||||
SystemCoreClock = CHIP_FREQ_CPU_MAX;
|
||||
}
|
||||
|
||||
extern void SystemCoreClockUpdate( void )
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void)
|
||||
{
|
||||
/* Set FWS for Embedded Flash Access according operating frequency*/
|
||||
if(SystemCoreClock < SYS_FREQ_FWS_0){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_1){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
}else{
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT
|
||||
/*Disable the watchdog */
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
|
||||
SystemCoreClock = OSC32_CLK;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = ERC_OSC;
|
||||
}
|
||||
SystemCoreClock = SYS_FREQ_XTAL_32K;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_SLCK_RC;
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2;
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3;
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2;
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3;
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FF) + 1);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FF));
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = UTMIPLL/2;
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
|
||||
CKGR_PLLAR_MULA_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
|
||||
CKGR_PLLAR_DIVA_Pos));
|
||||
} else {
|
||||
SystemCoreClock = SYS_UTMIPLL / 2U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
|
||||
SystemCoreClock /= 3;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
SystemCoreClock /= 3U;
|
||||
} else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
|
||||
PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
@ -164,4 +202,3 @@ extern void SystemCoreClockUpdate( void )
|
|||
#endif
|
||||
/**INDENT-ON**/
|
||||
/* @endcond */
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -34,13 +34,18 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
|||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -51,4 +56,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/* @endcond */
|
||||
|
||||
#endif /* SYSTEM_SAM3U_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -3,6 +3,17 @@
|
|||
#ifndef _SAM3XA_
|
||||
#define _SAM3XA_
|
||||
|
||||
/* Device characteristics */
|
||||
#define CHIP_FREQ_SLCK_RC_MIN (20000U)
|
||||
#define CHIP_FREQ_SLCK_RC (32000U)
|
||||
#define CHIP_FREQ_SLCK_RC_MAX (44000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000U)
|
||||
#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000U)
|
||||
#define CHIP_FREQ_CPU_MAX (84000000U)
|
||||
|
||||
#define CHIP_FLASH_WAIT_STATE (3U)
|
||||
|
||||
#if defined __SAM3A2C__
|
||||
#include "sam3a2c.h"
|
||||
#elif defined __SAM3A4C__
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \note
|
||||
|
|
@ -31,72 +31,72 @@ extern "C" {
|
|||
|
||||
#ifdef __GNUC__
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UsageFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SVC_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DebugMon_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PendSV_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SysTick_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
//void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
//void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void ACC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void ADC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void CAN0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void CAN1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void CRCCU_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DACC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void DMAC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EFC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EFC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void EMAC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void HSMCI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOA_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOB_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOD_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOE_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PIOF_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RSTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void RTT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SDRAMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SPI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SPI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SSC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void SUPC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC4_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC5_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC6_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC7_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TC8_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TRNG_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void TWI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UART_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void UOTGHS_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void USART3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
|
||||
void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void CAN0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void CAN1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void DMAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EFC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EFC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void EMAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void HSMCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOE_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PIOF_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SDRAMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SPI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SPI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC6_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC7_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TC8_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TRNG_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UART_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void UOTGHS_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void USART3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
#ifdef __ICCARM__
|
||||
/* Cortex-M3 core handlers */
|
||||
#pragma weak Reset_Handler=Dummy_Handler
|
||||
//#pragma weak Reset_Handler=Dummy_Handler
|
||||
#pragma weak NMI_Handler=Dummy_Handler
|
||||
#pragma weak HardFault_Handler=Dummy_Handler
|
||||
//#pragma weak HardFault_Handler=Dummy_Handler
|
||||
#pragma weak MemManage_Handler=Dummy_Handler
|
||||
#pragma weak BusFault_Handler=Dummy_Handler
|
||||
#pragma weak UsageFault_Handler=Dummy_Handler
|
||||
|
|
@ -158,9 +158,10 @@ extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler")
|
|||
/**
|
||||
* \brief Default interrupt handler for unused IRQs.
|
||||
*/
|
||||
void Dummy_Handler( void )
|
||||
void Dummy_Handler(void)
|
||||
{
|
||||
while ( 1 ) {}
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -26,71 +26,71 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Function prototype for exception table items (interrupt handler). */
|
||||
typedef void( *IntFunc )( void ) ;
|
||||
typedef void (*IntFunc) (void);
|
||||
|
||||
/* Default empty handler */
|
||||
extern void Dummy_Handler( void ) ;
|
||||
void Dummy_Handler(void);
|
||||
|
||||
/* Cortex-M3 core handlers */
|
||||
extern void Reset_Handler( void ) ;
|
||||
extern void NMI_Handler( void ) ;
|
||||
extern void HardFault_Handler( void ) ;
|
||||
extern void MemManage_Handler( void ) ;
|
||||
extern void BusFault_Handler( void ) ;
|
||||
extern void UsageFault_Handler( void ) ;
|
||||
extern void SVC_Handler( void ) ;
|
||||
extern void DebugMon_Handler( void ) ;
|
||||
extern void PendSV_Handler( void ) ;
|
||||
extern void SysTick_Handler( void ) ;
|
||||
void Reset_Handler(void);
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
/* Peripherals handlers */
|
||||
extern void ACC_IrqHandler( void ) ;
|
||||
extern void ADC_IrqHandler( void ) ;
|
||||
extern void CAN0_IrqHandler( void ) ;
|
||||
extern void CAN1_IrqHandler( void ) ;
|
||||
extern void CRCCU_IrqHandler( void ) ;
|
||||
extern void DACC_IrqHandler( void ) ;
|
||||
extern void DMAC_IrqHandler( void ) ;
|
||||
extern void EFC0_IrqHandler( void ) ;
|
||||
extern void EFC1_IrqHandler( void ) ;
|
||||
extern void EMAC_IrqHandler( void ) ;
|
||||
extern void HSMCI_IrqHandler( void ) ;
|
||||
extern void PIOA_IrqHandler( void ) ;
|
||||
extern void PIOB_IrqHandler( void ) ;
|
||||
extern void PIOC_IrqHandler( void ) ;
|
||||
extern void PIOD_IrqHandler( void ) ;
|
||||
extern void PIOE_IrqHandler( void ) ;
|
||||
extern void PIOF_IrqHandler( void ) ;
|
||||
extern void PMC_IrqHandler( void ) ;
|
||||
extern void PWM_IrqHandler( void ) ;
|
||||
extern void RSTC_IrqHandler( void ) ;
|
||||
extern void RTC_IrqHandler( void ) ;
|
||||
extern void RTT_IrqHandler( void ) ;
|
||||
extern void SDRAMC_IrqHandler( void ) ;
|
||||
extern void SMC_IrqHandler( void ) ;
|
||||
extern void SPI0_IrqHandler( void ) ;
|
||||
extern void SPI1_IrqHandler( void ) ;
|
||||
extern void SSC_IrqHandler( void ) ;
|
||||
extern void SUPC_IrqHandler( void ) ;
|
||||
extern void TC0_IrqHandler( void ) ;
|
||||
extern void TC1_IrqHandler( void ) ;
|
||||
extern void TC2_IrqHandler( void ) ;
|
||||
extern void TC3_IrqHandler( void ) ;
|
||||
extern void TC4_IrqHandler( void ) ;
|
||||
extern void TC5_IrqHandler( void ) ;
|
||||
extern void TC6_IrqHandler( void ) ;
|
||||
extern void TC7_IrqHandler( void ) ;
|
||||
extern void TC8_IrqHandler( void ) ;
|
||||
extern void TRNG_IrqHandler( void ) ;
|
||||
extern void TWI0_IrqHandler( void ) ;
|
||||
extern void TWI1_IrqHandler( void ) ;
|
||||
extern void UART_IrqHandler( void ) ;
|
||||
extern void UOTGHS_IrqHandler( void ) ;
|
||||
extern void USART0_IrqHandler( void ) ;
|
||||
extern void USART1_IrqHandler( void ) ;
|
||||
extern void USART2_IrqHandler( void ) ;
|
||||
extern void USART3_IrqHandler( void ) ;
|
||||
extern void WDT_IrqHandler( void ) ;
|
||||
void ACC_IrqHandler(void);
|
||||
void ADC_IrqHandler(void);
|
||||
void CAN0_IrqHandler(void);
|
||||
void CAN1_IrqHandler(void);
|
||||
void CRCCU_IrqHandler(void);
|
||||
void DACC_IrqHandler(void);
|
||||
void DMAC_IrqHandler(void);
|
||||
void EFC0_IrqHandler(void);
|
||||
void EFC1_IrqHandler(void);
|
||||
void EMAC_IrqHandler(void);
|
||||
void HSMCI_IrqHandler(void);
|
||||
void PIOA_IrqHandler(void);
|
||||
void PIOB_IrqHandler(void);
|
||||
void PIOC_IrqHandler(void);
|
||||
void PIOD_IrqHandler(void);
|
||||
void PIOE_IrqHandler(void);
|
||||
void PIOF_IrqHandler(void);
|
||||
void PMC_IrqHandler(void);
|
||||
void PWM_IrqHandler(void);
|
||||
void RSTC_IrqHandler(void);
|
||||
void RTC_IrqHandler(void);
|
||||
void RTT_IrqHandler(void);
|
||||
void SDRAMC_IrqHandler(void);
|
||||
void SMC_IrqHandler(void);
|
||||
void SPI0_IrqHandler(void);
|
||||
void SPI1_IrqHandler(void);
|
||||
void SSC_IrqHandler(void);
|
||||
void SUPC_IrqHandler(void);
|
||||
void TC0_IrqHandler(void);
|
||||
void TC1_IrqHandler(void);
|
||||
void TC2_IrqHandler(void);
|
||||
void TC3_IrqHandler(void);
|
||||
void TC4_IrqHandler(void);
|
||||
void TC5_IrqHandler(void);
|
||||
void TC6_IrqHandler(void);
|
||||
void TC7_IrqHandler(void);
|
||||
void TC8_IrqHandler(void);
|
||||
void TRNG_IrqHandler(void);
|
||||
void TWI0_IrqHandler(void);
|
||||
void TWI1_IrqHandler(void);
|
||||
void UART_IrqHandler(void);
|
||||
void UOTGHS_IrqHandler(void);
|
||||
void USART0_IrqHandler(void);
|
||||
void USART1_IrqHandler(void);
|
||||
void USART2_IrqHandler(void);
|
||||
void USART3_IrqHandler(void);
|
||||
void WDT_IrqHandler(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -101,4 +101,3 @@ extern void WDT_IrqHandler( void ) ;
|
|||
/* @endcond */
|
||||
|
||||
#endif /* EXCEPTIONS_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
|
|
@ -12,14 +12,13 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3xa.h"
|
||||
#include "system_sam3x.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
/* Stack Configuration */
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8),section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE] ;
|
||||
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
|
||||
__attribute__ ((aligned(8), section(".stack")))
|
||||
uint32_t pdwStack[STACK_SIZE];
|
||||
|
||||
/* Initialize segments */
|
||||
extern uint32_t _sfixed;
|
||||
|
|
@ -31,125 +30,120 @@ extern uint32_t _szero;
|
|||
extern uint32_t _ezero;
|
||||
|
||||
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
|
||||
extern int main( void ) ;
|
||||
int main(void);
|
||||
/** \endcond */
|
||||
void ResetException( void ) ;
|
||||
extern void __libc_init_array( void ) ;
|
||||
|
||||
void __libc_init_array(void);
|
||||
|
||||
/* Exception Table */
|
||||
__attribute__((section(".vectors")))
|
||||
__attribute__ ((section(".vectors")))
|
||||
IntFunc exception_table[] = {
|
||||
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc)(&pdwStack[STACK_SIZE-1]),
|
||||
ResetException,
|
||||
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||
(IntFunc) (&pdwStack[STACK_SIZE - 1]),
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EFC 1 */
|
||||
UART_IrqHandler, /* 8 UART */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
SDRAMC_IrqHandler, /* 10 SDRAMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
PIOD_IrqHandler, /* 14 Parallel IO Controller D */
|
||||
PIOE_IrqHandler, /* 15 Parallel IO Controller E */
|
||||
PIOF_IrqHandler, /* 16 Parallel IO Controller F */
|
||||
USART0_IrqHandler, /* 17 USART 0 */
|
||||
USART1_IrqHandler, /* 18 USART 1 */
|
||||
USART2_IrqHandler, /* 19 USART 2 */
|
||||
USART3_IrqHandler, /* 20 USART 3 */
|
||||
HSMCI_IrqHandler, /* 21 MCI */
|
||||
TWI0_IrqHandler, /* 22 TWI 0 */
|
||||
TWI1_IrqHandler, /* 23 TWI 1 */
|
||||
SPI0_IrqHandler, /* 24 SPI 0 */
|
||||
SPI1_IrqHandler, /* 25 SPI 1 */
|
||||
SSC_IrqHandler, /* 26 SSC */
|
||||
TC0_IrqHandler, /* 27 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 28 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 29 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 30 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 31 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 32 Timer Counter 5 */
|
||||
TC6_IrqHandler, /* 33 Timer Counter 6 */
|
||||
TC7_IrqHandler, /* 34 Timer Counter 7 */
|
||||
TC8_IrqHandler, /* 35 Timer Counter 8 */
|
||||
PWM_IrqHandler, /* 36 PWM */
|
||||
ADC_IrqHandler, /* 37 ADC controller */
|
||||
DACC_IrqHandler, /* 38 DAC controller */
|
||||
DMAC_IrqHandler, /* 39 DMA Controller */
|
||||
UOTGHS_IrqHandler, /* 40 USB OTG High Speed */
|
||||
TRNG_IrqHandler, /* 41 True Random Number Generator */
|
||||
EMAC_IrqHandler, /* 42 Ethernet MAC */
|
||||
CAN0_IrqHandler, /* 43 CAN Controller 0 */
|
||||
CAN1_IrqHandler, /* 44 CAN Controller 1 */
|
||||
} ;
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EFC 1 */
|
||||
UART_IrqHandler, /* 8 UART */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
SDRAMC_IrqHandler, /* 10 SDRAMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
PIOD_IrqHandler, /* 14 Parallel IO Controller D */
|
||||
PIOE_IrqHandler, /* 15 Parallel IO Controller E */
|
||||
PIOF_IrqHandler, /* 16 Parallel IO Controller F */
|
||||
USART0_IrqHandler, /* 17 USART 0 */
|
||||
USART1_IrqHandler, /* 18 USART 1 */
|
||||
USART2_IrqHandler, /* 19 USART 2 */
|
||||
USART3_IrqHandler, /* 20 USART 3 */
|
||||
HSMCI_IrqHandler, /* 21 MCI */
|
||||
TWI0_IrqHandler, /* 22 TWI 0 */
|
||||
TWI1_IrqHandler, /* 23 TWI 1 */
|
||||
SPI0_IrqHandler, /* 24 SPI 0 */
|
||||
SPI1_IrqHandler, /* 25 SPI 1 */
|
||||
SSC_IrqHandler, /* 26 SSC */
|
||||
TC0_IrqHandler, /* 27 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 28 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 29 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 30 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 31 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 32 Timer Counter 5 */
|
||||
TC6_IrqHandler, /* 33 Timer Counter 6 */
|
||||
TC7_IrqHandler, /* 34 Timer Counter 7 */
|
||||
TC8_IrqHandler, /* 35 Timer Counter 8 */
|
||||
PWM_IrqHandler, /* 36 PWM */
|
||||
ADC_IrqHandler, /* 37 ADC controller */
|
||||
DACC_IrqHandler, /* 38 DAC controller */
|
||||
DMAC_IrqHandler, /* 39 DMA Controller */
|
||||
UOTGHS_IrqHandler, /* 40 USB OTG High Speed */
|
||||
TRNG_IrqHandler, /* 41 True Random Number Generator */
|
||||
EMAC_IrqHandler, /* 42 Ethernet MAC */
|
||||
CAN0_IrqHandler, /* 43 CAN Controller 0 */
|
||||
CAN1_IrqHandler, /* 44 CAN Controller 1 */
|
||||
};
|
||||
|
||||
/* TEMPORARY PATCH FOR SCB */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
|
||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||
|
||||
/**
|
||||
* \brief This is the code that gets called on processor reset.
|
||||
* To initialize the device, and call the main() routine.
|
||||
*/
|
||||
void ResetException( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
uint32_t *pSrc, *pDest ;
|
||||
uint32_t *pSrc, *pDest;
|
||||
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext ;
|
||||
pDest = &_srelocate ;
|
||||
/* Initialize the relocate segment */
|
||||
pSrc = &_etext;
|
||||
pDest = &_srelocate;
|
||||
|
||||
if ( pSrc != pDest )
|
||||
{
|
||||
for ( ; pDest < &_erelocate ; )
|
||||
{
|
||||
*pDest++ = *pSrc++ ;
|
||||
}
|
||||
}
|
||||
if (pSrc != pDest) {
|
||||
for (; pDest < &_erelocate;) {
|
||||
*pDest++ = *pSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear the zero segment */
|
||||
for ( pDest = &_szero ; pDest < &_ezero ; )
|
||||
{
|
||||
*pDest++ = 0;
|
||||
}
|
||||
/* Clear the zero segment */
|
||||
for (pDest = &_szero; pDest < &_ezero;) {
|
||||
*pDest++ = 0;
|
||||
}
|
||||
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *)&_sfixed;
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
/* Set the vector table base address */
|
||||
pSrc = (uint32_t *) & _sfixed;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM0_ADDR) && ((uint32_t)pSrc < NFC_RAM_ADDR) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
/* Initialize the C library */
|
||||
__libc_init_array() ;
|
||||
/* Initialize the C library */
|
||||
__libc_init_array();
|
||||
|
||||
/* Branch to main function */
|
||||
main() ;
|
||||
/* Branch to main function */
|
||||
main();
|
||||
|
||||
/* Infinite loop */
|
||||
while ( 1 ) ;
|
||||
/* Infinite loop */
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,115 +12,111 @@
|
|||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "exceptions.h"
|
||||
#include "sam3xa.h"
|
||||
#include "system_sam3x.h"
|
||||
#include "../exceptions.h"
|
||||
#include "sam3.h"
|
||||
|
||||
typedef void( *intfunc )( void );
|
||||
typedef void (*intfunc) (void);
|
||||
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
|
||||
|
||||
extern void __iar_program_start( void ) ;
|
||||
extern int __low_level_init( void ) ;
|
||||
void __iar_program_start(void);
|
||||
int __low_level_init(void);
|
||||
|
||||
/* Exception Table */
|
||||
#pragma language=extended
|
||||
#pragma segment="CSTACK"
|
||||
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0. */
|
||||
/* The name "__vector_table" has special meaning for C-SPY: */
|
||||
/* it is where the SP start value is found, and the NVIC vector */
|
||||
/* table register (VTOR) is initialized to this address if != 0 */
|
||||
|
||||
#pragma section = ".intvec"
|
||||
#pragma location = ".intvec"
|
||||
const intvec_elem __vector_table[] =
|
||||
{
|
||||
{ .__ptr = __sfe( "CSTACK" ) },
|
||||
Reset_Handler,
|
||||
const intvec_elem __vector_table[] = {
|
||||
{.__ptr = __sfe("CSTACK")},
|
||||
Reset_Handler,
|
||||
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
NMI_Handler,
|
||||
HardFault_Handler,
|
||||
MemManage_Handler,
|
||||
BusFault_Handler,
|
||||
UsageFault_Handler,
|
||||
0, 0, 0, 0, /* Reserved */
|
||||
SVC_Handler,
|
||||
DebugMon_Handler,
|
||||
0, /* Reserved */
|
||||
PendSV_Handler,
|
||||
SysTick_Handler,
|
||||
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EFC 1 */
|
||||
UART_IrqHandler, /* 8 UART */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
SDRAMC_IrqHandler, /* 10 SDRAMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
PIOD_IrqHandler, /* 14 Parallel IO Controller D */
|
||||
PIOE_IrqHandler, /* 15 Parallel IO Controller E */
|
||||
PIOF_IrqHandler, /* 16 Parallel IO Controller F */
|
||||
USART0_IrqHandler, /* 17 USART 0 */
|
||||
USART1_IrqHandler, /* 18 USART 1 */
|
||||
USART2_IrqHandler, /* 19 USART 2 */
|
||||
USART3_IrqHandler, /* 20 USART 3 */
|
||||
HSMCI_IrqHandler, /* 21 MCI */
|
||||
TWI0_IrqHandler, /* 22 TWI 0 */
|
||||
TWI1_IrqHandler, /* 23 TWI 1 */
|
||||
SPI0_IrqHandler, /* 24 SPI 0 */
|
||||
SPI1_IrqHandler, /* 25 SPI 1 */
|
||||
SSC_IrqHandler, /* 26 SSC */
|
||||
TC0_IrqHandler, /* 27 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 28 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 29 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 30 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 31 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 32 Timer Counter 5 */
|
||||
TC6_IrqHandler, /* 33 Timer Counter 6 */
|
||||
TC7_IrqHandler, /* 34 Timer Counter 7 */
|
||||
TC8_IrqHandler, /* 35 Timer Counter 8 */
|
||||
PWM_IrqHandler, /* 36 PWM */
|
||||
ADC_IrqHandler, /* 37 ADC controller */
|
||||
DACC_IrqHandler, /* 38 DAC controller */
|
||||
DMAC_IrqHandler, /* 39 DMA Controller */
|
||||
UOTGHS_IrqHandler, /* 40 USB OTG High Speed */
|
||||
TRNG_IrqHandler, /* 41 True Random Number Generator */
|
||||
EMAC_IrqHandler, /* 42 Ethernet MAC */
|
||||
CAN0_IrqHandler, /* 43 CAN Controller 0 */
|
||||
CAN1_IrqHandler, /* 44 CAN Controller 1 */
|
||||
/* Configurable interrupts */
|
||||
SUPC_IrqHandler, /* 0 Supply Controller */
|
||||
RSTC_IrqHandler, /* 1 Reset Controller */
|
||||
RTC_IrqHandler, /* 2 Real Time Clock */
|
||||
RTT_IrqHandler, /* 3 Real Time Timer */
|
||||
WDT_IrqHandler, /* 4 Watchdog Timer */
|
||||
PMC_IrqHandler, /* 5 PMC */
|
||||
EFC0_IrqHandler, /* 6 EFC 0 */
|
||||
EFC1_IrqHandler, /* 7 EFC 1 */
|
||||
UART_IrqHandler, /* 8 UART */
|
||||
SMC_IrqHandler, /* 9 SMC */
|
||||
SDRAMC_IrqHandler, /* 10 SDRAMC */
|
||||
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
|
||||
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
|
||||
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
|
||||
PIOD_IrqHandler, /* 14 Parallel IO Controller D */
|
||||
PIOE_IrqHandler, /* 15 Parallel IO Controller E */
|
||||
PIOF_IrqHandler, /* 16 Parallel IO Controller F */
|
||||
USART0_IrqHandler, /* 17 USART 0 */
|
||||
USART1_IrqHandler, /* 18 USART 1 */
|
||||
USART2_IrqHandler, /* 19 USART 2 */
|
||||
USART3_IrqHandler, /* 20 USART 3 */
|
||||
HSMCI_IrqHandler, /* 21 MCI */
|
||||
TWI0_IrqHandler, /* 22 TWI 0 */
|
||||
TWI1_IrqHandler, /* 23 TWI 1 */
|
||||
SPI0_IrqHandler, /* 24 SPI 0 */
|
||||
SPI1_IrqHandler, /* 25 SPI 1 */
|
||||
SSC_IrqHandler, /* 26 SSC */
|
||||
TC0_IrqHandler, /* 27 Timer Counter 0 */
|
||||
TC1_IrqHandler, /* 28 Timer Counter 1 */
|
||||
TC2_IrqHandler, /* 29 Timer Counter 2 */
|
||||
TC3_IrqHandler, /* 30 Timer Counter 3 */
|
||||
TC4_IrqHandler, /* 31 Timer Counter 4 */
|
||||
TC5_IrqHandler, /* 32 Timer Counter 5 */
|
||||
TC6_IrqHandler, /* 33 Timer Counter 6 */
|
||||
TC7_IrqHandler, /* 34 Timer Counter 7 */
|
||||
TC8_IrqHandler, /* 35 Timer Counter 8 */
|
||||
PWM_IrqHandler, /* 36 PWM */
|
||||
ADC_IrqHandler, /* 37 ADC controller */
|
||||
DACC_IrqHandler, /* 38 DAC controller */
|
||||
DMAC_IrqHandler, /* 39 DMA Controller */
|
||||
UOTGHS_IrqHandler, /* 40 USB OTG High Speed */
|
||||
TRNG_IrqHandler, /* 41 True Random Number Generator */
|
||||
EMAC_IrqHandler, /* 42 Ethernet MAC */
|
||||
CAN0_IrqHandler, /* 43 CAN Controller 0 */
|
||||
CAN1_IrqHandler, /* 44 CAN Controller 1 */
|
||||
};
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern int __low_level_init( void )
|
||||
int __low_level_init(void)
|
||||
{
|
||||
uint32_t* pSrc = __section_begin( ".intvec" ) ;
|
||||
uint32_t *pSrc = __section_begin(".intvec");
|
||||
|
||||
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
|
||||
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
|
||||
|
||||
if ( ((uint32_t)pSrc >= IRAM0_ADDR) && ((uint32_t)pSrc < NFC_RAM_ADDR) )
|
||||
{
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
|
||||
}
|
||||
if (((uint32_t) pSrc >= IRAM0_ADDR) && ((uint32_t) pSrc < NFC_RAM_ADDR)) {
|
||||
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
|
||||
}
|
||||
|
||||
return 1 ; /* if return 0, the data sections will not be initialized. */
|
||||
return 1; /* if return 0, the data sections will not be initialized */
|
||||
}
|
||||
|
||||
/**------------------------------------------------------------------------------
|
||||
* This is the code that gets called on processor reset. To initialize the
|
||||
* device.
|
||||
*------------------------------------------------------------------------------*/
|
||||
extern void Reset_Handler( void )
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__iar_program_start();
|
||||
__iar_program_start();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
/*! \file *********************************************************************
|
||||
*
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* \brief Provides the low-level initialization functions that called
|
||||
* on chip startup.
|
||||
*
|
||||
* $asf_license$
|
||||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -27,131 +27,172 @@ extern "C" {
|
|||
/* @endcond */
|
||||
|
||||
/* Clock settings (84MHz) */
|
||||
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0x6) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3f) \
|
||||
| CKGR_PLLAR_DIVA(0x1))
|
||||
#define BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
|
||||
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
|
||||
#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
|
||||
| CKGR_PLLAR_MULA(0x6) \
|
||||
| CKGR_PLLAR_PLLACOUNT(0x3f) \
|
||||
| CKGR_PLLAR_DIVA(0x1))
|
||||
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK)
|
||||
|
||||
/* Clock Definitions */
|
||||
#define XTAL32 ( 32768UL) /* 32k crystal frequency */
|
||||
#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
|
||||
#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
|
||||
#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
|
||||
#define UTMIPLL (480000000UL) /* UTMI PLL frequency */
|
||||
#define MAINCK_XTAL_HZ (12000000UL) /* External crystal frequency */
|
||||
#define MCK_HZ (84000000UL) /* Processor frequency */
|
||||
#define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */
|
||||
#define SYS_FREQ_XTAL_XTAL12M (12000000UL) /* External 12M crystal frequency */
|
||||
#define SYS_UTMIPLL (480000000UL) /* UTMI PLL frequency */
|
||||
|
||||
#define SYS_FREQ_FWS_0 (22500000UL) /* Maximum operating frequency when FWS is 0 */
|
||||
#define SYS_FREQ_FWS_1 (34000000UL) /* Maximum operating frequency when FWS is 1 */
|
||||
#define SYS_FREQ_FWS_2 (53000000UL) /* Maximum operating frequency when FWS is 2 */
|
||||
#define SYS_FREQ_FWS_3 (78000000UL) /* Maximum operating frequency when FWS is 3 */
|
||||
|
||||
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
|
||||
|
||||
/* FIXME: should be generated by sock */
|
||||
uint32_t SystemCoreClock = EFRC_OSC;
|
||||
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
/**
|
||||
* \brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemFrequency variable.
|
||||
*/
|
||||
extern void SystemInit( void )
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
/* Set 3 FWS for Embedded Flash Access */
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
|
||||
|
||||
/* Initialize main oscillator */
|
||||
if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
|
||||
{
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
|
||||
}
|
||||
/* Initialize main oscillator */
|
||||
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
|
||||
}
|
||||
}
|
||||
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
/* Switch to 3-20MHz Xtal oscillator */
|
||||
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
|
||||
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
|
||||
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
|
||||
}
|
||||
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) |
|
||||
PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA));
|
||||
/* Initialize PLLA */
|
||||
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
|
||||
}
|
||||
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to main clock */
|
||||
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = BOARD_MCKR ;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
|
||||
/* Switch to PLLA */
|
||||
PMC->PMC_MCKR = SYS_BOARD_MCKR;
|
||||
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
|
||||
}
|
||||
|
||||
SystemCoreClock = MCK_HZ;
|
||||
SystemCoreClock = CHIP_FREQ_CPU_MAX;
|
||||
}
|
||||
|
||||
extern void SystemCoreClockUpdate( void )
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void)
|
||||
{
|
||||
/* Set FWS for Embedded Flash Access according operating frequency*/
|
||||
if(SystemCoreClock < SYS_FREQ_FWS_0){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(0);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_1){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(1);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(2);
|
||||
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(3);
|
||||
}else{
|
||||
EFC0->EEFC_FMR = EEFC_FMR_FWS(4);
|
||||
EFC1->EEFC_FMR = EEFC_FMR_FWS(4);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT
|
||||
/*Disable the watchdog */
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
#endif
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
/* Determine clock frequency according to clock register values */
|
||||
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
|
||||
SystemCoreClock = OSC32_CLK;
|
||||
else
|
||||
SystemCoreClock = ERC_OSC;
|
||||
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
|
||||
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
|
||||
SystemCoreClock = SYS_FREQ_XTAL_32K;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_SLCK_RC;
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2;
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3;
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
|
||||
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
|
||||
case PMC_MCKR_CSS_UPLL_CLK: /* UPLL clock */
|
||||
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
|
||||
SystemCoreClock = MAINCK_XTAL_HZ;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = EFRC_OSC;
|
||||
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
|
||||
} else {
|
||||
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
|
||||
|
||||
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
|
||||
case CKGR_MOR_MOSCRCF_4MHz:
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_8MHz:
|
||||
SystemCoreClock *= 2;
|
||||
SystemCoreClock *= 2U;
|
||||
break;
|
||||
case CKGR_MOR_MOSCRCF_12MHz:
|
||||
SystemCoreClock *= 3;
|
||||
SystemCoreClock *= 3U;
|
||||
break;
|
||||
case 3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FF) + 1);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FF));
|
||||
}
|
||||
else {
|
||||
SystemCoreClock = UTMIPLL/2;
|
||||
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
|
||||
CKGR_PLLAR_MULA_Pos) + 1U);
|
||||
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
|
||||
CKGR_PLLAR_DIVA_Pos));
|
||||
} else {
|
||||
SystemCoreClock = SYS_UTMIPLL / 2U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
|
||||
SystemCoreClock /= 3;
|
||||
}
|
||||
else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
SystemCoreClock /= 3U;
|
||||
} else {
|
||||
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
|
||||
PMC_MCKR_PRES_Pos);
|
||||
}
|
||||
}
|
||||
|
||||
/* @cond 0 */
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
*
|
||||
* \par Purpose
|
||||
*
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* This file provides basic support for Cortex-M processor based
|
||||
* microcontrollers.
|
||||
*
|
||||
* \author Atmel Corporation: http://www.atmel.com \n
|
||||
|
|
@ -34,13 +34,18 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
|||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
extern void SystemInit(void);
|
||||
void SystemInit(void);
|
||||
|
||||
/**
|
||||
* Initialize the flash and watchdog setting .
|
||||
*/
|
||||
void set_flash_and_watchdog(void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
/* @cond 0 */
|
||||
/**INDENT-OFF**/
|
||||
|
|
@ -51,4 +56,3 @@ extern void SystemCoreClockUpdate(void);
|
|||
/* @endcond */
|
||||
|
||||
#endif /* SYSTEM_SAM3X_H_INCLUDED */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue