mirror of https://github.com/noisymime/Arduino.git
[sam] committing state-of-the-art code: compiling under EWARM 6.21.1 but debug not easy
This commit is contained in:
Thibaut VIARD
parent
bb4c1af790
commit
8f01f92e87
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#ifndef _WIRING_MATH_
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#define _WIRING_MATH_
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extern long random( long ) ;
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extern long random( long, long ) ;
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extern void randomSeed( uint32_t dwSeed ) ;
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extern long map( long, long, long, long, long ) ;
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#endif /* _WIRING_MATH_ */
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/* ----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support
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* ----------------------------------------------------------------------------
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* Copyright (c) 2010, Atmel Corporation
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*
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* All rights reserved.
|
||||
*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Atmel's name may not be used to endorse or promote products derived from
|
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* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ----------------------------------------------------------------------------
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||||
*/
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "Arduino.h"
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/*----------------------------------------------------------------------------
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* Exported variables
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*----------------------------------------------------------------------------*/
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|
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/*----------------------------------------------------------------------------
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* Definitions
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*----------------------------------------------------------------------------*/
|
||||
|
||||
/*------------------------------------------------------------------------------
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* Types
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*------------------------------------------------------------------------------*/
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typedef union { IntFunc __fun; void * __ptr; } IntVector;
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/*------------------------------------------------------------------------------
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* ProtoTypes
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*------------------------------------------------------------------------------*/
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extern void __iar_program_start( void ) ;
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extern int __low_level_init( void ) ;
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/*------------------------------------------------------------------------------
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* Exception Table
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*------------------------------------------------------------------------------*/
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#pragma language=extended
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#pragma segment="CSTACK"
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/* The name "__vector_table" has special meaning for C-SPY: */
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/* it is where the SP start value is found, and the NVIC vector */
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/* table register (VTOR) is initialized to this address if != 0. */
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#pragma section = ".vectors"
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#pragma location = ".vectors"
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const IntVector __vector_table[] =
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{
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{ .__ptr = __sfe( "CSTACK" ) },
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__iar_program_start,
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NMI_Handler,
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HardFault_Handler,
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MemManage_Handler,
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BusFault_Handler,
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UsageFault_Handler,
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0, 0, 0, 0, /* Reserved */
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SVC_Handler,
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DebugMon_Handler,
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0, /* Reserved */
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PendSV_Handler,
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SysTick_Handler,
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#if defined sam3s4c
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/* Configurable interrupts */
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SUPC_IrqHandler, /* 0 Supply Controller */
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RSTC_IrqHandler, /* 1 Reset Controller */
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RTC_IrqHandler, /* 2 Real Time Clock */
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RTT_IrqHandler, /* 3 Real Time Timer */
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WDT_IrqHandler, /* 4 Watchdog Timer */
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PMC_IrqHandler, /* 5 PMC */
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EEFC_IrqHandler, /* 6 EEFC */
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Dummy_Handler, /* 7 Reserved */
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UART0_IrqHandler, /* 8 UART0 */
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UART1_IrqHandler, /* 9 UART1 */
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SMC_IrqHandler, /* 10 SMC */
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PIOA_IrqHandler, /* 11 Parallel IO Controller A */
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PIOB_IrqHandler, /* 12 Parallel IO Controller B */
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PIOC_IrqHandler, /* 13 Parallel IO Controller C */
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USART0_IrqHandler, /* 14 USART 0 */
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USART1_IrqHandler, /* 15 USART 1 */
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Dummy_Handler, /* 16 Reserved */
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Dummy_Handler, /* 17 Reserved */
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MCI_IrqHandler, /* 18 MCI */
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TWI0_IrqHandler, /* 19 TWI 0 */
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TWI1_IrqHandler, /* 20 TWI 1 */
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SPI_IrqHandler, /* 21 SPI */
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SSC_IrqHandler, /* 22 SSC */
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TC0_IrqHandler, /* 23 Timer Counter 0 */
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TC1_IrqHandler, /* 24 Timer Counter 1 */
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TC2_IrqHandler, /* 25 Timer Counter 2 */
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TC3_IrqHandler, /* 26 Timer Counter 3 */
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TC4_IrqHandler, /* 27 Timer Counter 4 */
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TC5_IrqHandler, /* 28 Timer Counter 5 */
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ADC_IrqHandler, /* 29 ADC controller */
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DAC_IrqHandler, /* 30 DAC controller */
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PWM_IrqHandler, /* 31 PWM */
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CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
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ACC_IrqHandler, /* 33 Analog Comparator */
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USBD_IrqHandler, /* 34 USB Device Port */
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Dummy_Handler /* 35 not used */
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#endif /* defined sam3s4c */
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|
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#if defined sam3u4e
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#endif /* defined sam3u4e */
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};
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|
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/**------------------------------------------------------------------------------
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* This is the code that gets called on processor reset. To initialize the
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* device.
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*------------------------------------------------------------------------------*/
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extern int __low_level_init( void )
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{
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uint32_t* pSrc = (uint32_t*)__section_begin( ".vectors" ) ;
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/* Low level Initialize */
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LowLevelInit() ;
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SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
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if ( ((uint32_t)pSrc >= IRAM0_ADDR) && ((uint32_t)pSrc < NFC_RAM_ADDR) )
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{
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SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
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}
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return 1 ; /* if return 0, the data sections will not be initialized. */
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}
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Load Diff
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Load Diff
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/**
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* \file
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*
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* Implementation of low level library.
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*
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*/
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#if defined __ICCARM__ /* IAR Ewarm 5.41+ */
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#include "board.h"
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#include <stdio.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <yfuns.h>
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#include <uart.h>
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extern __weak size_t __write( int handle, const unsigned char *buf, size_t bufSize )
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{
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size_t nChars = 0 ;
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/* Check for the command to flush all handles */
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if ( handle == -1 )
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{
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return 0 ;
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}
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/* Check for stdout and stderr (only necessary if FILE descriptors are enabled.) */
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if ( handle != 1 && handle != 2 )
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{
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/* remove warnings */
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return 0xfffffff ;
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}
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for ( /* Empty */ ; bufSize > 0 ; --bufSize )
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{
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while ( !uart_is_tx_ready(CONSOLE_UART) )
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;
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uart_write( CONSOLE_UART, *buf ) ;
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++buf ;
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++nChars ;
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}
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return nChars ;
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}
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extern __weak size_t __read( int handle, unsigned char *buf, size_t bufSize )
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{
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size_t nChars = 0 ;
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/* Check for stdin (only necessary if FILE descriptors are enabled) */
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if ( handle != 0 )
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{
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/* remove warnings */
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return 0xfffffff ;
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}
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for ( /*Empty*/; bufSize > 0 ; --bufSize )
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{
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uint8_t c;
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while (uart_read( CONSOLE_UART, &c ))
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;
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if ( c == 0 )
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{
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break ;
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}
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*buf++ = c ;
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++nChars ;
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}
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return nChars ;
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}
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/**
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* \brief Outputs a character on the UART.
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*
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* \param c Character to output.
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*
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* \return The character that was output.
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*/
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extern __weak signed int putchar( signed int c )
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{
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while ( !uart_is_tx_ready(CONSOLE_UART) )
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;
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uart_write( CONSOLE_UART, c ) ;
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return c ;
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}
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#endif // defined __ICCARM__
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#ifndef _WIRING_
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#define _WIRING_
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|
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#ifdef __cplusplus
|
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extern "C" {
|
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#endif
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extern void init( void ) ;
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extern uint32_t millis( void ) ;
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extern uint32_t micros( void ) ;
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extern void delay( uint32_t dwMs ) ;
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extern void delayMicroseconds( uint32_t dwUs ) ;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _WIRING_ */
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#ifndef _WIRING_ANALOG_
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#define _WIRING_ANALOG_
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#ifdef __cplusplus
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||||
extern "C" {
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||||
#endif
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||||
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||||
/*
|
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* \brief
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*/
|
||||
extern void analogReference( uint8_t mode ) ;
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||||
/*
|
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* \brief
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*/
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extern void analogWrite( uint8_t, int ) ;
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/*
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* \brief
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*/
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extern int analogRead( uint8_t ) ;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _WIRING_ANALOG_ */
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#ifndef _WIRING_DIGITAL_
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#define _WIRING_DIGITAL_
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#ifdef __cplusplus
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extern "C" {
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#endif
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|
||||
/*
|
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* \brief Configures the specified pin to behave either as an input or an output. See the description of digital pins for details.
|
||||
*
|
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* \param dwPin the number of the pin whose mode you wish to set
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* \param dwMode either INPUT or OUTPUT
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*/
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extern void pinMode( uint32_t dwPin, uint32_t dwMode ) ;
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|
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/*
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* \brief Write a HIGH or a LOW value to a digital pin.
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*
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* \desc If the pin has been configured as an OUTPUT with pinMode(), its voltage will be set to the
|
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* corresponding value: 5V (or 3.3V on 3.3V boards) for HIGH, 0V (ground) for LOW.
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*
|
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* If the pin is configured as an INPUT, writing a HIGH value with digitalWrite() will enable an internal
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* 20K pullup resistor (see the tutorial on digital pins). Writing LOW will disable the pullup. The pullup
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* resistor is enough to light an LED dimly, so if LEDs appear to work, but very dimly, this is a likely
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* cause. The remedy is to set the pin to an output with the pinMode() function.
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*
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* \note Digital pin PIN_LED is harder to use as a digital input than the other digital pins because it has an LED
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* and resistor attached to it that's soldered to the board on most boards. If you enable its internal 20k pull-up
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* resistor, it will hang at around 1.7 V instead of the expected 5V because the onboard LED and series resistor
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* pull the voltage level down, meaning it always returns LOW. If you must use pin PIN_LED as a digital input, use an
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* external pull down resistor.
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*
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* \param dwPin the pin number
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* \param dwVal HIGH or LOW
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*/
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extern void digitalWrite( uint32_t dwPin, uint32_t dwVal ) ;
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/*
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* \brief Reads the value from a specified digital pin, either HIGH or LOW.
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||||
*
|
||||
* \param dwPin the number of the digital pin you want to read (int)
|
||||
*/
|
||||
extern int digitalRead( uint32_t dwPin ) ;
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||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
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||||
|
||||
#endif /* _WIRING_DIGITAL_ */
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#ifndef _WIRING_PULSE_
|
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#define _WIRING_PULSE_
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|
||||
#ifdef __cplusplus
|
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extern "C" {
|
||||
#endif
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||||
|
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/*
|
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* \brief Measures the length (in microseconds) of a pulse on the pin; state is HIGH
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* or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds
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* to 3 minutes in length, but must be called at least a few dozen microseconds
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||||
* before the start of the pulse.
|
||||
*/
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||||
extern uint32_t pulseIn( uint32_t ulPin, uint32_t ulState, uint32_t ulTimeout = 1000000L ) ;
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||||
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||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WIRING_PULSE_ */
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||||
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#ifndef _WIRING_SHIFT_
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||||
#define _WIRING_SHIFT_
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||||
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||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* \brief
|
||||
*/
|
||||
extern uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder ) ;
|
||||
|
||||
|
||||
/*
|
||||
* \brief
|
||||
*/
|
||||
extern void shiftOut( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder, uint32_t ulVal ) ;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _WIRING_SHIFT_ */
|
||||
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|||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\..\..\..\cores\sam\build_iar\libarduino.ewp</path>
|
||||
</project>
|
||||
<project>
|
||||
<path>$WS_DIR$\libsam.ewp</path>
|
||||
</project>
|
||||
<project>
|
||||
<path>$WS_DIR$\..\..\..\cores\sam\validation\build_iar\test.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
/*****************************************************************************
|
||||
* @file ReadMe.txt
|
||||
* @purpose Explanation how to use the Device folder and template files
|
||||
* @version V2.10
|
||||
* @date 25. July 2011
|
||||
*****************************************************************************/
|
||||
|
||||
Following directory structure and template files are given:
|
||||
|
||||
- <Vendor>
|
||||
|
|
||||
+-- <Device>
|
||||
|
|
||||
+-- Include
|
||||
| +- <Device>.h header file
|
||||
| +- system_Device.h system include file
|
||||
+-- Source
|
||||
|
|
||||
+ Templates
|
||||
+- system_<Device>.c system source file
|
||||
|
|
||||
+-- ARM
|
||||
| +- startup_<Device>.s startup file for ARMCC
|
||||
|
|
||||
+-- GCC
|
||||
|
|
||||
+-- IAR
|
||||
|
||||
|
||||
Copy the complete folder including files and replace:
|
||||
- folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.
|
||||
- folder name 'Device' with your specific device name e.g.: LPC17xx.
|
||||
- in the filenames 'Device' with your specific device name e.g.: LPC17xx.
|
||||
|
||||
|
||||
The template files contain comments starting with 'ToDo: '
|
||||
There it is described what you need to do.
|
||||
|
||||
|
||||
The template files contain following placeholder:
|
||||
|
||||
<Device>
|
||||
<Device> should be replaced with your specific device name.
|
||||
e.g.: LPC17xx
|
||||
|
||||
<DeviceInterrupt>
|
||||
<DeviceInterrupt> should be replaced with a specific device interrupt name.
|
||||
e.g.: TIM1 for Timer#1 interrupt.
|
||||
|
||||
<DeviceAbbreviation>
|
||||
<DeviceAbbreviation> should be replaced with a dedicated device family
|
||||
abbreviation (e.g.: LPC for LPC17xx device family)
|
||||
|
||||
Cortex-M#
|
||||
Cortex-M# can be replaced with the specific Cortex-M number
|
||||
e.g.: Cortex-M3
|
||||
|
||||
|
||||
|
||||
Note:
|
||||
Template files (i.e. startup_Device.s, system_Device.c) are application
|
||||
specific and therefore expected to be copied into the application project
|
||||
folder prior to use!
|
||||
|
||||
|
|
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|
|||
#include <stdlib.h>
|
||||
#include <compiler.h>
|
||||
#include <board.h>
|
||||
#include "conf_board.h"
|
||||
|
||||
volatile uint32_t msTicks = 0; /* counts 1ms timeTicks */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
SysTick_Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
msTicks++; /* increment counter necessary in Delay() */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
delays number of tick Systicks (happens every 1 ms)
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void Delay(uint32_t dlyTicks)
|
||||
{
|
||||
uint32_t curTicks;
|
||||
|
||||
curTicks = msTicks;
|
||||
while ((msTicks - curTicks) < dlyTicks);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
configer LED pins
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_Config(void)
|
||||
{
|
||||
LED0_PIO->PIO_PER = LED0_MASK; /* Setup Pin PA19 for LED */
|
||||
LED0_PIO->PIO_OER = LED0_MASK;
|
||||
LED0_PIO->PIO_PUDR = LED0_MASK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Switch on LEDs
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_On(uint32_t led)
|
||||
{
|
||||
LED0_PIO->PIO_CODR = led; /* Turn On LED */
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Switch off LEDs
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_Off(uint32_t led)
|
||||
{
|
||||
LED0_PIO->PIO_SODR = led; /* Turn Off LED */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
MAIN function
|
||||
*----------------------------------------------------------------------------*/
|
||||
int main(void)
|
||||
{
|
||||
SystemInit();
|
||||
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
|
||||
if (SysTick_Config(SystemCoreClock / 1000)) { /* Setup SysTick Timer for 1 msec interrupts */
|
||||
while (1); /* Capture error */
|
||||
}
|
||||
|
||||
LED_Config();
|
||||
|
||||
while(1) {
|
||||
LED_On (LED0_MASK); /* Turn on the LED. */
|
||||
Delay (1000); /* delay 100 Msec */
|
||||
LED_Off (LED0_MASK); /* Turn off the LED. */
|
||||
Delay (1000); /* delay 100 Msec */
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Board configuration for clock example 1
|
||||
*
|
||||
* Copyright (C) 2010 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel AVR product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
*/
|
||||
#ifndef CONF_BOARD_H_INCLUDED
|
||||
#define CONF_BOARD_H_INCLUDED
|
||||
|
||||
#define LED0_PIO PIOA
|
||||
#define LED0_MASK (0x01 << 23)
|
||||
|
||||
#endif /* CONF_BOARD_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Board configuration for clock example 1
|
||||
*
|
||||
* Copyright (C) 2010 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel AVR product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
*/
|
||||
#ifndef CONF_BOARD_H_INCLUDED
|
||||
#define CONF_BOARD_H_INCLUDED
|
||||
|
||||
#define LED0_PIO PIOA
|
||||
#define LED0_MASK (0x01 << 19)
|
||||
|
||||
#endif /* CONF_BOARD_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Board configuration for clock example 1
|
||||
*
|
||||
* Copyright (C) 2010 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel AVR product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
*/
|
||||
#ifndef CONF_BOARD_H_INCLUDED
|
||||
#define CONF_BOARD_H_INCLUDED
|
||||
|
||||
#define LED0_PIO PIOA
|
||||
#define LED0_MASK (0x01 << 19)
|
||||
|
||||
#endif /* CONF_BOARD_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Board configuration for clock example 1
|
||||
*
|
||||
* Copyright (C) 2010 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel AVR product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
*/
|
||||
#ifndef CONF_BOARD_H_INCLUDED
|
||||
#define CONF_BOARD_H_INCLUDED
|
||||
|
||||
#define LED0_PIO PIOB
|
||||
#define LED0_MASK (0x01 << 0)
|
||||
|
||||
#endif /* CONF_BOARD_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Board configuration for clock example 1
|
||||
*
|
||||
* Copyright (C) 2010 Atmel Corporation. All rights reserved.
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. The name of Atmel may not be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* 4. This software may only be redistributed and used in connection with an
|
||||
* Atmel AVR product.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
|
||||
* DAMAGE.
|
||||
*/
|
||||
#ifndef CONF_BOARD_H_INCLUDED
|
||||
#define CONF_BOARD_H_INCLUDED
|
||||
|
||||
#define LED0_PIO PIOB
|
||||
#define LED0_MASK (0x01 << 12)
|
||||
|
||||
#endif /* CONF_BOARD_H_INCLUDED */
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_ADC_COMPONENT_
|
||||
#define _SAM3N_ADC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_ADC Analog-to-digital Converter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Adc hardware registers */
|
||||
typedef struct {
|
||||
WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */
|
||||
RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */
|
||||
RwReg ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */
|
||||
RwReg ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */
|
||||
WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */
|
||||
WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */
|
||||
RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */
|
||||
RoReg Reserved1[1];
|
||||
RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
|
||||
WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
|
||||
WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
|
||||
RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
|
||||
RoReg ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */
|
||||
RoReg Reserved2[2];
|
||||
RoReg ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */
|
||||
RwReg ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */
|
||||
RwReg ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */
|
||||
RoReg Reserved3[2];
|
||||
RoReg ADC_CDR[16]; /**< \brief (Adc Offset: 0x50) Channel Data Register */
|
||||
RoReg Reserved4[12];
|
||||
RwReg ADC_TRGR; /**< \brief (Adc Offset: 0xC0) Trigger Register */
|
||||
RoReg Reserved5[8];
|
||||
RwReg ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */
|
||||
RoReg ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */
|
||||
RoReg Reserved6[5];
|
||||
RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
|
||||
RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */
|
||||
RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */
|
||||
RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */
|
||||
} Adc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
|
||||
#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
|
||||
#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
|
||||
/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */
|
||||
#define ADC_SEQR1_USCH1_Pos 0
|
||||
#define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */
|
||||
#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos)))
|
||||
#define ADC_SEQR1_USCH2_Pos 4
|
||||
#define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */
|
||||
#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos)))
|
||||
#define ADC_SEQR1_USCH3_Pos 8
|
||||
#define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */
|
||||
#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos)))
|
||||
#define ADC_SEQR1_USCH4_Pos 12
|
||||
#define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */
|
||||
#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos)))
|
||||
#define ADC_SEQR1_USCH5_Pos 16
|
||||
#define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */
|
||||
#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos)))
|
||||
#define ADC_SEQR1_USCH6_Pos 20
|
||||
#define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */
|
||||
#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos)))
|
||||
#define ADC_SEQR1_USCH7_Pos 24
|
||||
#define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */
|
||||
#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos)))
|
||||
#define ADC_SEQR1_USCH8_Pos 28
|
||||
#define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */
|
||||
#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos)))
|
||||
/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */
|
||||
#define ADC_SEQR2_USCH9_Pos 0
|
||||
#define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */
|
||||
#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos)))
|
||||
#define ADC_SEQR2_USCH10_Pos 4
|
||||
#define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */
|
||||
#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos)))
|
||||
#define ADC_SEQR2_USCH11_Pos 8
|
||||
#define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */
|
||||
#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos)))
|
||||
#define ADC_SEQR2_USCH12_Pos 12
|
||||
#define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */
|
||||
#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos)))
|
||||
#define ADC_SEQR2_USCH13_Pos 16
|
||||
#define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */
|
||||
#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos)))
|
||||
#define ADC_SEQR2_USCH14_Pos 20
|
||||
#define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */
|
||||
#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos)))
|
||||
#define ADC_SEQR2_USCH15_Pos 24
|
||||
#define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */
|
||||
#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos)))
|
||||
#define ADC_SEQR2_USCH16_Pos 28
|
||||
#define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */
|
||||
#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos)))
|
||||
/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
|
||||
#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
|
||||
#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
|
||||
#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
|
||||
#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
|
||||
#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
|
||||
#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
|
||||
#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
|
||||
#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
|
||||
#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */
|
||||
#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */
|
||||
#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */
|
||||
#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */
|
||||
#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */
|
||||
#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */
|
||||
#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */
|
||||
#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */
|
||||
/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
|
||||
#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
|
||||
#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
|
||||
#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
|
||||
#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
|
||||
#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
|
||||
#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
|
||||
#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
|
||||
#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
|
||||
#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */
|
||||
#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */
|
||||
#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */
|
||||
#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */
|
||||
#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */
|
||||
#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */
|
||||
#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */
|
||||
#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */
|
||||
/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
|
||||
#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
|
||||
#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
|
||||
#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
|
||||
#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
|
||||
#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
|
||||
#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
|
||||
#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
|
||||
#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
|
||||
#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */
|
||||
#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */
|
||||
#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */
|
||||
#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */
|
||||
#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */
|
||||
#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */
|
||||
#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */
|
||||
#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */
|
||||
/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
|
||||
#define ADC_LCDR_LDATA_Pos 0
|
||||
#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
|
||||
#define ADC_LCDR_CHNB_Pos 12
|
||||
#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */
|
||||
/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
|
||||
#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
|
||||
#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
|
||||
#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
|
||||
#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
|
||||
#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
|
||||
#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
|
||||
#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
|
||||
#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
|
||||
#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */
|
||||
#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */
|
||||
#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */
|
||||
#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */
|
||||
#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */
|
||||
#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */
|
||||
#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */
|
||||
#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */
|
||||
#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
|
||||
#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
|
||||
#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */
|
||||
#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
|
||||
#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
|
||||
/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
|
||||
#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
|
||||
#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
|
||||
#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
|
||||
#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
|
||||
#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
|
||||
#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
|
||||
#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
|
||||
#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
|
||||
#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */
|
||||
#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */
|
||||
#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */
|
||||
#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */
|
||||
#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */
|
||||
#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */
|
||||
#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */
|
||||
#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */
|
||||
#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
|
||||
#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
|
||||
#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */
|
||||
#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
|
||||
#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
|
||||
/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
|
||||
#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
|
||||
#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
|
||||
#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
|
||||
#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
|
||||
#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
|
||||
#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
|
||||
#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
|
||||
#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
|
||||
#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */
|
||||
#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */
|
||||
#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */
|
||||
#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */
|
||||
#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */
|
||||
#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */
|
||||
#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */
|
||||
#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */
|
||||
#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
|
||||
#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
|
||||
#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */
|
||||
#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
|
||||
#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
|
||||
/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */
|
||||
#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */
|
||||
#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */
|
||||
#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */
|
||||
#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */
|
||||
#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */
|
||||
#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */
|
||||
#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */
|
||||
#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */
|
||||
#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */
|
||||
#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */
|
||||
#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */
|
||||
#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */
|
||||
#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */
|
||||
#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */
|
||||
#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */
|
||||
#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */
|
||||
#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */
|
||||
#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */
|
||||
#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */
|
||||
#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */
|
||||
#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */
|
||||
/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */
|
||||
#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */
|
||||
#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */
|
||||
#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */
|
||||
#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */
|
||||
#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */
|
||||
#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */
|
||||
#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */
|
||||
#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */
|
||||
#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */
|
||||
#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */
|
||||
#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */
|
||||
#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */
|
||||
#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */
|
||||
#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */
|
||||
#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */
|
||||
#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */
|
||||
/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */
|
||||
#define ADC_EMR_CMPMODE_Pos 0
|
||||
#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */
|
||||
#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
|
||||
#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
|
||||
#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */
|
||||
#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */
|
||||
#define ADC_EMR_CMPSEL_Pos 4
|
||||
#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */
|
||||
#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos)))
|
||||
#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */
|
||||
#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */
|
||||
/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */
|
||||
#define ADC_CWR_LOWTHRES_Pos 0
|
||||
#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */
|
||||
#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos)))
|
||||
#define ADC_CWR_HIGHTHRES_Pos 16
|
||||
#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */
|
||||
#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos)))
|
||||
/* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */
|
||||
#define ADC_CDR_DATA_Pos 0
|
||||
#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[16]) Converted Data */
|
||||
/* -------- ADC_TRGR : (ADC Offset: 0xC0) Trigger Register -------- */
|
||||
#define ADC_TRGR_TRGMOD_Pos 0
|
||||
#define ADC_TRGR_TRGMOD_Msk (0x7u << ADC_TRGR_TRGMOD_Pos) /**< \brief (ADC_TRGR) Trigger Mode */
|
||||
#define ADC_TRGR_TRGMOD_NO_TRIGGER (0x0u << 0) /**< \brief (ADC_TRGR) No trigger, only software trigger can start conversions */
|
||||
#define ADC_TRGR_TRGMOD_EXT_TRIG_RISE (0x1u << 0) /**< \brief (ADC_TRGR) External Trigger Rising Edge */
|
||||
#define ADC_TRGR_TRGMOD_EXT_TRIG_FALL (0x2u << 0) /**< \brief (ADC_TRGR) External Trigger Falling Edge */
|
||||
#define ADC_TRGR_TRGMOD_EXT_TRIG_ANY (0x3u << 0) /**< \brief (ADC_TRGR) External Trigger Any Edge */
|
||||
#define ADC_TRGR_TRGMOD_PERIOD_TRIG (0x5u << 0) /**< \brief (ADC_TRGR) Periodic Trigger (TRGPER shall be initiated appropriately) */
|
||||
#define ADC_TRGR_TRGMOD_CONTINUOUS (0x6u << 0) /**< \brief (ADC_TRGR) Continuous Mode */
|
||||
#define ADC_TRGR_TRGPER_Pos 16
|
||||
#define ADC_TRGR_TRGPER_Msk (0xffffu << ADC_TRGR_TRGPER_Pos) /**< \brief (ADC_TRGR) Trigger Period */
|
||||
#define ADC_TRGR_TRGPER(value) ((ADC_TRGR_TRGPER_Msk & ((value) << ADC_TRGR_TRGPER_Pos)))
|
||||
/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */
|
||||
#define ADC_WPMR_WPKEY_Pos 8
|
||||
#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */
|
||||
#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos)))
|
||||
/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */
|
||||
#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */
|
||||
#define ADC_WPSR_WPVSRC_Pos 8
|
||||
#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */
|
||||
/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define ADC_RPR_RXPTR_Pos 0
|
||||
#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
|
||||
#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
|
||||
/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
|
||||
#define ADC_RCR_RXCTR_Pos 0
|
||||
#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
|
||||
#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
|
||||
/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define ADC_TPR_TXPTR_Pos 0
|
||||
#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
|
||||
#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
|
||||
/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define ADC_TCR_TXCTR_Pos 0
|
||||
#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
|
||||
#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
|
||||
/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define ADC_RNPR_RXNPTR_Pos 0
|
||||
#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
|
||||
#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
|
||||
/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define ADC_RNCR_RXNCTR_Pos 0
|
||||
#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
|
||||
#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
|
||||
/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define ADC_TNPR_TXNPTR_Pos 0
|
||||
#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
|
||||
#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
|
||||
/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define ADC_TNCR_TXNCTR_Pos 0
|
||||
#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
|
||||
#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
|
||||
/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
|
||||
#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
|
||||
#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
|
||||
#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
|
||||
#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
|
||||
#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
|
||||
#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_ADC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_CHIPID_COMPONENT_
|
||||
#define _SAM3N_CHIPID_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Chip Identifier */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_CHIPID Chip Identifier */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Chipid hardware registers */
|
||||
typedef struct {
|
||||
RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
|
||||
RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
|
||||
} Chipid;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
|
||||
#define CHIPID_CIDR_VERSION_Pos 0
|
||||
#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
|
||||
#define CHIPID_CIDR_EPROC_Pos 5
|
||||
#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
|
||||
#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
|
||||
#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
|
||||
#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
|
||||
#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
|
||||
#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
|
||||
#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
|
||||
#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
|
||||
#define CHIPID_CIDR_NVPSIZ_Pos 8
|
||||
#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
|
||||
#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
|
||||
#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_Pos 12
|
||||
#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
|
||||
#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
|
||||
#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_Pos 16
|
||||
#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
|
||||
#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
|
||||
#define CHIPID_CIDR_ARCH_Pos 20
|
||||
#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
|
||||
#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
|
||||
#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
|
||||
#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
|
||||
#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
|
||||
#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
|
||||
#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
|
||||
#define CHIPID_CIDR_NVPTYP_Pos 28
|
||||
#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
|
||||
#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
|
||||
#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */
|
||||
#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
|
||||
#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
|
||||
/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
|
||||
#define CHIPID_EXID_EXID_Pos 0
|
||||
#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_CHIPID_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_DACC_COMPONENT_
|
||||
#define _SAM3N_DACC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_DACC Digital-to-Analog Converter Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Dacc hardware registers */
|
||||
typedef struct {
|
||||
WoReg DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */
|
||||
RwReg DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */
|
||||
WoReg DACC_CDR; /**< \brief (Dacc Offset: 0x08) Conversion Data Register */
|
||||
WoReg DACC_IER; /**< \brief (Dacc Offset: 0x0C) Interrupt Enable Register */
|
||||
WoReg DACC_IDR; /**< \brief (Dacc Offset: 0x10) Interrupt Disable Register */
|
||||
RoReg DACC_IMR; /**< \brief (Dacc Offset: 0x14) Interrupt Mask Register */
|
||||
RoReg DACC_ISR; /**< \brief (Dacc Offset: 0x18) Interrupt Status Register */
|
||||
RoReg Reserved1[50];
|
||||
RwReg DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode Register */
|
||||
RoReg DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status Register */
|
||||
RoReg Reserved2[5];
|
||||
RwReg DACC_RPR; /**< \brief (Dacc Offset: 0x100) Receive Pointer Register */
|
||||
RwReg DACC_RCR; /**< \brief (Dacc Offset: 0x104) Receive Counter Register */
|
||||
RwReg DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg DACC_RNPR; /**< \brief (Dacc Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg DACC_RNCR; /**< \brief (Dacc Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */
|
||||
RoReg DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */
|
||||
} Dacc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */
|
||||
#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */
|
||||
/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */
|
||||
#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */
|
||||
#define DACC_MR_TRGSEL_Pos 1
|
||||
#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */
|
||||
#define DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /**< \brief (DACC_MR) External trigger */
|
||||
#define DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 0 */
|
||||
#define DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 1 */
|
||||
#define DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 2 */
|
||||
#define DACC_MR_DACEN (0x1u << 4) /**< \brief (DACC_MR) DAC enable */
|
||||
#define DACC_MR_WORD (0x1u << 5) /**< \brief (DACC_MR) Word Transfer */
|
||||
#define DACC_MR_STARTUP_Pos 8
|
||||
#define DACC_MR_STARTUP_Msk (0xffu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */
|
||||
#define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos)))
|
||||
#define DACC_MR_CLKDIV_Pos 16
|
||||
#define DACC_MR_CLKDIV_Msk (0xffffu << DACC_MR_CLKDIV_Pos) /**< \brief (DACC_MR) DAC Clock Divider for Internal Trigger */
|
||||
#define DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos)))
|
||||
/* -------- DACC_CDR : (DACC Offset: 0x08) Conversion Data Register -------- */
|
||||
#define DACC_CDR_DATA_Pos 0
|
||||
#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */
|
||||
#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos)))
|
||||
/* -------- DACC_IER : (DACC Offset: 0x0C) Interrupt Enable Register -------- */
|
||||
#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmission Ready Interrupt Enable */
|
||||
#define DACC_IER_ENDTX (0x1u << 1) /**< \brief (DACC_IER) End of PDC Interrupt Enable */
|
||||
#define DACC_IER_TXBUFE (0x1u << 2) /**< \brief (DACC_IER) Buffer Empty Interrupt Enable */
|
||||
/* -------- DACC_IDR : (DACC Offset: 0x10) Interrupt Disable Register -------- */
|
||||
#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmission Ready Interrupt Disable */
|
||||
#define DACC_IDR_ENDTX (0x1u << 1) /**< \brief (DACC_IDR) End of PDC Interrupt Disable */
|
||||
#define DACC_IDR_TXBUFE (0x1u << 2) /**< \brief (DACC_IDR) Buffer Empty Interrupt Disable */
|
||||
/* -------- DACC_IMR : (DACC Offset: 0x14) Interrupt Mask Register -------- */
|
||||
#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmission Ready Interrupt Mask */
|
||||
#define DACC_IMR_ENDTX (0x1u << 1) /**< \brief (DACC_IMR) End of PDC Interrupt Mask */
|
||||
#define DACC_IMR_TXBUFE (0x1u << 2) /**< \brief (DACC_IMR) Buffer Empty Interrupt Mask */
|
||||
/* -------- DACC_ISR : (DACC Offset: 0x18) Interrupt Status Register -------- */
|
||||
#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmission Ready Interrupt Flag */
|
||||
#define DACC_ISR_ENDTX (0x1u << 1) /**< \brief (DACC_ISR) End of PDC Interrupt Flag */
|
||||
#define DACC_ISR_TXBUFE (0x1u << 2) /**< \brief (DACC_ISR) Buffer Empty Interrupt Flag */
|
||||
/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */
|
||||
#define DACC_WPMR_WPKEY_Pos 8
|
||||
#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */
|
||||
#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos)))
|
||||
/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status Register -------- */
|
||||
#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */
|
||||
#define DACC_WPSR_WPROTADDR_Pos 8
|
||||
#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */
|
||||
/* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define DACC_RPR_RXPTR_Pos 0
|
||||
#define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /**< \brief (DACC_RPR) Receive Pointer Register */
|
||||
#define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos)))
|
||||
/* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */
|
||||
#define DACC_RCR_RXCTR_Pos 0
|
||||
#define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /**< \brief (DACC_RCR) Receive Counter Register */
|
||||
#define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos)))
|
||||
/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define DACC_TPR_TXPTR_Pos 0
|
||||
#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */
|
||||
#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos)))
|
||||
/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define DACC_TCR_TXCTR_Pos 0
|
||||
#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */
|
||||
#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos)))
|
||||
/* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define DACC_RNPR_RXNPTR_Pos 0
|
||||
#define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /**< \brief (DACC_RNPR) Receive Next Pointer */
|
||||
#define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos)))
|
||||
/* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define DACC_RNCR_RXNCTR_Pos 0
|
||||
#define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /**< \brief (DACC_RNCR) Receive Next Counter */
|
||||
#define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos)))
|
||||
/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define DACC_TNPR_TXNPTR_Pos 0
|
||||
#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */
|
||||
#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos)))
|
||||
/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define DACC_TNCR_TXNCTR_Pos 0
|
||||
#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */
|
||||
#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos)))
|
||||
/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */
|
||||
#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */
|
||||
#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */
|
||||
#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */
|
||||
#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */
|
||||
#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */
|
||||
#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_DACC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_EFC_COMPONENT_
|
||||
#define _SAM3N_EFC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_EFC Embedded Flash Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Efc hardware registers */
|
||||
typedef struct {
|
||||
RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
|
||||
WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
|
||||
RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
|
||||
RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
|
||||
} Efc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
|
||||
#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
|
||||
#define EEFC_FMR_FWS_Pos 8
|
||||
#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
|
||||
#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
|
||||
#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
|
||||
#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
|
||||
/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
|
||||
#define EEFC_FCR_FCMD_Pos 0
|
||||
#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
|
||||
#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
|
||||
#define EEFC_FCR_FARG_Pos 8
|
||||
#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
|
||||
#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
|
||||
#define EEFC_FCR_FKEY_Pos 24
|
||||
#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
|
||||
#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
|
||||
/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
|
||||
#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
|
||||
#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
|
||||
#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
|
||||
/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
|
||||
#define EEFC_FRR_FVALUE_Pos 0
|
||||
#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_EFC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_GPBR_COMPONENT_
|
||||
#define _SAM3N_GPBR_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_GPBR General Purpose Backup Register */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Gpbr hardware registers */
|
||||
typedef struct {
|
||||
RwReg SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
|
||||
} Gpbr;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
|
||||
#define SYS_GPBR_GPBR_VALUE_Pos 0
|
||||
#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */
|
||||
#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_GPBR_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_MATRIX_COMPONENT_
|
||||
#define _SAM3N_MATRIX_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_MATRIX AHB Bus Matrix */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Matrix hardware registers */
|
||||
typedef struct {
|
||||
RwReg MATRIX_MCFG[3]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
|
||||
RoReg Reserved1[13];
|
||||
RwReg MATRIX_SCFG[4]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
|
||||
RoReg Reserved2[12];
|
||||
RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
|
||||
RoReg Reserved3[1];
|
||||
RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
|
||||
RoReg Reserved4[1];
|
||||
RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
|
||||
RoReg Reserved5[1];
|
||||
RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
|
||||
RoReg Reserved6[1];
|
||||
RoReg Reserved7[29];
|
||||
RwReg CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */
|
||||
RoReg Reserved8[51];
|
||||
RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
|
||||
RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
|
||||
} Matrix;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- MATRIX_MCFG[3] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
|
||||
#define MATRIX_MCFG_ULBT_Pos 0
|
||||
#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[3]) Undefined Length Burst Type */
|
||||
#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
|
||||
/* -------- MATRIX_SCFG[4] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
|
||||
#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[4]) Default Master Type */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[4]) Fixed Default Master */
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
|
||||
#define MATRIX_SCFG_ARBT_Pos 24
|
||||
#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[4]) Arbitration Type */
|
||||
#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
|
||||
/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
|
||||
#define MATRIX_PRAS0_M0PR_Pos 0
|
||||
#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
|
||||
#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
|
||||
#define MATRIX_PRAS0_M1PR_Pos 4
|
||||
#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
|
||||
#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
|
||||
#define MATRIX_PRAS0_M2PR_Pos 8
|
||||
#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
|
||||
#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
|
||||
#define MATRIX_PRAS0_M3PR_Pos 12
|
||||
#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
|
||||
#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
|
||||
/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
|
||||
#define MATRIX_PRAS1_M0PR_Pos 0
|
||||
#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
|
||||
#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
|
||||
#define MATRIX_PRAS1_M1PR_Pos 4
|
||||
#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
|
||||
#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
|
||||
#define MATRIX_PRAS1_M2PR_Pos 8
|
||||
#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
|
||||
#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
|
||||
#define MATRIX_PRAS1_M3PR_Pos 12
|
||||
#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
|
||||
#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
|
||||
/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
|
||||
#define MATRIX_PRAS2_M0PR_Pos 0
|
||||
#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
|
||||
#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
|
||||
#define MATRIX_PRAS2_M1PR_Pos 4
|
||||
#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
|
||||
#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
|
||||
#define MATRIX_PRAS2_M2PR_Pos 8
|
||||
#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
|
||||
#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
|
||||
#define MATRIX_PRAS2_M3PR_Pos 12
|
||||
#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
|
||||
#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
|
||||
/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
|
||||
#define MATRIX_PRAS3_M0PR_Pos 0
|
||||
#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
|
||||
#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
|
||||
#define MATRIX_PRAS3_M1PR_Pos 4
|
||||
#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
|
||||
#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
|
||||
#define MATRIX_PRAS3_M2PR_Pos 8
|
||||
#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
|
||||
#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
|
||||
#define MATRIX_PRAS3_M3PR_Pos 12
|
||||
#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
|
||||
#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
|
||||
/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */
|
||||
#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */
|
||||
#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */
|
||||
#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */
|
||||
#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */
|
||||
#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */
|
||||
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
|
||||
#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
|
||||
#define MATRIX_WPMR_WPKEY_Pos 8
|
||||
#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
|
||||
#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
|
||||
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
|
||||
#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
|
||||
#define MATRIX_WPSR_WPVSRC_Pos 8
|
||||
#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_MATRIX_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PDC_COMPONENT_
|
||||
#define _SAM3N_PDC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_PDC Peripheral DMA Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Pdc hardware registers */
|
||||
typedef struct {
|
||||
RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
|
||||
RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
|
||||
RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
|
||||
RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
|
||||
RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
|
||||
RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
|
||||
RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
|
||||
RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
|
||||
WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
|
||||
RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
|
||||
} Pdc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
|
||||
#define PERIPH_RPR_RXPTR_Pos 0
|
||||
#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
|
||||
#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
|
||||
/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
|
||||
#define PERIPH_RCR_RXCTR_Pos 0
|
||||
#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
|
||||
#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
|
||||
/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
|
||||
#define PERIPH_TPR_TXPTR_Pos 0
|
||||
#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
|
||||
#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
|
||||
/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
|
||||
#define PERIPH_TCR_TXCTR_Pos 0
|
||||
#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
|
||||
#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
|
||||
/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
|
||||
#define PERIPH_RNPR_RXNPTR_Pos 0
|
||||
#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
|
||||
#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
|
||||
/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
|
||||
#define PERIPH_RNCR_RXNCTR_Pos 0
|
||||
#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
|
||||
#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
|
||||
/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
|
||||
#define PERIPH_TNPR_TXNPTR_Pos 0
|
||||
#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
|
||||
#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
|
||||
/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
|
||||
#define PERIPH_TNCR_TXNCTR_Pos 0
|
||||
#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
|
||||
#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
|
||||
/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
|
||||
#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
|
||||
#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
|
||||
#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
|
||||
#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
|
||||
#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
|
||||
#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_PDC_COMPONENT_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,325 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PMC_COMPONENT_
|
||||
#define _SAM3N_PMC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Power Management Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_PMC Power Management Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Pmc hardware registers */
|
||||
typedef struct {
|
||||
WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
|
||||
WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
|
||||
RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
|
||||
RoReg Reserved1[1];
|
||||
WoReg PMC_PCER; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register */
|
||||
WoReg PMC_PCDR; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register */
|
||||
RoReg PMC_PCSR; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register */
|
||||
RoReg Reserved2[1];
|
||||
RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
|
||||
RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
|
||||
RwReg CKGR_PLLR; /**< \brief (Pmc Offset: 0x0028) PLL Register */
|
||||
RoReg Reserved3[1];
|
||||
RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
|
||||
RoReg Reserved4[3];
|
||||
RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
|
||||
RoReg Reserved5[5];
|
||||
WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
|
||||
WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
|
||||
RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
|
||||
RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
|
||||
RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
|
||||
RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
|
||||
WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
|
||||
RoReg Reserved6[26];
|
||||
RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */
|
||||
RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */
|
||||
RoReg Reserved7[9];
|
||||
RwReg PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */
|
||||
} Pmc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
|
||||
#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
|
||||
#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
|
||||
#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
|
||||
/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
|
||||
#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
|
||||
#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
|
||||
#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
|
||||
/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
|
||||
#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
|
||||
#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
|
||||
#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
|
||||
/* -------- PMC_PCER : (PMC Offset: 0x0010) Peripheral Clock Enable Register -------- */
|
||||
#define PMC_PCER_PID2 (0x1u << 2) /**< \brief (PMC_PCER) Peripheral Clock 2 Enable */
|
||||
#define PMC_PCER_PID3 (0x1u << 3) /**< \brief (PMC_PCER) Peripheral Clock 3 Enable */
|
||||
#define PMC_PCER_PID4 (0x1u << 4) /**< \brief (PMC_PCER) Peripheral Clock 4 Enable */
|
||||
#define PMC_PCER_PID5 (0x1u << 5) /**< \brief (PMC_PCER) Peripheral Clock 5 Enable */
|
||||
#define PMC_PCER_PID6 (0x1u << 6) /**< \brief (PMC_PCER) Peripheral Clock 6 Enable */
|
||||
#define PMC_PCER_PID7 (0x1u << 7) /**< \brief (PMC_PCER) Peripheral Clock 7 Enable */
|
||||
#define PMC_PCER_PID8 (0x1u << 8) /**< \brief (PMC_PCER) Peripheral Clock 8 Enable */
|
||||
#define PMC_PCER_PID9 (0x1u << 9) /**< \brief (PMC_PCER) Peripheral Clock 9 Enable */
|
||||
#define PMC_PCER_PID10 (0x1u << 10) /**< \brief (PMC_PCER) Peripheral Clock 10 Enable */
|
||||
#define PMC_PCER_PID11 (0x1u << 11) /**< \brief (PMC_PCER) Peripheral Clock 11 Enable */
|
||||
#define PMC_PCER_PID12 (0x1u << 12) /**< \brief (PMC_PCER) Peripheral Clock 12 Enable */
|
||||
#define PMC_PCER_PID13 (0x1u << 13) /**< \brief (PMC_PCER) Peripheral Clock 13 Enable */
|
||||
#define PMC_PCER_PID14 (0x1u << 14) /**< \brief (PMC_PCER) Peripheral Clock 14 Enable */
|
||||
#define PMC_PCER_PID15 (0x1u << 15) /**< \brief (PMC_PCER) Peripheral Clock 15 Enable */
|
||||
#define PMC_PCER_PID16 (0x1u << 16) /**< \brief (PMC_PCER) Peripheral Clock 16 Enable */
|
||||
#define PMC_PCER_PID17 (0x1u << 17) /**< \brief (PMC_PCER) Peripheral Clock 17 Enable */
|
||||
#define PMC_PCER_PID18 (0x1u << 18) /**< \brief (PMC_PCER) Peripheral Clock 18 Enable */
|
||||
#define PMC_PCER_PID19 (0x1u << 19) /**< \brief (PMC_PCER) Peripheral Clock 19 Enable */
|
||||
#define PMC_PCER_PID20 (0x1u << 20) /**< \brief (PMC_PCER) Peripheral Clock 20 Enable */
|
||||
#define PMC_PCER_PID21 (0x1u << 21) /**< \brief (PMC_PCER) Peripheral Clock 21 Enable */
|
||||
#define PMC_PCER_PID22 (0x1u << 22) /**< \brief (PMC_PCER) Peripheral Clock 22 Enable */
|
||||
#define PMC_PCER_PID23 (0x1u << 23) /**< \brief (PMC_PCER) Peripheral Clock 23 Enable */
|
||||
#define PMC_PCER_PID24 (0x1u << 24) /**< \brief (PMC_PCER) Peripheral Clock 24 Enable */
|
||||
#define PMC_PCER_PID25 (0x1u << 25) /**< \brief (PMC_PCER) Peripheral Clock 25 Enable */
|
||||
#define PMC_PCER_PID26 (0x1u << 26) /**< \brief (PMC_PCER) Peripheral Clock 26 Enable */
|
||||
#define PMC_PCER_PID27 (0x1u << 27) /**< \brief (PMC_PCER) Peripheral Clock 27 Enable */
|
||||
#define PMC_PCER_PID28 (0x1u << 28) /**< \brief (PMC_PCER) Peripheral Clock 28 Enable */
|
||||
#define PMC_PCER_PID29 (0x1u << 29) /**< \brief (PMC_PCER) Peripheral Clock 29 Enable */
|
||||
#define PMC_PCER_PID30 (0x1u << 30) /**< \brief (PMC_PCER) Peripheral Clock 30 Enable */
|
||||
#define PMC_PCER_PID31 (0x1u << 31) /**< \brief (PMC_PCER) Peripheral Clock 31 Enable */
|
||||
/* -------- PMC_PCDR : (PMC Offset: 0x0014) Peripheral Clock Disable Register -------- */
|
||||
#define PMC_PCDR_PID2 (0x1u << 2) /**< \brief (PMC_PCDR) Peripheral Clock 2 Disable */
|
||||
#define PMC_PCDR_PID3 (0x1u << 3) /**< \brief (PMC_PCDR) Peripheral Clock 3 Disable */
|
||||
#define PMC_PCDR_PID4 (0x1u << 4) /**< \brief (PMC_PCDR) Peripheral Clock 4 Disable */
|
||||
#define PMC_PCDR_PID5 (0x1u << 5) /**< \brief (PMC_PCDR) Peripheral Clock 5 Disable */
|
||||
#define PMC_PCDR_PID6 (0x1u << 6) /**< \brief (PMC_PCDR) Peripheral Clock 6 Disable */
|
||||
#define PMC_PCDR_PID7 (0x1u << 7) /**< \brief (PMC_PCDR) Peripheral Clock 7 Disable */
|
||||
#define PMC_PCDR_PID8 (0x1u << 8) /**< \brief (PMC_PCDR) Peripheral Clock 8 Disable */
|
||||
#define PMC_PCDR_PID9 (0x1u << 9) /**< \brief (PMC_PCDR) Peripheral Clock 9 Disable */
|
||||
#define PMC_PCDR_PID10 (0x1u << 10) /**< \brief (PMC_PCDR) Peripheral Clock 10 Disable */
|
||||
#define PMC_PCDR_PID11 (0x1u << 11) /**< \brief (PMC_PCDR) Peripheral Clock 11 Disable */
|
||||
#define PMC_PCDR_PID12 (0x1u << 12) /**< \brief (PMC_PCDR) Peripheral Clock 12 Disable */
|
||||
#define PMC_PCDR_PID13 (0x1u << 13) /**< \brief (PMC_PCDR) Peripheral Clock 13 Disable */
|
||||
#define PMC_PCDR_PID14 (0x1u << 14) /**< \brief (PMC_PCDR) Peripheral Clock 14 Disable */
|
||||
#define PMC_PCDR_PID15 (0x1u << 15) /**< \brief (PMC_PCDR) Peripheral Clock 15 Disable */
|
||||
#define PMC_PCDR_PID16 (0x1u << 16) /**< \brief (PMC_PCDR) Peripheral Clock 16 Disable */
|
||||
#define PMC_PCDR_PID17 (0x1u << 17) /**< \brief (PMC_PCDR) Peripheral Clock 17 Disable */
|
||||
#define PMC_PCDR_PID18 (0x1u << 18) /**< \brief (PMC_PCDR) Peripheral Clock 18 Disable */
|
||||
#define PMC_PCDR_PID19 (0x1u << 19) /**< \brief (PMC_PCDR) Peripheral Clock 19 Disable */
|
||||
#define PMC_PCDR_PID20 (0x1u << 20) /**< \brief (PMC_PCDR) Peripheral Clock 20 Disable */
|
||||
#define PMC_PCDR_PID21 (0x1u << 21) /**< \brief (PMC_PCDR) Peripheral Clock 21 Disable */
|
||||
#define PMC_PCDR_PID22 (0x1u << 22) /**< \brief (PMC_PCDR) Peripheral Clock 22 Disable */
|
||||
#define PMC_PCDR_PID23 (0x1u << 23) /**< \brief (PMC_PCDR) Peripheral Clock 23 Disable */
|
||||
#define PMC_PCDR_PID24 (0x1u << 24) /**< \brief (PMC_PCDR) Peripheral Clock 24 Disable */
|
||||
#define PMC_PCDR_PID25 (0x1u << 25) /**< \brief (PMC_PCDR) Peripheral Clock 25 Disable */
|
||||
#define PMC_PCDR_PID26 (0x1u << 26) /**< \brief (PMC_PCDR) Peripheral Clock 26 Disable */
|
||||
#define PMC_PCDR_PID27 (0x1u << 27) /**< \brief (PMC_PCDR) Peripheral Clock 27 Disable */
|
||||
#define PMC_PCDR_PID28 (0x1u << 28) /**< \brief (PMC_PCDR) Peripheral Clock 28 Disable */
|
||||
#define PMC_PCDR_PID29 (0x1u << 29) /**< \brief (PMC_PCDR) Peripheral Clock 29 Disable */
|
||||
#define PMC_PCDR_PID30 (0x1u << 30) /**< \brief (PMC_PCDR) Peripheral Clock 30 Disable */
|
||||
#define PMC_PCDR_PID31 (0x1u << 31) /**< \brief (PMC_PCDR) Peripheral Clock 31 Disable */
|
||||
/* -------- PMC_PCSR : (PMC Offset: 0x0018) Peripheral Clock Status Register -------- */
|
||||
#define PMC_PCSR_PID2 (0x1u << 2) /**< \brief (PMC_PCSR) Peripheral Clock 2 Status */
|
||||
#define PMC_PCSR_PID3 (0x1u << 3) /**< \brief (PMC_PCSR) Peripheral Clock 3 Status */
|
||||
#define PMC_PCSR_PID4 (0x1u << 4) /**< \brief (PMC_PCSR) Peripheral Clock 4 Status */
|
||||
#define PMC_PCSR_PID5 (0x1u << 5) /**< \brief (PMC_PCSR) Peripheral Clock 5 Status */
|
||||
#define PMC_PCSR_PID6 (0x1u << 6) /**< \brief (PMC_PCSR) Peripheral Clock 6 Status */
|
||||
#define PMC_PCSR_PID7 (0x1u << 7) /**< \brief (PMC_PCSR) Peripheral Clock 7 Status */
|
||||
#define PMC_PCSR_PID8 (0x1u << 8) /**< \brief (PMC_PCSR) Peripheral Clock 8 Status */
|
||||
#define PMC_PCSR_PID9 (0x1u << 9) /**< \brief (PMC_PCSR) Peripheral Clock 9 Status */
|
||||
#define PMC_PCSR_PID10 (0x1u << 10) /**< \brief (PMC_PCSR) Peripheral Clock 10 Status */
|
||||
#define PMC_PCSR_PID11 (0x1u << 11) /**< \brief (PMC_PCSR) Peripheral Clock 11 Status */
|
||||
#define PMC_PCSR_PID12 (0x1u << 12) /**< \brief (PMC_PCSR) Peripheral Clock 12 Status */
|
||||
#define PMC_PCSR_PID13 (0x1u << 13) /**< \brief (PMC_PCSR) Peripheral Clock 13 Status */
|
||||
#define PMC_PCSR_PID14 (0x1u << 14) /**< \brief (PMC_PCSR) Peripheral Clock 14 Status */
|
||||
#define PMC_PCSR_PID15 (0x1u << 15) /**< \brief (PMC_PCSR) Peripheral Clock 15 Status */
|
||||
#define PMC_PCSR_PID16 (0x1u << 16) /**< \brief (PMC_PCSR) Peripheral Clock 16 Status */
|
||||
#define PMC_PCSR_PID17 (0x1u << 17) /**< \brief (PMC_PCSR) Peripheral Clock 17 Status */
|
||||
#define PMC_PCSR_PID18 (0x1u << 18) /**< \brief (PMC_PCSR) Peripheral Clock 18 Status */
|
||||
#define PMC_PCSR_PID19 (0x1u << 19) /**< \brief (PMC_PCSR) Peripheral Clock 19 Status */
|
||||
#define PMC_PCSR_PID20 (0x1u << 20) /**< \brief (PMC_PCSR) Peripheral Clock 20 Status */
|
||||
#define PMC_PCSR_PID21 (0x1u << 21) /**< \brief (PMC_PCSR) Peripheral Clock 21 Status */
|
||||
#define PMC_PCSR_PID22 (0x1u << 22) /**< \brief (PMC_PCSR) Peripheral Clock 22 Status */
|
||||
#define PMC_PCSR_PID23 (0x1u << 23) /**< \brief (PMC_PCSR) Peripheral Clock 23 Status */
|
||||
#define PMC_PCSR_PID24 (0x1u << 24) /**< \brief (PMC_PCSR) Peripheral Clock 24 Status */
|
||||
#define PMC_PCSR_PID25 (0x1u << 25) /**< \brief (PMC_PCSR) Peripheral Clock 25 Status */
|
||||
#define PMC_PCSR_PID26 (0x1u << 26) /**< \brief (PMC_PCSR) Peripheral Clock 26 Status */
|
||||
#define PMC_PCSR_PID27 (0x1u << 27) /**< \brief (PMC_PCSR) Peripheral Clock 27 Status */
|
||||
#define PMC_PCSR_PID28 (0x1u << 28) /**< \brief (PMC_PCSR) Peripheral Clock 28 Status */
|
||||
#define PMC_PCSR_PID29 (0x1u << 29) /**< \brief (PMC_PCSR) Peripheral Clock 29 Status */
|
||||
#define PMC_PCSR_PID30 (0x1u << 30) /**< \brief (PMC_PCSR) Peripheral Clock 30 Status */
|
||||
#define PMC_PCSR_PID31 (0x1u << 31) /**< \brief (PMC_PCSR) Peripheral Clock 31 Status */
|
||||
/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
|
||||
#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
|
||||
#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
|
||||
#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
|
||||
#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
|
||||
#define CKGR_MOR_MOSCRCF_Pos 4
|
||||
#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
|
||||
#define CKGR_MOR_MOSCRCF_4MHZ (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */
|
||||
#define CKGR_MOR_MOSCRCF_8MHZ (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */
|
||||
#define CKGR_MOR_MOSCRCF_12MHZ (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */
|
||||
#define CKGR_MOR_MOSCXTST_Pos 8
|
||||
#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
|
||||
#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
|
||||
#define CKGR_MOR_KEY_Pos 16
|
||||
#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
|
||||
#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
|
||||
#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
|
||||
#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
|
||||
/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
|
||||
#define CKGR_MCFR_MAINF_Pos 0
|
||||
#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
|
||||
#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
|
||||
/* -------- CKGR_PLLR : (PMC Offset: 0x0028) PLL Register -------- */
|
||||
#define CKGR_PLLR_DIV_Pos 0
|
||||
#define CKGR_PLLR_DIV_Msk (0xffu << CKGR_PLLR_DIV_Pos) /**< \brief (CKGR_PLLR) Divider */
|
||||
#define CKGR_PLLR_DIV(value) ((CKGR_PLLR_DIV_Msk & ((value) << CKGR_PLLR_DIV_Pos)))
|
||||
#define CKGR_PLLR_PLLCOUNT_Pos 8
|
||||
#define CKGR_PLLR_PLLCOUNT_Msk (0x3fu << CKGR_PLLR_PLLCOUNT_Pos) /**< \brief (CKGR_PLLR) PLL Counter */
|
||||
#define CKGR_PLLR_PLLCOUNT(value) ((CKGR_PLLR_PLLCOUNT_Msk & ((value) << CKGR_PLLR_PLLCOUNT_Pos)))
|
||||
#define CKGR_PLLR_MUL_Pos 16
|
||||
#define CKGR_PLLR_MUL_Msk (0x7ffu << CKGR_PLLR_MUL_Pos) /**< \brief (CKGR_PLLR) PLL Multiplier */
|
||||
#define CKGR_PLLR_MUL(value) ((CKGR_PLLR_MUL_Msk & ((value) << CKGR_PLLR_MUL_Pos)))
|
||||
#define CKGR_PLLR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLR) */
|
||||
/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
|
||||
#define PMC_MCKR_CSS_Pos 0
|
||||
#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
|
||||
#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */
|
||||
#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */
|
||||
#define PMC_MCKR_CSS_PLL_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLL Clock is selected */
|
||||
#define PMC_MCKR_PRES_Pos 4
|
||||
#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
|
||||
#define PMC_MCKR_PRES_CLK (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */
|
||||
#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */
|
||||
#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */
|
||||
#define PMC_MCKR_PRES_CLK_28 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */
|
||||
#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */
|
||||
#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */
|
||||
#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */
|
||||
#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */
|
||||
#define PMC_MCKR_PLLDIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLL Divisor by 2 */
|
||||
/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
|
||||
#define PMC_PCK_CSS_Pos 0
|
||||
#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
|
||||
#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */
|
||||
#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */
|
||||
#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */
|
||||
#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */
|
||||
#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */
|
||||
#define PMC_PCK_PRES_Pos 4
|
||||
#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Processor Clock Prescaler */
|
||||
#define PMC_PCK_PRES_CLK (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */
|
||||
#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */
|
||||
#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */
|
||||
#define PMC_PCK_PRES_CLK_28 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */
|
||||
#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */
|
||||
#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */
|
||||
#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */
|
||||
/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
|
||||
#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
|
||||
#define PMC_IER_LOCK (0x1u << 1) /**< \brief (PMC_IER) PLL Lock Interrupt Enable */
|
||||
#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
|
||||
#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
|
||||
#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
|
||||
#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
|
||||
/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
|
||||
#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
|
||||
#define PMC_IDR_LOCK (0x1u << 1) /**< \brief (PMC_IDR) PLL Lock Interrupt Disable */
|
||||
#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
|
||||
#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
|
||||
#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
|
||||
#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
|
||||
/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
|
||||
#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
|
||||
#define PMC_SR_LOCK (0x1u << 1) /**< \brief (PMC_SR) PLL Lock Status */
|
||||
#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
|
||||
#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
|
||||
#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
|
||||
#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
|
||||
#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
|
||||
#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
|
||||
#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
|
||||
#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
|
||||
#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
|
||||
#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
|
||||
/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
|
||||
#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
|
||||
#define PMC_IMR_LOCK (0x1u << 1) /**< \brief (PMC_IMR) PLL Lock Interrupt Mask */
|
||||
#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
|
||||
#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
|
||||
#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
|
||||
#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
|
||||
/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
|
||||
#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
|
||||
#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
|
||||
#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
|
||||
#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
|
||||
#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
|
||||
#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
|
||||
#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
|
||||
#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
|
||||
#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
|
||||
#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
|
||||
#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
|
||||
#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
|
||||
#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
|
||||
#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
|
||||
#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
|
||||
#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
|
||||
#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
|
||||
#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
|
||||
#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
|
||||
/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
|
||||
#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */
|
||||
/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
|
||||
#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
|
||||
/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
|
||||
#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
|
||||
#define PMC_WPMR_WPKEY_Pos 8
|
||||
#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
|
||||
#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
|
||||
/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
|
||||
#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */
|
||||
#define PMC_WPSR_WPVSRC_Pos 8
|
||||
#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
|
||||
/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */
|
||||
#define PMC_OCR_CAL4_Pos 0
|
||||
#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */
|
||||
#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos)))
|
||||
#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */
|
||||
#define PMC_OCR_CAL8_Pos 8
|
||||
#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */
|
||||
#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos)))
|
||||
#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */
|
||||
#define PMC_OCR_CAL12_Pos 16
|
||||
#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */
|
||||
#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos)))
|
||||
#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_PMC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PWM_COMPONENT_
|
||||
#define _SAM3N_PWM_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_PWM Pulse Width Modulation Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief PwmCh_num hardware registers */
|
||||
typedef struct {
|
||||
RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
|
||||
RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
|
||||
RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Period Register */
|
||||
RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Counter Register */
|
||||
RwReg PWM_CUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Update Register */
|
||||
RoReg Reserved1[3];
|
||||
} PwmCh_num;
|
||||
/** \brief Pwm hardware registers */
|
||||
#define PWMCH_NUM_NUMBER 4
|
||||
typedef struct {
|
||||
RwReg PWM_MR; /**< \brief (Pwm Offset: 0x00) PWM Mode Register */
|
||||
WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
|
||||
WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
|
||||
RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
|
||||
WoReg PWM_IER; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register */
|
||||
WoReg PWM_IDR; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register */
|
||||
RoReg PWM_IMR; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register */
|
||||
RoReg PWM_ISR; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register */
|
||||
RoReg Reserved1[120];
|
||||
PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
|
||||
} Pwm;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- PWM_MR : (PWM Offset: 0x00) PWM Mode Register -------- */
|
||||
#define PWM_MR_DIVA_Pos 0
|
||||
#define PWM_MR_DIVA_Msk (0xffu << PWM_MR_DIVA_Pos) /**< \brief (PWM_MR) CLKA, CLKB Divide Factor */
|
||||
#define PWM_MR_DIVA_CLK_OFF (0x0u << 0) /**< \brief (PWM_MR) CLKA, CLKB clock is turned off */
|
||||
#define PWM_MR_DIVA_CLK_DIV1 (0x1u << 0) /**< \brief (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */
|
||||
#define PWM_MR_PREA_Pos 8
|
||||
#define PWM_MR_PREA_Msk (0xfu << PWM_MR_PREA_Pos) /**< \brief (PWM_MR) */
|
||||
#define PWM_MR_PREA_MCK (0x0u << 8) /**< \brief (PWM_MR) Master Clock */
|
||||
#define PWM_MR_PREA_MCKDIV2 (0x1u << 8) /**< \brief (PWM_MR) Master Clock divided by 2 */
|
||||
#define PWM_MR_PREA_MCKDIV4 (0x2u << 8) /**< \brief (PWM_MR) Master Clock divided by 4 */
|
||||
#define PWM_MR_PREA_MCKDIV8 (0x3u << 8) /**< \brief (PWM_MR) Master Clock divided by 8 */
|
||||
#define PWM_MR_PREA_MCKDIV16 (0x4u << 8) /**< \brief (PWM_MR) Master Clock divided by 16 */
|
||||
#define PWM_MR_PREA_MCKDIV32 (0x5u << 8) /**< \brief (PWM_MR) Master Clock divided by 32 */
|
||||
#define PWM_MR_PREA_MCKDIV64 (0x6u << 8) /**< \brief (PWM_MR) Master Clock divided by 64 */
|
||||
#define PWM_MR_PREA_MCKDIV128 (0x7u << 8) /**< \brief (PWM_MR) Master Clock divided by 128 */
|
||||
#define PWM_MR_PREA_MCKDIV256 (0x8u << 8) /**< \brief (PWM_MR) Master Clock divided by 256 */
|
||||
#define PWM_MR_PREA_MCKDIV512 (0x9u << 8) /**< \brief (PWM_MR) Master Clock divided by 512 */
|
||||
#define PWM_MR_PREA_MCKDIV1024 (0xAu << 8) /**< \brief (PWM_MR) Master Clock divided by 1024 */
|
||||
#define PWM_MR_DIVB_Pos 16
|
||||
#define PWM_MR_DIVB_Msk (0xffu << PWM_MR_DIVB_Pos) /**< \brief (PWM_MR) CLKA, CLKB Divide Factor */
|
||||
#define PWM_MR_DIVB_CLK_OFF (0x0u << 16) /**< \brief (PWM_MR) CLKA, CLKB clock is turned off */
|
||||
#define PWM_MR_DIVB_CLK_DIV1 (0x1u << 16) /**< \brief (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */
|
||||
#define PWM_MR_PREB_Pos 24
|
||||
#define PWM_MR_PREB_Msk (0xfu << PWM_MR_PREB_Pos) /**< \brief (PWM_MR) */
|
||||
#define PWM_MR_PREB_MCK (0x0u << 24) /**< \brief (PWM_MR) Master Clock */
|
||||
#define PWM_MR_PREB_MCKDIV2 (0x1u << 24) /**< \brief (PWM_MR) Master Clock divided by 2 */
|
||||
#define PWM_MR_PREB_MCKDIV4 (0x2u << 24) /**< \brief (PWM_MR) Master Clock divided by 4 */
|
||||
#define PWM_MR_PREB_MCKDIV8 (0x3u << 24) /**< \brief (PWM_MR) Master Clock divided by 8 */
|
||||
#define PWM_MR_PREB_MCKDIV16 (0x4u << 24) /**< \brief (PWM_MR) Master Clock divided by 16 */
|
||||
#define PWM_MR_PREB_MCKDIV32 (0x5u << 24) /**< \brief (PWM_MR) Master Clock divided by 32 */
|
||||
#define PWM_MR_PREB_MCKDIV64 (0x6u << 24) /**< \brief (PWM_MR) Master Clock divided by 64 */
|
||||
#define PWM_MR_PREB_MCKDIV128 (0x7u << 24) /**< \brief (PWM_MR) Master Clock divided by 128 */
|
||||
#define PWM_MR_PREB_MCKDIV256 (0x8u << 24) /**< \brief (PWM_MR) Master Clock divided by 256 */
|
||||
#define PWM_MR_PREB_MCKDIV512 (0x9u << 24) /**< \brief (PWM_MR) Master Clock divided by 512 */
|
||||
#define PWM_MR_PREB_MCKDIV1024 (0xAu << 24) /**< \brief (PWM_MR) Master Clock divided by 1024 */
|
||||
/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
|
||||
#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
|
||||
#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
|
||||
#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
|
||||
#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
|
||||
/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
|
||||
#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
|
||||
#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
|
||||
#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
|
||||
#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
|
||||
/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
|
||||
#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
|
||||
#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
|
||||
#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
|
||||
#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
|
||||
/* -------- PWM_IER : (PWM Offset: 0x10) PWM Interrupt Enable Register -------- */
|
||||
#define PWM_IER_CHID0 (0x1u << 0) /**< \brief (PWM_IER) Channel ID. */
|
||||
#define PWM_IER_CHID1 (0x1u << 1) /**< \brief (PWM_IER) Channel ID. */
|
||||
#define PWM_IER_CHID2 (0x1u << 2) /**< \brief (PWM_IER) Channel ID. */
|
||||
#define PWM_IER_CHID3 (0x1u << 3) /**< \brief (PWM_IER) Channel ID. */
|
||||
/* -------- PWM_IDR : (PWM Offset: 0x14) PWM Interrupt Disable Register -------- */
|
||||
#define PWM_IDR_CHID0 (0x1u << 0) /**< \brief (PWM_IDR) Channel ID. */
|
||||
#define PWM_IDR_CHID1 (0x1u << 1) /**< \brief (PWM_IDR) Channel ID. */
|
||||
#define PWM_IDR_CHID2 (0x1u << 2) /**< \brief (PWM_IDR) Channel ID. */
|
||||
#define PWM_IDR_CHID3 (0x1u << 3) /**< \brief (PWM_IDR) Channel ID. */
|
||||
/* -------- PWM_IMR : (PWM Offset: 0x18) PWM Interrupt Mask Register -------- */
|
||||
#define PWM_IMR_CHID0 (0x1u << 0) /**< \brief (PWM_IMR) Channel ID. */
|
||||
#define PWM_IMR_CHID1 (0x1u << 1) /**< \brief (PWM_IMR) Channel ID. */
|
||||
#define PWM_IMR_CHID2 (0x1u << 2) /**< \brief (PWM_IMR) Channel ID. */
|
||||
#define PWM_IMR_CHID3 (0x1u << 3) /**< \brief (PWM_IMR) Channel ID. */
|
||||
/* -------- PWM_ISR : (PWM Offset: 0x1C) PWM Interrupt Status Register -------- */
|
||||
#define PWM_ISR_CHID0 (0x1u << 0) /**< \brief (PWM_ISR) Channel ID */
|
||||
#define PWM_ISR_CHID1 (0x1u << 1) /**< \brief (PWM_ISR) Channel ID */
|
||||
#define PWM_ISR_CHID2 (0x1u << 2) /**< \brief (PWM_ISR) Channel ID */
|
||||
#define PWM_ISR_CHID3 (0x1u << 3) /**< \brief (PWM_ISR) Channel ID */
|
||||
/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
|
||||
#define PWM_CMR_CPRE_Pos 0
|
||||
#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
|
||||
#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master Clock */
|
||||
#define PWM_CMR_CPRE_MCKDIV2 (0x1u << 0) /**< \brief (PWM_CMR) Master Clock divided by 2 */
|
||||
#define PWM_CMR_CPRE_MCKDIV4 (0x2u << 0) /**< \brief (PWM_CMR) Master Clock divided by 4 */
|
||||
#define PWM_CMR_CPRE_MCKDIV8 (0x3u << 0) /**< \brief (PWM_CMR) Master Clock divided by 8 */
|
||||
#define PWM_CMR_CPRE_MCKDIV16 (0x4u << 0) /**< \brief (PWM_CMR) Master Clock divided by 16 */
|
||||
#define PWM_CMR_CPRE_MCKDIV32 (0x5u << 0) /**< \brief (PWM_CMR) Master Clock divided by 32 */
|
||||
#define PWM_CMR_CPRE_MCKDIV64 (0x6u << 0) /**< \brief (PWM_CMR) Master Clock divided by 64 */
|
||||
#define PWM_CMR_CPRE_MCKDIV128 (0x7u << 0) /**< \brief (PWM_CMR) Master Clock divided by 128 */
|
||||
#define PWM_CMR_CPRE_MCKDIV256 (0x8u << 0) /**< \brief (PWM_CMR) Master Clock divided by 256 */
|
||||
#define PWM_CMR_CPRE_MCKDIV512 (0x9u << 0) /**< \brief (PWM_CMR) Master Clock divided by 512 */
|
||||
#define PWM_CMR_CPRE_MCKDIV1024 (0xAu << 0) /**< \brief (PWM_CMR) Master Clock divided by 1024 */
|
||||
#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
|
||||
#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
|
||||
#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
|
||||
#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
|
||||
#define PWM_CMR_CPD (0x1u << 10) /**< \brief (PWM_CMR) Channel Update Period */
|
||||
/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
|
||||
#define PWM_CDTY_CDTY_Pos 0
|
||||
#define PWM_CDTY_CDTY_Msk (0xffffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty Cycle */
|
||||
#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
|
||||
/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
|
||||
#define PWM_CPRD_CPRD_Pos 0
|
||||
#define PWM_CPRD_CPRD_Msk (0xffffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
|
||||
#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
|
||||
/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
|
||||
#define PWM_CCNT_CNT_Pos 0
|
||||
#define PWM_CCNT_CNT_Msk (0xffffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
|
||||
/* -------- PWM_CUPD : (PWM Offset: N/A) PWM Channel Update Register -------- */
|
||||
#define PWM_CUPD_CUPD_Pos 0
|
||||
#define PWM_CUPD_CUPD_Msk (0xffffffffu << PWM_CUPD_CUPD_Pos) /**< \brief (PWM_CUPD) */
|
||||
#define PWM_CUPD_CUPD(value) ((PWM_CUPD_CUPD_Msk & ((value) << PWM_CUPD_CUPD_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_PWM_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_RSTC_COMPONENT_
|
||||
#define _SAM3N_RSTC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Reset Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_RSTC Reset Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Rstc hardware registers */
|
||||
typedef struct {
|
||||
WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
|
||||
RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
|
||||
RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
|
||||
} Rstc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
|
||||
#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
|
||||
#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
|
||||
#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
|
||||
#define RSTC_CR_KEY_Pos 24
|
||||
#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
|
||||
#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
|
||||
/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
|
||||
#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
|
||||
#define RSTC_SR_RSTTYP_Pos 8
|
||||
#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
|
||||
#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
|
||||
#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
|
||||
/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
|
||||
#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
|
||||
#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
|
||||
#define RSTC_MR_ERSTL_Pos 8
|
||||
#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
|
||||
#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
|
||||
#define RSTC_MR_KEY_Pos 24
|
||||
#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
|
||||
#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_RSTC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_RTC_COMPONENT_
|
||||
#define _SAM3N_RTC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Real-time Clock */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_RTC Real-time Clock */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Rtc hardware registers */
|
||||
typedef struct {
|
||||
RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
|
||||
RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
|
||||
RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
|
||||
RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
|
||||
RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
|
||||
RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
|
||||
RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
|
||||
WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
|
||||
WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
|
||||
WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
|
||||
RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
|
||||
RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
|
||||
RoReg Reserved1[45];
|
||||
RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
|
||||
} Rtc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
|
||||
#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
|
||||
#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
|
||||
#define RTC_CR_TIMEVSEL_Pos 8
|
||||
#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
|
||||
#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
|
||||
#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
|
||||
#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
|
||||
#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
|
||||
#define RTC_CR_CALEVSEL_Pos 16
|
||||
#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
|
||||
#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
|
||||
#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
|
||||
#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
|
||||
/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
|
||||
#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
|
||||
/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
|
||||
#define RTC_TIMR_SEC_Pos 0
|
||||
#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
|
||||
#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
|
||||
#define RTC_TIMR_MIN_Pos 8
|
||||
#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
|
||||
#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
|
||||
#define RTC_TIMR_HOUR_Pos 16
|
||||
#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
|
||||
#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
|
||||
#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
|
||||
/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
|
||||
#define RTC_CALR_CENT_Pos 0
|
||||
#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
|
||||
#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
|
||||
#define RTC_CALR_YEAR_Pos 8
|
||||
#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
|
||||
#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
|
||||
#define RTC_CALR_MONTH_Pos 16
|
||||
#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
|
||||
#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
|
||||
#define RTC_CALR_DAY_Pos 21
|
||||
#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
|
||||
#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
|
||||
#define RTC_CALR_DATE_Pos 24
|
||||
#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
|
||||
#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
|
||||
/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
|
||||
#define RTC_TIMALR_SEC_Pos 0
|
||||
#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
|
||||
#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
|
||||
#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
|
||||
#define RTC_TIMALR_MIN_Pos 8
|
||||
#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
|
||||
#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
|
||||
#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
|
||||
#define RTC_TIMALR_HOUR_Pos 16
|
||||
#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
|
||||
#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
|
||||
#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
|
||||
#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
|
||||
/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
|
||||
#define RTC_CALALR_MONTH_Pos 16
|
||||
#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
|
||||
#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
|
||||
#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
|
||||
#define RTC_CALALR_DATE_Pos 24
|
||||
#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
|
||||
#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
|
||||
#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
|
||||
/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
|
||||
#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
|
||||
#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
|
||||
#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
|
||||
#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
|
||||
#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
|
||||
/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
|
||||
#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
|
||||
#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
|
||||
#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
|
||||
#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
|
||||
#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
|
||||
/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
|
||||
#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
|
||||
#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
|
||||
#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
|
||||
#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
|
||||
#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
|
||||
/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
|
||||
#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
|
||||
#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
|
||||
#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
|
||||
#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
|
||||
#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
|
||||
/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
|
||||
#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
|
||||
#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
|
||||
#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
|
||||
#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
|
||||
#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
|
||||
/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
|
||||
#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
|
||||
#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
|
||||
#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
|
||||
#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
|
||||
/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
|
||||
#define RTC_WPMR_WPKEY_Pos 8
|
||||
#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */
|
||||
#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_RTC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_RTT_COMPONENT_
|
||||
#define _SAM3N_RTT_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Real-time Timer */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_RTT Real-time Timer */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Rtt hardware registers */
|
||||
typedef struct {
|
||||
RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
|
||||
RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
|
||||
RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
|
||||
RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
|
||||
} Rtt;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
|
||||
#define RTT_MR_RTPRES_Pos 0
|
||||
#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
|
||||
#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
|
||||
#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
|
||||
#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
|
||||
#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
|
||||
/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
|
||||
#define RTT_AR_ALMV_Pos 0
|
||||
#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
|
||||
#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
|
||||
/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
|
||||
#define RTT_VR_CRTV_Pos 0
|
||||
#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
|
||||
/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
|
||||
#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
|
||||
#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_RTT_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_SPI_COMPONENT_
|
||||
#define _SAM3N_SPI_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_SPI Serial Peripheral Interface */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Spi hardware registers */
|
||||
typedef struct {
|
||||
WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
|
||||
RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
|
||||
RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
|
||||
WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
|
||||
RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
|
||||
WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
|
||||
WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
|
||||
RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
|
||||
RoReg Reserved1[4];
|
||||
RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
|
||||
RoReg Reserved2[41];
|
||||
RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
|
||||
RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
|
||||
RoReg Reserved3[5];
|
||||
RwReg SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */
|
||||
RwReg SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */
|
||||
RwReg SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */
|
||||
RoReg SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */
|
||||
} Spi;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
|
||||
#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
|
||||
#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
|
||||
#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
|
||||
#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
|
||||
/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
|
||||
#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
|
||||
#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
|
||||
#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
|
||||
#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
|
||||
#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
|
||||
#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
|
||||
#define SPI_MR_PCS_Pos 16
|
||||
#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
|
||||
#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
|
||||
#define SPI_MR_DLYBCS_Pos 24
|
||||
#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
|
||||
#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
|
||||
/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
|
||||
#define SPI_RDR_RD_Pos 0
|
||||
#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
|
||||
#define SPI_RDR_PCS_Pos 16
|
||||
#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
|
||||
/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
|
||||
#define SPI_TDR_TD_Pos 0
|
||||
#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
|
||||
#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
|
||||
#define SPI_TDR_PCS_Pos 16
|
||||
#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
|
||||
#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
|
||||
#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
|
||||
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
|
||||
#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
|
||||
#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
|
||||
#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
|
||||
#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
|
||||
#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */
|
||||
#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */
|
||||
#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */
|
||||
#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */
|
||||
#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
|
||||
#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
|
||||
#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
|
||||
#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
|
||||
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
|
||||
#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
|
||||
#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
|
||||
#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
|
||||
#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
|
||||
#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */
|
||||
#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */
|
||||
#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */
|
||||
#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */
|
||||
#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
|
||||
#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
|
||||
#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
|
||||
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
|
||||
#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
|
||||
#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
|
||||
#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
|
||||
#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
|
||||
#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */
|
||||
#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */
|
||||
#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */
|
||||
#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */
|
||||
#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
|
||||
#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
|
||||
#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
|
||||
/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
|
||||
#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
|
||||
#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
|
||||
#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
|
||||
#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
|
||||
#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */
|
||||
#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */
|
||||
#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */
|
||||
#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */
|
||||
#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
|
||||
#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
|
||||
#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
|
||||
/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
|
||||
#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
|
||||
#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
|
||||
#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
|
||||
#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
|
||||
#define SPI_CSR_BITS_Pos 4
|
||||
#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
|
||||
#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
|
||||
#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
|
||||
#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
|
||||
#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
|
||||
#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
|
||||
#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
|
||||
#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
|
||||
#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
|
||||
#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
|
||||
#define SPI_CSR_SCBR_Pos 8
|
||||
#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
|
||||
#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
|
||||
#define SPI_CSR_DLYBS_Pos 16
|
||||
#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
|
||||
#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
|
||||
#define SPI_CSR_DLYBCT_Pos 24
|
||||
#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
|
||||
#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
|
||||
/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
|
||||
#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
|
||||
#define SPI_WPMR_SPIWPKEY_Pos 8
|
||||
#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
|
||||
#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
|
||||
/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
|
||||
#define SPI_WPSR_SPIWPVS_Pos 0
|
||||
#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
|
||||
#define SPI_WPSR_SPIWPVSRC_Pos 8
|
||||
#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
|
||||
/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define SPI_RPR_RXPTR_Pos 0
|
||||
#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */
|
||||
#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos)))
|
||||
/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */
|
||||
#define SPI_RCR_RXCTR_Pos 0
|
||||
#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */
|
||||
#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos)))
|
||||
/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define SPI_TPR_TXPTR_Pos 0
|
||||
#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */
|
||||
#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos)))
|
||||
/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define SPI_TCR_TXCTR_Pos 0
|
||||
#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */
|
||||
#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos)))
|
||||
/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define SPI_RNPR_RXNPTR_Pos 0
|
||||
#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */
|
||||
#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos)))
|
||||
/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define SPI_RNCR_RXNCTR_Pos 0
|
||||
#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */
|
||||
#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos)))
|
||||
/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define SPI_TNPR_TXNPTR_Pos 0
|
||||
#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */
|
||||
#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos)))
|
||||
/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define SPI_TNCR_TXNCTR_Pos 0
|
||||
#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */
|
||||
#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos)))
|
||||
/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */
|
||||
#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */
|
||||
#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */
|
||||
#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */
|
||||
#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */
|
||||
#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */
|
||||
#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_SPI_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_SUPC_COMPONENT_
|
||||
#define _SAM3N_SUPC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Supply Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_SUPC Supply Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Supc hardware registers */
|
||||
typedef struct {
|
||||
WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
|
||||
RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
|
||||
RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
|
||||
RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
|
||||
RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
|
||||
RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
|
||||
} Supc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
|
||||
#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
|
||||
#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
|
||||
#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
|
||||
#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
|
||||
#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
|
||||
#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
|
||||
#define SUPC_CR_KEY_Pos 24
|
||||
#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
|
||||
#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
|
||||
/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
|
||||
#define SUPC_SMMR_SMTH_Pos 0
|
||||
#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
|
||||
#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
|
||||
#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
|
||||
#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
|
||||
#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
|
||||
#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
|
||||
#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
|
||||
#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
|
||||
#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
|
||||
#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
|
||||
#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
|
||||
#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
|
||||
#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
|
||||
#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
|
||||
#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
|
||||
#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
|
||||
#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
|
||||
#define SUPC_SMMR_SMSMPL_Pos 8
|
||||
#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
|
||||
#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
|
||||
#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
|
||||
#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
|
||||
#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
|
||||
#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
|
||||
#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
|
||||
#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
|
||||
#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
|
||||
#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
|
||||
#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
|
||||
#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
|
||||
/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
|
||||
#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
|
||||
#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
|
||||
#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
|
||||
#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
|
||||
#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
|
||||
#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
|
||||
#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */
|
||||
#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */
|
||||
#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */
|
||||
#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
|
||||
#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
|
||||
#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
|
||||
#define SUPC_MR_KEY_Pos 24
|
||||
#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
|
||||
#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
|
||||
/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
|
||||
#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
|
||||
#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
|
||||
#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
|
||||
#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
|
||||
#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
|
||||
#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
|
||||
#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_WKUPDBC_Pos 12
|
||||
#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
|
||||
#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
|
||||
#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
|
||||
/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
|
||||
#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
|
||||
#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
|
||||
#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
|
||||
#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
|
||||
#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
|
||||
#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
|
||||
#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
|
||||
#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
|
||||
#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
|
||||
#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
|
||||
#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
|
||||
#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
|
||||
#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
|
||||
#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
|
||||
#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
|
||||
#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
|
||||
#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
|
||||
#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
|
||||
#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
|
||||
#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
|
||||
#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
|
||||
#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
|
||||
#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
|
||||
#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
|
||||
#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
|
||||
#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
|
||||
#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
|
||||
#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
|
||||
#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
|
||||
#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
|
||||
#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
|
||||
#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
|
||||
#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
|
||||
#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
|
||||
#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
|
||||
#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
|
||||
#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
|
||||
#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
|
||||
#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
|
||||
#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */
|
||||
#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */
|
||||
#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
|
||||
#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
|
||||
#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
|
||||
#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
|
||||
#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
|
||||
#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
|
||||
#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
|
||||
#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
|
||||
#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
|
||||
#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
|
||||
#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
|
||||
#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
|
||||
#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
|
||||
#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
|
||||
#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
|
||||
#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
|
||||
#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
|
||||
#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
|
||||
#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
|
||||
#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_SUPC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_TC_COMPONENT_
|
||||
#define _SAM3N_TC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Timer Counter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_TC Timer Counter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief TcChannel hardware registers */
|
||||
typedef struct {
|
||||
RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
|
||||
RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
|
||||
RwReg TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */
|
||||
RoReg Reserved1[1];
|
||||
RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
|
||||
RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
|
||||
RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
|
||||
RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
|
||||
RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
|
||||
RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
|
||||
RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
|
||||
RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
|
||||
RoReg Reserved2[4];
|
||||
} TcChannel;
|
||||
/** \brief Tc hardware registers */
|
||||
#define TCCHANNEL_NUMBER 3
|
||||
typedef struct {
|
||||
TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
|
||||
WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
|
||||
RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
|
||||
WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
|
||||
WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
|
||||
RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
|
||||
RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
|
||||
RoReg Reserved1[3];
|
||||
RwReg TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */
|
||||
} Tc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
|
||||
#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
|
||||
#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
|
||||
#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
|
||||
/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
|
||||
#define TC_CMR_TCCLKS_Pos 0
|
||||
#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
|
||||
#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
|
||||
#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
|
||||
#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
|
||||
#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
|
||||
#define TC_CMR_BURST_Pos 4
|
||||
#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
|
||||
#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
|
||||
#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
|
||||
#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
|
||||
#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
|
||||
#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
|
||||
#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
|
||||
#define TC_CMR_ETRGEDG_Pos 8
|
||||
#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
|
||||
#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
|
||||
#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
|
||||
#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
|
||||
#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
|
||||
#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
|
||||
#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
|
||||
#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
|
||||
#define TC_CMR_LDRA_Pos 16
|
||||
#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
|
||||
#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
|
||||
#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
|
||||
#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
|
||||
#define TC_CMR_LDRB_Pos 18
|
||||
#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
|
||||
#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
|
||||
#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
|
||||
#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
|
||||
#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
|
||||
#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
|
||||
#define TC_CMR_EEVTEDG_Pos 8
|
||||
#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
|
||||
#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
|
||||
#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
|
||||
#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
|
||||
#define TC_CMR_EEVT_Pos 10
|
||||
#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
|
||||
#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
|
||||
#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
|
||||
#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
|
||||
#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
|
||||
#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
|
||||
#define TC_CMR_WAVSEL_Pos 13
|
||||
#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
|
||||
#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
|
||||
#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
|
||||
#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
|
||||
#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
|
||||
#define TC_CMR_ACPA_Pos 16
|
||||
#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
|
||||
#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_ACPC_Pos 18
|
||||
#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
|
||||
#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_AEEVT_Pos 20
|
||||
#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
|
||||
#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_ASWTRG_Pos 22
|
||||
#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
|
||||
#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BCPB_Pos 24
|
||||
#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
|
||||
#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BCPC_Pos 26
|
||||
#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
|
||||
#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BEEVT_Pos 28
|
||||
#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
|
||||
#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BSWTRG_Pos 30
|
||||
#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
|
||||
#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
|
||||
/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */
|
||||
#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */
|
||||
#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */
|
||||
/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
|
||||
#define TC_CV_CV_Pos 0
|
||||
#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
|
||||
/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
|
||||
#define TC_RA_RA_Pos 0
|
||||
#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
|
||||
#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
|
||||
/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
|
||||
#define TC_RB_RB_Pos 0
|
||||
#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
|
||||
#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
|
||||
/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
|
||||
#define TC_RC_RC_Pos 0
|
||||
#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
|
||||
#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
|
||||
/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
|
||||
#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
|
||||
#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
|
||||
#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
|
||||
#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
|
||||
#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
|
||||
#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
|
||||
#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
|
||||
#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
|
||||
#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
|
||||
#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
|
||||
#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
|
||||
/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
|
||||
#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
|
||||
#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
|
||||
#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
|
||||
#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
|
||||
#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
|
||||
#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
|
||||
#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
|
||||
#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
|
||||
/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
|
||||
#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
|
||||
#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
|
||||
#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
|
||||
#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
|
||||
#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
|
||||
#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
|
||||
#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
|
||||
#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
|
||||
/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
|
||||
#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
|
||||
#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
|
||||
#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
|
||||
#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
|
||||
#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
|
||||
#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
|
||||
#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
|
||||
#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
|
||||
/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
|
||||
#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
|
||||
/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
|
||||
#define TC_BMR_TC0XC0S_Pos 0
|
||||
#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
|
||||
#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
|
||||
#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
|
||||
#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
|
||||
#define TC_BMR_TC1XC1S_Pos 2
|
||||
#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
|
||||
#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
|
||||
#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
|
||||
#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
|
||||
#define TC_BMR_TC2XC2S_Pos 4
|
||||
#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
|
||||
#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
|
||||
#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
|
||||
#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
|
||||
#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
|
||||
#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
|
||||
#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
|
||||
#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
|
||||
#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
|
||||
#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
|
||||
#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
|
||||
#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
|
||||
#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
|
||||
#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
|
||||
#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */
|
||||
#define TC_BMR_MAXFILT_Pos 20
|
||||
#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
|
||||
#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
|
||||
/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
|
||||
#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
|
||||
#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
|
||||
#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
|
||||
/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
|
||||
#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
|
||||
#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
|
||||
#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
|
||||
/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
|
||||
#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
|
||||
#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
|
||||
#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
|
||||
/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
|
||||
#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
|
||||
#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
|
||||
#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
|
||||
#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
|
||||
/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */
|
||||
#define TC_WPMR_WPKEY_Pos 8
|
||||
#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */
|
||||
#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_TC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_TWI_COMPONENT_
|
||||
#define _SAM3N_TWI_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Two-wire Interface */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_TWI Two-wire Interface */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Twi hardware registers */
|
||||
typedef struct {
|
||||
WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */
|
||||
RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */
|
||||
RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */
|
||||
RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */
|
||||
RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
|
||||
RoReg Reserved1[3];
|
||||
RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */
|
||||
WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
|
||||
WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
|
||||
RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
|
||||
RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */
|
||||
WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
|
||||
RoReg Reserved2[50];
|
||||
RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
|
||||
RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
|
||||
RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
|
||||
RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
|
||||
} Twi;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
|
||||
#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
|
||||
#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
|
||||
#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
|
||||
#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
|
||||
#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
|
||||
#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
|
||||
#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
|
||||
#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
|
||||
/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
|
||||
#define TWI_MMR_IADRSZ_Pos 8
|
||||
#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
|
||||
#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
|
||||
#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
|
||||
#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
|
||||
#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
|
||||
#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
|
||||
#define TWI_MMR_DADR_Pos 16
|
||||
#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
|
||||
#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
|
||||
/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
|
||||
#define TWI_SMR_SADR_Pos 16
|
||||
#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
|
||||
#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
|
||||
/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
|
||||
#define TWI_IADR_IADR_Pos 0
|
||||
#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
|
||||
#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
|
||||
/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
|
||||
#define TWI_CWGR_CLDIV_Pos 0
|
||||
#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
|
||||
#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
|
||||
#define TWI_CWGR_CHDIV_Pos 8
|
||||
#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
|
||||
#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
|
||||
#define TWI_CWGR_CKDIV_Pos 16
|
||||
#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
|
||||
#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
|
||||
/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
|
||||
#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
|
||||
#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
|
||||
#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
|
||||
#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
|
||||
#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
|
||||
#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
|
||||
#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
|
||||
#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
|
||||
#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
|
||||
#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
|
||||
#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
|
||||
#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
|
||||
#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
|
||||
#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
|
||||
#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
|
||||
/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
|
||||
#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
|
||||
#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
|
||||
#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
|
||||
#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
|
||||
#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
|
||||
#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
|
||||
#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
|
||||
#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
|
||||
#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
|
||||
#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
|
||||
#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
|
||||
#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
|
||||
#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
|
||||
#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
|
||||
/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
|
||||
#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
|
||||
#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
|
||||
#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
|
||||
#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
|
||||
#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
|
||||
#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
|
||||
#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
|
||||
#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
|
||||
#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
|
||||
#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
|
||||
#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
|
||||
#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
|
||||
#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
|
||||
#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
|
||||
/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
|
||||
#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
|
||||
#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
|
||||
#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
|
||||
#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
|
||||
#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
|
||||
#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
|
||||
#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
|
||||
#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
|
||||
#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
|
||||
#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
|
||||
#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
|
||||
#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
|
||||
#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
|
||||
#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
|
||||
/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
|
||||
#define TWI_RHR_RXDATA_Pos 0
|
||||
#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
|
||||
/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
|
||||
#define TWI_THR_TXDATA_Pos 0
|
||||
#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
|
||||
#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
|
||||
/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define TWI_RPR_RXPTR_Pos 0
|
||||
#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
|
||||
#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
|
||||
/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
|
||||
#define TWI_RCR_RXCTR_Pos 0
|
||||
#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
|
||||
#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
|
||||
/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define TWI_TPR_TXPTR_Pos 0
|
||||
#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
|
||||
#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
|
||||
/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define TWI_TCR_TXCTR_Pos 0
|
||||
#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
|
||||
#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
|
||||
/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define TWI_RNPR_RXNPTR_Pos 0
|
||||
#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
|
||||
#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
|
||||
/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define TWI_RNCR_RXNCTR_Pos 0
|
||||
#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
|
||||
#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
|
||||
/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define TWI_TNPR_TXNPTR_Pos 0
|
||||
#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
|
||||
#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
|
||||
/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define TWI_TNCR_TXNCTR_Pos 0
|
||||
#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
|
||||
#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
|
||||
/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
|
||||
#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
|
||||
#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
|
||||
#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
|
||||
#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
|
||||
#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
|
||||
#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_TWI_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_UART_COMPONENT_
|
||||
#define _SAM3N_UART_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_UART Universal Asynchronous Receiver Transmitter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Uart hardware registers */
|
||||
typedef struct {
|
||||
WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
|
||||
RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
|
||||
WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
|
||||
WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
|
||||
RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
|
||||
RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
|
||||
RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
|
||||
WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
|
||||
RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
|
||||
RoReg Reserved1[55];
|
||||
RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
|
||||
RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
|
||||
RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
|
||||
RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
|
||||
} Uart;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
|
||||
#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
|
||||
#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
|
||||
#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
|
||||
#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
|
||||
#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
|
||||
#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
|
||||
#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
|
||||
/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
|
||||
#define UART_MR_PAR_Pos 9
|
||||
#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
|
||||
#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
|
||||
#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
|
||||
#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
|
||||
#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
|
||||
#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
|
||||
#define UART_MR_CHMODE_Pos 14
|
||||
#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
|
||||
#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
|
||||
#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
|
||||
#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
|
||||
#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
|
||||
/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
|
||||
#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
|
||||
#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
|
||||
#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
|
||||
#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
|
||||
#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
|
||||
#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
|
||||
#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
|
||||
#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
|
||||
#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
|
||||
#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
|
||||
/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
|
||||
#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
|
||||
#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
|
||||
#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
|
||||
#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
|
||||
#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
|
||||
#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
|
||||
#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
|
||||
#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
|
||||
#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
|
||||
#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
|
||||
/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
|
||||
#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
|
||||
#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
|
||||
#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
|
||||
#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
|
||||
#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
|
||||
#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
|
||||
#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
|
||||
#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
|
||||
#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
|
||||
#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
|
||||
/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
|
||||
#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
|
||||
#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
|
||||
#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
|
||||
#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
|
||||
#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
|
||||
#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
|
||||
#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
|
||||
#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
|
||||
#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
|
||||
#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
|
||||
/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
|
||||
#define UART_RHR_RXCHR_Pos 0
|
||||
#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
|
||||
/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
|
||||
#define UART_THR_TXCHR_Pos 0
|
||||
#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
|
||||
#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
|
||||
/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
|
||||
#define UART_BRGR_CD_Pos 0
|
||||
#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
|
||||
#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
|
||||
/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define UART_RPR_RXPTR_Pos 0
|
||||
#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
|
||||
#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
|
||||
/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
|
||||
#define UART_RCR_RXCTR_Pos 0
|
||||
#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
|
||||
#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
|
||||
/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define UART_TPR_TXPTR_Pos 0
|
||||
#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
|
||||
#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
|
||||
/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define UART_TCR_TXCTR_Pos 0
|
||||
#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
|
||||
#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
|
||||
/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define UART_RNPR_RXNPTR_Pos 0
|
||||
#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
|
||||
#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
|
||||
/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define UART_RNCR_RXNCTR_Pos 0
|
||||
#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
|
||||
#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
|
||||
/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define UART_TNPR_TXNPTR_Pos 0
|
||||
#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
|
||||
#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
|
||||
/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define UART_TNCR_TXNCTR_Pos 0
|
||||
#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
|
||||
#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
|
||||
/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
|
||||
#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
|
||||
#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
|
||||
#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
|
||||
#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
|
||||
#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
|
||||
#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_UART_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_USART_COMPONENT_
|
||||
#define _SAM3N_USART_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_USART Universal Synchronous Asynchronous Receiver Transmitter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Usart hardware registers */
|
||||
typedef struct {
|
||||
WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
|
||||
RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
|
||||
WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
|
||||
WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
|
||||
RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
|
||||
RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
|
||||
RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
|
||||
WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
|
||||
RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
|
||||
RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
|
||||
RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
|
||||
RoReg Reserved1[5];
|
||||
RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
|
||||
RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
|
||||
RoReg Reserved2[1];
|
||||
RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
|
||||
RoReg Reserved3[37];
|
||||
RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
|
||||
RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
|
||||
RoReg Reserved4[5];
|
||||
RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
|
||||
RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
|
||||
RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
|
||||
RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
|
||||
} Usart;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
|
||||
#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
|
||||
#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
|
||||
#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
|
||||
#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
|
||||
#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
|
||||
#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
|
||||
#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
|
||||
#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
|
||||
#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
|
||||
#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
|
||||
#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
|
||||
#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
|
||||
#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
|
||||
#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
|
||||
#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
|
||||
#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
|
||||
#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
|
||||
#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
|
||||
/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
|
||||
#define US_MR_USART_MODE_Pos 0
|
||||
#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */
|
||||
#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
|
||||
#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
|
||||
#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
|
||||
#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
|
||||
#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
|
||||
#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
|
||||
#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
|
||||
#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
|
||||
#define US_MR_USCLKS_Pos 4
|
||||
#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
|
||||
#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
|
||||
#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
|
||||
#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
|
||||
#define US_MR_CHRL_Pos 6
|
||||
#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
|
||||
#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
|
||||
#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
|
||||
#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
|
||||
#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
|
||||
#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
|
||||
#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
|
||||
#define US_MR_PAR_Pos 9
|
||||
#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
|
||||
#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
|
||||
#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
|
||||
#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
|
||||
#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
|
||||
#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
|
||||
#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
|
||||
#define US_MR_NBSTOP_Pos 12
|
||||
#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
|
||||
#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
|
||||
#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
|
||||
#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
|
||||
#define US_MR_CHMODE_Pos 14
|
||||
#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
|
||||
#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
|
||||
#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
|
||||
#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
|
||||
#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
|
||||
#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
|
||||
#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
|
||||
#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
|
||||
#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
|
||||
#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
|
||||
#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
|
||||
#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
|
||||
#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
|
||||
#define US_MR_MAX_ITERATION_Pos 24
|
||||
#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */
|
||||
#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
|
||||
#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
|
||||
/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
|
||||
#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
|
||||
#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
|
||||
#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
|
||||
#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
|
||||
#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
|
||||
#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
|
||||
#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
|
||||
#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
|
||||
#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
|
||||
#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
|
||||
#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
|
||||
#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
|
||||
#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
|
||||
#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
|
||||
#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
|
||||
#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
|
||||
/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
|
||||
#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
|
||||
#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
|
||||
#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
|
||||
#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
|
||||
#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
|
||||
#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
|
||||
#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
|
||||
#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
|
||||
#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
|
||||
#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
|
||||
#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
|
||||
#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
|
||||
#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
|
||||
#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
|
||||
#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
|
||||
#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
|
||||
/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
|
||||
#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
|
||||
#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
|
||||
#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
|
||||
#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
|
||||
#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
|
||||
#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
|
||||
#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
|
||||
#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
|
||||
#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
|
||||
#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
|
||||
#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
|
||||
#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
|
||||
#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
|
||||
#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
|
||||
#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
|
||||
#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
|
||||
/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
|
||||
#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
|
||||
#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
|
||||
#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
|
||||
#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
|
||||
#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
|
||||
#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
|
||||
#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
|
||||
#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
|
||||
#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
|
||||
#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
|
||||
#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
|
||||
#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
|
||||
#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
|
||||
#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
|
||||
#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
|
||||
#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
|
||||
#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
|
||||
/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
|
||||
#define US_RHR_RXCHR_Pos 0
|
||||
#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
|
||||
#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
|
||||
/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
|
||||
#define US_THR_TXCHR_Pos 0
|
||||
#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
|
||||
#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
|
||||
#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
|
||||
/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
|
||||
#define US_BRGR_CD_Pos 0
|
||||
#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
|
||||
#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
|
||||
#define US_BRGR_FP_Pos 16
|
||||
#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
|
||||
#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
|
||||
/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
|
||||
#define US_RTOR_TO_Pos 0
|
||||
#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
|
||||
#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
|
||||
/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
|
||||
#define US_TTGR_TG_Pos 0
|
||||
#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
|
||||
#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
|
||||
/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
|
||||
#define US_FIDI_FI_DI_RATIO_Pos 0
|
||||
#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
|
||||
#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
|
||||
/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
|
||||
#define US_NER_NB_ERRORS_Pos 0
|
||||
#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
|
||||
/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
|
||||
#define US_IF_IRDA_FILTER_Pos 0
|
||||
#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
|
||||
#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
|
||||
/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
|
||||
#define US_WPMR_WPKEY_Pos 8
|
||||
#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
|
||||
#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
|
||||
/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
|
||||
#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
|
||||
#define US_WPSR_WPVSRC_Pos 8
|
||||
#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
|
||||
/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define US_RPR_RXPTR_Pos 0
|
||||
#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
|
||||
#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
|
||||
/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
|
||||
#define US_RCR_RXCTR_Pos 0
|
||||
#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
|
||||
#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
|
||||
/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define US_TPR_TXPTR_Pos 0
|
||||
#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
|
||||
#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
|
||||
/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define US_TCR_TXCTR_Pos 0
|
||||
#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
|
||||
#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
|
||||
/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define US_RNPR_RXNPTR_Pos 0
|
||||
#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
|
||||
#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
|
||||
/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define US_RNCR_RXNCTR_Pos 0
|
||||
#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
|
||||
#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
|
||||
/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define US_TNPR_TXNPTR_Pos 0
|
||||
#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
|
||||
#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
|
||||
/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define US_TNCR_TXNCTR_Pos 0
|
||||
#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
|
||||
#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
|
||||
/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
|
||||
#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
|
||||
#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
|
||||
#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
|
||||
#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
|
||||
#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
|
||||
#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_USART_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_WDT_COMPONENT_
|
||||
#define _SAM3N_WDT_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Watchdog Timer */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3N_WDT Watchdog Timer */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Wdt hardware registers */
|
||||
typedef struct {
|
||||
WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
|
||||
RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
|
||||
RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
|
||||
} Wdt;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
|
||||
#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
|
||||
#define WDT_CR_KEY_Pos 24
|
||||
#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
|
||||
#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
|
||||
/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
|
||||
#define WDT_MR_WDV_Pos 0
|
||||
#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
|
||||
#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
|
||||
#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
|
||||
#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
|
||||
#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
|
||||
#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
|
||||
#define WDT_MR_WDD_Pos 16
|
||||
#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
|
||||
#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
|
||||
#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
|
||||
#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
|
||||
/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
|
||||
#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
|
||||
#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3N_WDT_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_ADC_INSTANCE_
|
||||
#define _SAM3N_ADC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC peripheral ========== */
|
||||
#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */
|
||||
#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */
|
||||
#define REG_ADC_SEQR1 REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
|
||||
#define REG_ADC_SEQR2 REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
|
||||
#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */
|
||||
#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */
|
||||
#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */
|
||||
#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */
|
||||
#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
|
||||
#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
|
||||
#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
|
||||
#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */
|
||||
#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */
|
||||
#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */
|
||||
#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */
|
||||
#define REG_ADC_CDR REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register */
|
||||
#define REG_ADC_TRGR REG_ACCESS(RwReg, 0x400380C0U) /**< \brief (ADC) Trigger Register */
|
||||
#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
|
||||
#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
|
||||
#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */
|
||||
#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */
|
||||
#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
|
||||
#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
|
||||
#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
|
||||
#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
|
||||
#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
|
||||
#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
|
||||
#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */
|
||||
#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3N_ADC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_CHIPID_INSTANCE_
|
||||
#define _SAM3N_CHIPID_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CHIPID peripheral ========== */
|
||||
#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
|
||||
|
||||
#endif /* _SAM3N_CHIPID_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_DACC_INSTANCE_
|
||||
#define _SAM3N_DACC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DACC peripheral ========== */
|
||||
#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */
|
||||
#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */
|
||||
#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C008U) /**< \brief (DACC) Conversion Data Register */
|
||||
#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
|
||||
#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
|
||||
#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
|
||||
#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
|
||||
#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
|
||||
#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
|
||||
#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
|
||||
#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */
|
||||
#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
|
||||
#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
|
||||
#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
|
||||
#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
|
||||
#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
|
||||
#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
|
||||
#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */
|
||||
#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3N_DACC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_EFC_INSTANCE_
|
||||
#define _SAM3N_EFC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EFC peripheral ========== */
|
||||
#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
|
||||
#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
|
||||
#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
|
||||
#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
|
||||
|
||||
#endif /* _SAM3N_EFC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_GPBR_INSTANCE_
|
||||
#define _SAM3N_GPBR_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GPBR peripheral ========== */
|
||||
#define REG_GPBR_GPBR REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
|
||||
|
||||
#endif /* _SAM3N_GPBR_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_MATRIX_INSTANCE_
|
||||
#define _SAM3N_MATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MATRIX peripheral ========== */
|
||||
#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
|
||||
#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
|
||||
#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_CCFG_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
|
||||
#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
|
||||
#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3N_MATRIX_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PIOA_INSTANCE_
|
||||
#define _SAM3N_PIOA_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOA peripheral ========== */
|
||||
#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
|
||||
#define REG_PIOA_IFSCDR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOA_IFSCER REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOA_IFSCSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
|
||||
#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
|
||||
#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
|
||||
#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
|
||||
#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
|
||||
#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
|
||||
|
||||
#endif /* _SAM3N_PIOA_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PIOB_INSTANCE_
|
||||
#define _SAM3N_PIOB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOB peripheral ========== */
|
||||
#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
|
||||
#define REG_PIOB_IFSCDR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOB_IFSCER REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOB_IFSCSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
|
||||
#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
|
||||
#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
|
||||
#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
|
||||
#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
|
||||
#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
|
||||
|
||||
#endif /* _SAM3N_PIOB_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PIOC_INSTANCE_
|
||||
#define _SAM3N_PIOC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOC peripheral ========== */
|
||||
#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
|
||||
#define REG_PIOC_IFSCDR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOC_IFSCER REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOC_IFSCSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
|
||||
#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
|
||||
#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
|
||||
#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
|
||||
#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
|
||||
#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
|
||||
|
||||
#endif /* _SAM3N_PIOC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PMC_INSTANCE_
|
||||
#define _SAM3N_PMC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PMC peripheral ========== */
|
||||
#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
|
||||
#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
|
||||
#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
|
||||
#define REG_CKGR_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLL Register */
|
||||
#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
|
||||
#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
|
||||
#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
|
||||
#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
|
||||
#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
|
||||
#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
|
||||
|
||||
#endif /* _SAM3N_PMC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_PWM_INSTANCE_
|
||||
#define _SAM3N_PWM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PWM peripheral ========== */
|
||||
#define REG_PWM_MR REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Mode Register */
|
||||
#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */
|
||||
#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */
|
||||
#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */
|
||||
#define REG_PWM_IER REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
|
||||
#define REG_PWM_IDR REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
|
||||
#define REG_PWM_IMR REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
|
||||
#define REG_PWM_ISR REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
|
||||
#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
|
||||
#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
|
||||
#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
|
||||
#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
|
||||
#define REG_PWM_CUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
|
||||
#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
|
||||
#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
|
||||
#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
|
||||
#define REG_PWM_CUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
|
||||
#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
|
||||
#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
|
||||
#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
|
||||
#define REG_PWM_CUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
|
||||
#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
|
||||
#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
|
||||
#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
|
||||
#define REG_PWM_CUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
|
||||
|
||||
#endif /* _SAM3N_PWM_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_RSTC_INSTANCE_
|
||||
#define _SAM3N_RSTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RSTC peripheral ========== */
|
||||
#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */
|
||||
#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */
|
||||
#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */
|
||||
|
||||
#endif /* _SAM3N_RSTC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_RTC_INSTANCE_
|
||||
#define _SAM3N_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */
|
||||
#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */
|
||||
#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */
|
||||
#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */
|
||||
#define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
|
||||
|
||||
#endif /* _SAM3N_RTC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_RTT_INSTANCE_
|
||||
#define _SAM3N_RTT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTT peripheral ========== */
|
||||
#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */
|
||||
#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */
|
||||
#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */
|
||||
#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */
|
||||
|
||||
#endif /* _SAM3N_RTT_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_SPI_INSTANCE_
|
||||
#define _SAM3N_SPI_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SPI peripheral ========== */
|
||||
#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
|
||||
#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
|
||||
#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
|
||||
#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
|
||||
#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
|
||||
#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
|
||||
#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
|
||||
#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
|
||||
#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
|
||||
#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
|
||||
#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
|
||||
#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */
|
||||
#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */
|
||||
#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
|
||||
#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
|
||||
#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
|
||||
#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
|
||||
#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
|
||||
#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
|
||||
#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */
|
||||
#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3N_SPI_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_SUPC_INSTANCE_
|
||||
#define _SAM3N_SUPC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SUPC peripheral ========== */
|
||||
#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
|
||||
#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
|
||||
#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
|
||||
|
||||
#endif /* _SAM3N_SUPC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_TC0_INSTANCE_
|
||||
#define _SAM3N_TC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC0 peripheral ========== */
|
||||
#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
|
||||
#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC0_SMMR0 REG_ACCESS(RwReg, 0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
|
||||
#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
|
||||
#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
|
||||
#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
|
||||
#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
|
||||
#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
|
||||
#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC0_SMMR1 REG_ACCESS(RwReg, 0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
|
||||
#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
|
||||
#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
|
||||
#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
|
||||
#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
|
||||
#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
|
||||
#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC0_SMMR2 REG_ACCESS(RwReg, 0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
|
||||
#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
|
||||
#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
|
||||
#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
|
||||
#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
|
||||
#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
|
||||
#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
|
||||
|
||||
#endif /* _SAM3N_TC0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_TC1_INSTANCE_
|
||||
#define _SAM3N_TC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC1 peripheral ========== */
|
||||
#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
|
||||
#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC1_SMMR0 REG_ACCESS(RwReg, 0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
|
||||
#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
|
||||
#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
|
||||
#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
|
||||
#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
|
||||
#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
|
||||
#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC1_SMMR1 REG_ACCESS(RwReg, 0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
|
||||
#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
|
||||
#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
|
||||
#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
|
||||
#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
|
||||
#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
|
||||
#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC1_SMMR2 REG_ACCESS(RwReg, 0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
|
||||
#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
|
||||
#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
|
||||
#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
|
||||
#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
|
||||
#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */
|
||||
#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */
|
||||
#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
|
||||
#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
|
||||
#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
|
||||
#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
|
||||
#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
|
||||
|
||||
#endif /* _SAM3N_TC1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_TWI0_INSTANCE_
|
||||
#define _SAM3N_TWI0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TWI0 peripheral ========== */
|
||||
#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */
|
||||
#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */
|
||||
#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */
|
||||
#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */
|
||||
#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
|
||||
#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */
|
||||
#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
|
||||
#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
|
||||
#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
|
||||
#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */
|
||||
#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
|
||||
#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
|
||||
#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */
|
||||
#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
|
||||
#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
|
||||
#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
|
||||
#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
|
||||
#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
|
||||
#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
|
||||
#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */
|
||||
#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3N_TWI0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_TWI1_INSTANCE_
|
||||
#define _SAM3N_TWI1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TWI1 peripheral ========== */
|
||||
#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */
|
||||
#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */
|
||||
#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
|
||||
#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
|
||||
#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
|
||||
#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */
|
||||
#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
|
||||
#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
|
||||
#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
|
||||
#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
|
||||
#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
|
||||
|
||||
#endif /* _SAM3N_TWI1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_UART0_INSTANCE_
|
||||
#define _SAM3N_UART0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for UART0 peripheral ========== */
|
||||
#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */
|
||||
#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */
|
||||
#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
|
||||
#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
|
||||
#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
|
||||
#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */
|
||||
#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */
|
||||
#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
|
||||
#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
|
||||
#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
|
||||
#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */
|
||||
#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
|
||||
#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
|
||||
#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
|
||||
#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
|
||||
#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
|
||||
#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
|
||||
#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */
|
||||
#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3N_UART0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_UART1_INSTANCE_
|
||||
#define _SAM3N_UART1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for UART1 peripheral ========== */
|
||||
#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */
|
||||
#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */
|
||||
#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
|
||||
#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
|
||||
#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
|
||||
#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */
|
||||
#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */
|
||||
#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
|
||||
#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
|
||||
|
||||
#endif /* _SAM3N_UART1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_USART0_INSTANCE_
|
||||
#define _SAM3N_USART0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART0 peripheral ========== */
|
||||
#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */
|
||||
#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */
|
||||
#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */
|
||||
#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */
|
||||
#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
|
||||
#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
|
||||
#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */
|
||||
#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
|
||||
#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
|
||||
#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */
|
||||
#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */
|
||||
#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
|
||||
#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
|
||||
#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
|
||||
#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
|
||||
#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
|
||||
#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
|
||||
#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */
|
||||
#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3N_USART0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_USART1_INSTANCE_
|
||||
#define _SAM3N_USART1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART1 peripheral ========== */
|
||||
#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */
|
||||
#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */
|
||||
#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */
|
||||
#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */
|
||||
#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
|
||||
#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
|
||||
#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */
|
||||
#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
|
||||
#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3N_USART1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_WDT_INSTANCE_
|
||||
#define _SAM3N_WDT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */
|
||||
#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */
|
||||
#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */
|
||||
|
||||
#endif /* _SAM3N_WDT_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N1A_PIO_
|
||||
#define _SAM3N1A_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
|
||||
#endif /* _SAM3N1A_PIO_ */
|
||||
|
|
@ -0,0 +1,212 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N1B_PIO_
|
||||
#define _SAM3N1B_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
|
||||
#endif /* _SAM3N1B_PIO_ */
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N1C_PIO_
|
||||
#define _SAM3N1C_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
|
||||
#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
|
||||
#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
|
||||
#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
|
||||
#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
|
||||
#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
|
||||
#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
|
||||
#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
|
||||
#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
|
||||
#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
|
||||
#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
|
||||
#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
|
||||
#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
|
||||
#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
|
||||
#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
|
||||
#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
|
||||
#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
|
||||
#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
|
||||
#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
|
||||
#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
|
||||
#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
|
||||
#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
|
||||
#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
|
||||
#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
|
||||
#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
|
||||
#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
|
||||
#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
|
||||
#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
|
||||
#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
|
||||
#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
|
||||
#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
|
||||
#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TC1 peripheral ========== */
|
||||
#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
|
||||
#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
|
||||
#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
|
||||
#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
|
||||
#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
|
||||
#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
|
||||
#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
|
||||
#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
|
||||
#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PC0_IDX 64
|
||||
#define PIO_PC1_IDX 65
|
||||
#define PIO_PC2_IDX 66
|
||||
#define PIO_PC3_IDX 67
|
||||
#define PIO_PC4_IDX 68
|
||||
#define PIO_PC5_IDX 69
|
||||
#define PIO_PC6_IDX 70
|
||||
#define PIO_PC7_IDX 71
|
||||
#define PIO_PC8_IDX 72
|
||||
#define PIO_PC9_IDX 73
|
||||
#define PIO_PC10_IDX 74
|
||||
#define PIO_PC11_IDX 75
|
||||
#define PIO_PC12_IDX 76
|
||||
#define PIO_PC13_IDX 77
|
||||
#define PIO_PC14_IDX 78
|
||||
#define PIO_PC15_IDX 79
|
||||
#define PIO_PC16_IDX 80
|
||||
#define PIO_PC17_IDX 81
|
||||
#define PIO_PC18_IDX 82
|
||||
#define PIO_PC19_IDX 83
|
||||
#define PIO_PC20_IDX 84
|
||||
#define PIO_PC21_IDX 85
|
||||
#define PIO_PC22_IDX 86
|
||||
#define PIO_PC23_IDX 87
|
||||
#define PIO_PC24_IDX 88
|
||||
#define PIO_PC25_IDX 89
|
||||
#define PIO_PC26_IDX 90
|
||||
#define PIO_PC27_IDX 91
|
||||
#define PIO_PC28_IDX 92
|
||||
#define PIO_PC29_IDX 93
|
||||
#define PIO_PC30_IDX 94
|
||||
#define PIO_PC31_IDX 95
|
||||
|
||||
#endif /* _SAM3N1C_PIO_ */
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N2A_PIO_
|
||||
#define _SAM3N2A_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
|
||||
#endif /* _SAM3N2A_PIO_ */
|
||||
|
|
@ -0,0 +1,212 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N2B_PIO_
|
||||
#define _SAM3N2B_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
|
||||
#endif /* _SAM3N2B_PIO_ */
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N2C_PIO_
|
||||
#define _SAM3N2C_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
|
||||
#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
|
||||
#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
|
||||
#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
|
||||
#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
|
||||
#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
|
||||
#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
|
||||
#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
|
||||
#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
|
||||
#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
|
||||
#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
|
||||
#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
|
||||
#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
|
||||
#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
|
||||
#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
|
||||
#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
|
||||
#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
|
||||
#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
|
||||
#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
|
||||
#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
|
||||
#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
|
||||
#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
|
||||
#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
|
||||
#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
|
||||
#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
|
||||
#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
|
||||
#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
|
||||
#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
|
||||
#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
|
||||
#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
|
||||
#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
|
||||
#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TC1 peripheral ========== */
|
||||
#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
|
||||
#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
|
||||
#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
|
||||
#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
|
||||
#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
|
||||
#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
|
||||
#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
|
||||
#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
|
||||
#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PC0_IDX 64
|
||||
#define PIO_PC1_IDX 65
|
||||
#define PIO_PC2_IDX 66
|
||||
#define PIO_PC3_IDX 67
|
||||
#define PIO_PC4_IDX 68
|
||||
#define PIO_PC5_IDX 69
|
||||
#define PIO_PC6_IDX 70
|
||||
#define PIO_PC7_IDX 71
|
||||
#define PIO_PC8_IDX 72
|
||||
#define PIO_PC9_IDX 73
|
||||
#define PIO_PC10_IDX 74
|
||||
#define PIO_PC11_IDX 75
|
||||
#define PIO_PC12_IDX 76
|
||||
#define PIO_PC13_IDX 77
|
||||
#define PIO_PC14_IDX 78
|
||||
#define PIO_PC15_IDX 79
|
||||
#define PIO_PC16_IDX 80
|
||||
#define PIO_PC17_IDX 81
|
||||
#define PIO_PC18_IDX 82
|
||||
#define PIO_PC19_IDX 83
|
||||
#define PIO_PC20_IDX 84
|
||||
#define PIO_PC21_IDX 85
|
||||
#define PIO_PC22_IDX 86
|
||||
#define PIO_PC23_IDX 87
|
||||
#define PIO_PC24_IDX 88
|
||||
#define PIO_PC25_IDX 89
|
||||
#define PIO_PC26_IDX 90
|
||||
#define PIO_PC27_IDX 91
|
||||
#define PIO_PC28_IDX 92
|
||||
#define PIO_PC29_IDX 93
|
||||
#define PIO_PC30_IDX 94
|
||||
#define PIO_PC31_IDX 95
|
||||
|
||||
#endif /* _SAM3N2C_PIO_ */
|
||||
|
|
@ -0,0 +1,180 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N4A_PIO_
|
||||
#define _SAM3N4A_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
|
||||
#endif /* _SAM3N4A_PIO_ */
|
||||
|
|
@ -0,0 +1,212 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N4B_PIO_
|
||||
#define _SAM3N4B_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
|
||||
#endif /* _SAM3N4B_PIO_ */
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N4C_PIO_
|
||||
#define _SAM3N4C_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
|
||||
#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
|
||||
#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
|
||||
#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
|
||||
#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
|
||||
#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
|
||||
#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
|
||||
#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
|
||||
#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
|
||||
#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
|
||||
#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
|
||||
#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
|
||||
#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
|
||||
#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
|
||||
#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
|
||||
#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
|
||||
#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
|
||||
#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
|
||||
#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
|
||||
#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
|
||||
#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
|
||||
#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
|
||||
#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
|
||||
#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
|
||||
#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
|
||||
#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
|
||||
#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
|
||||
#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
|
||||
#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
|
||||
#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
|
||||
#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
|
||||
#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */
|
||||
#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */
|
||||
#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */
|
||||
#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */
|
||||
#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */
|
||||
#define PIO_PC31X1_AD15 (1u << 31) /**< \brief Adc signal: AD15 */
|
||||
#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */
|
||||
#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */
|
||||
#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */
|
||||
#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */
|
||||
#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */
|
||||
#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for DACC peripheral ========== */
|
||||
#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */
|
||||
#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PC16B_PCK0 (1u << 16) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PC17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */
|
||||
#define PIO_PC14B_PCK2 (1u << 14) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA11B_PWM0 (1u << 11) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA23B_PWM0 (1u << 23) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PB0A_PWM0 (1u << 0) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC8B_PWM0 (1u << 8) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC18B_PWM0 (1u << 18) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PC22B_PWM0 (1u << 22) /**< \brief Pwm signal: PWM0 */
|
||||
#define PIO_PA1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA12B_PWM1 (1u << 12) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA24B_PWM1 (1u << 24) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PB1A_PWM1 (1u << 1) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC9B_PWM1 (1u << 9) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PC19B_PWM1 (1u << 19) /**< \brief Pwm signal: PWM1 */
|
||||
#define PIO_PA2A_PWM2 (1u << 2) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA13B_PWM2 (1u << 13) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA25B_PWM2 (1u << 25) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PB4B_PWM2 (1u << 4) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC10B_PWM2 (1u << 10) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PC20B_PWM2 (1u << 20) /**< \brief Pwm signal: PWM2 */
|
||||
#define PIO_PA7B_PWM3 (1u << 7) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PA14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PB14B_PWM3 (1u << 14) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC11B_PWM3 (1u << 11) /**< \brief Pwm signal: PWM3 */
|
||||
#define PIO_PC21B_PWM3 (1u << 21) /**< \brief Pwm signal: PWM3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC7B_NPCS2 (1u << 7) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TC1 peripheral ========== */
|
||||
#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */
|
||||
#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */
|
||||
#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */
|
||||
#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */
|
||||
#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */
|
||||
#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */
|
||||
#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */
|
||||
#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */
|
||||
#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART0 peripheral ========== */
|
||||
#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */
|
||||
#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */
|
||||
/* ========== Pio definition for UART1 peripheral ========== */
|
||||
#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */
|
||||
#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PC0_IDX 64
|
||||
#define PIO_PC1_IDX 65
|
||||
#define PIO_PC2_IDX 66
|
||||
#define PIO_PC3_IDX 67
|
||||
#define PIO_PC4_IDX 68
|
||||
#define PIO_PC5_IDX 69
|
||||
#define PIO_PC6_IDX 70
|
||||
#define PIO_PC7_IDX 71
|
||||
#define PIO_PC8_IDX 72
|
||||
#define PIO_PC9_IDX 73
|
||||
#define PIO_PC10_IDX 74
|
||||
#define PIO_PC11_IDX 75
|
||||
#define PIO_PC12_IDX 76
|
||||
#define PIO_PC13_IDX 77
|
||||
#define PIO_PC14_IDX 78
|
||||
#define PIO_PC15_IDX 79
|
||||
#define PIO_PC16_IDX 80
|
||||
#define PIO_PC17_IDX 81
|
||||
#define PIO_PC18_IDX 82
|
||||
#define PIO_PC19_IDX 83
|
||||
#define PIO_PC20_IDX 84
|
||||
#define PIO_PC21_IDX 85
|
||||
#define PIO_PC22_IDX 86
|
||||
#define PIO_PC23_IDX 87
|
||||
#define PIO_PC24_IDX 88
|
||||
#define PIO_PC25_IDX 89
|
||||
#define PIO_PC26_IDX 90
|
||||
#define PIO_PC27_IDX 91
|
||||
#define PIO_PC28_IDX 92
|
||||
#define PIO_PC29_IDX 93
|
||||
#define PIO_PC30_IDX 94
|
||||
#define PIO_PC31_IDX 95
|
||||
|
||||
#endif /* _SAM3N4C_PIO_ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N_
|
||||
#define _SAM3N_
|
||||
|
||||
#if defined __sam3n1a__
|
||||
#include "SAM3N1A.h"
|
||||
#elif defined __sam3n1b__
|
||||
#include "SAM3N1B.h"
|
||||
#elif defined __sam3n1c__
|
||||
#include "SAM3N1C.h"
|
||||
#elif defined __sam3n2a__
|
||||
#include "SAM3N2A.h"
|
||||
#elif defined __sam3n2b__
|
||||
#include "SAM3N2B.h"
|
||||
#elif defined __sam3n2c__
|
||||
#include "SAM3N2C.h"
|
||||
#elif defined __sam3n4a__
|
||||
#include "SAM3N4A.h"
|
||||
#elif defined __sam3n4b__
|
||||
#include "SAM3N4B.h"
|
||||
#elif defined __sam3n4c__
|
||||
#include "SAM3N4C.h"
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _SAM3N_ */
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N1A_
|
||||
#define _SAM3N1A_
|
||||
|
||||
/** \addtogroup SAM3N1A_definitions SAM3N1A definitions
|
||||
This file defines all structures and symbols for SAM3N1A:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N1A specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N1A Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N1A Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N1A Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N1A Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N1A Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N1A Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N1A Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N1A UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N1A UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N1A Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N1A Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N1A Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N1A USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N1A USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N1A Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N1A Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N1A Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N1A Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N1A Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N1A Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N1A Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N1A Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N1A Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N1A Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N1A Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N1A Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N1A does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N1A uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1A_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N1A.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N1A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x10000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 256
|
||||
#define IFLASH_NB_OF_LOCK_BITS 4
|
||||
#define IRAM_SIZE 0x2000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N1A_ */
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N1B_
|
||||
#define _SAM3N1B_
|
||||
|
||||
/** \addtogroup SAM3N1B_definitions SAM3N1B definitions
|
||||
This file defines all structures and symbols for SAM3N1B:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1B_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N1B specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N1B Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N1B Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N1B Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N1B Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N1B Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N1B Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N1B Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N1B UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N1B UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N1B Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N1B Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N1B Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N1B USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N1B USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N1B Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N1B Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N1B Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N1B Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N1B Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N1B Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N1B Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N1B Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N1B Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N1B Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N1B Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N1B Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N1B does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N1B uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1B_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1B_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1B_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1B_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1B_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N1B.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N1B */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x10000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 256
|
||||
#define IFLASH_NB_OF_LOCK_BITS 4
|
||||
#define IRAM_SIZE 0x2000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N1B_ */
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N1C_
|
||||
#define _SAM3N1C_
|
||||
|
||||
/** \addtogroup SAM3N1C_definitions SAM3N1C definitions
|
||||
This file defines all structures and symbols for SAM3N1C:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1C_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N1C specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N1C Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N1C Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N1C Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N1C Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N1C Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N1C Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N1C Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N1C UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N1C UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N1C Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N1C Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N1C Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N1C USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N1C USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N1C Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N1C Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N1C Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N1C Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N1C Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N1C Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N1C Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N1C Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N1C Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N1C Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N1C Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N1C Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N1C does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N1C uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1C_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1C_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TC1.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/PIOC.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1C_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1C_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N1C_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N1C.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N1C */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x10000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 256
|
||||
#define IFLASH_NB_OF_LOCK_BITS 4
|
||||
#define IRAM_SIZE 0x2000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N1C_ */
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N2A_
|
||||
#define _SAM3N2A_
|
||||
|
||||
/** \addtogroup SAM3N2A_definitions SAM3N2A definitions
|
||||
This file defines all structures and symbols for SAM3N2A:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N2A specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N2A Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N2A Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N2A Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N2A Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N2A Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N2A Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N2A Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N2A UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N2A UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N2A Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N2A Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N2A Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N2A USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N2A USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N2A Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N2A Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N2A Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N2A Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N2A Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N2A Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N2A Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N2A Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N2A Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N2A Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N2A Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N2A Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N2A does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N2A uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2A_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N2A.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N2A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x20000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 512
|
||||
#define IFLASH_NB_OF_LOCK_BITS 8
|
||||
#define IRAM_SIZE 0x4000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N2A_ */
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N2B_
|
||||
#define _SAM3N2B_
|
||||
|
||||
/** \addtogroup SAM3N2B_definitions SAM3N2B definitions
|
||||
This file defines all structures and symbols for SAM3N2B:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2B_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N2B specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N2B Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N2B Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N2B Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N2B Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N2B Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N2B Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N2B Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N2B UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N2B UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N2B Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N2B Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N2B Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N2B USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N2B USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N2B Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N2B Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N2B Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N2B Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N2B Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N2B Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N2B Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N2B Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N2B Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N2B Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N2B Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N2B Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N2B does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N2B uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2B_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2B_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2B_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2B_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2B_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N2B.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N2B */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x20000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 512
|
||||
#define IFLASH_NB_OF_LOCK_BITS 8
|
||||
#define IRAM_SIZE 0x4000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N2B_ */
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N2C_
|
||||
#define _SAM3N2C_
|
||||
|
||||
/** \addtogroup SAM3N2C_definitions SAM3N2C definitions
|
||||
This file defines all structures and symbols for SAM3N2C:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2C_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N2C specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N2C Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N2C Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N2C Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N2C Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N2C Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N2C Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N2C Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N2C UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N2C UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N2C Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N2C Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N2C Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N2C USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N2C USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N2C Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N2C Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N2C Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N2C Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N2C Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N2C Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N2C Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N2C Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N2C Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N2C Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N2C Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N2C Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N2C does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N2C uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2C_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2C_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TC1.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/PIOC.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2C_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2C_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TC1 CAST(Tc , 0x40014000U) /**< \brief (TC1 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40028000U) /**< \brief (USART1 ) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define PIOC CAST(Pio , 0x400E1200U) /**< \brief (PIOC ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N2C_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N2C.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N2C */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x20000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 512
|
||||
#define IFLASH_NB_OF_LOCK_BITS 8
|
||||
#define IRAM_SIZE 0x4000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N2C_ */
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3N4A_
|
||||
#define _SAM3N4A_
|
||||
|
||||
/** \addtogroup SAM3N4A_definitions SAM3N4A definitions
|
||||
This file defines all structures and symbols for SAM3N4A:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N4A_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3N4A specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3N4A Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3N4A Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3N4A Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3N4A Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3N4A Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3N4A Power Management Controller (PMC) */
|
||||
EFC_IRQn = 6, /**< 6 SAM3N4A Enhanced Flash Controller (EFC) */
|
||||
UART0_IRQn = 8, /**< 8 SAM3N4A UART 0 (UART0) */
|
||||
UART1_IRQn = 9, /**< 9 SAM3N4A UART 1 (UART1) */
|
||||
PIOA_IRQn = 11, /**< 11 SAM3N4A Parallel I/O Controller A (PIOA) */
|
||||
PIOB_IRQn = 12, /**< 12 SAM3N4A Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 13, /**< 13 SAM3N4A Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 14, /**< 14 SAM3N4A USART 0 (USART0) */
|
||||
USART1_IRQn = 15, /**< 15 SAM3N4A USART 1 (USART1) */
|
||||
TWI0_IRQn = 19, /**< 19 SAM3N4A Two Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 20, /**< 20 SAM3N4A Two Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 21, /**< 21 SAM3N4A Serial Peripheral Interface (SPI) */
|
||||
TC0_IRQn = 23, /**< 23 SAM3N4A Timer/Counter 0 (TC0) */
|
||||
TC1_IRQn = 24, /**< 24 SAM3N4A Timer/Counter 1 (TC1) */
|
||||
TC2_IRQn = 25, /**< 25 SAM3N4A Timer/Counter 2 (TC2) */
|
||||
TC3_IRQn = 26, /**< 26 SAM3N4A Timer/Counter 3 (TC3) */
|
||||
TC4_IRQn = 27, /**< 27 SAM3N4A Timer/Counter 4 (TC4) */
|
||||
TC5_IRQn = 28, /**< 28 SAM3N4A Timer/Counter 5 (TC5) */
|
||||
ADC_IRQn = 29, /**< 29 SAM3N4A Analog To Digital Converter (ADC) */
|
||||
DACC_IRQn = 30, /**< 30 SAM3N4A Digital To Analog Converter (DACC) */
|
||||
PWM_IRQn = 31 /**< 31 SAM3N4A Pulse Width Modulation (PWM) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 0 /**< SAM3N4A does not provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3N4A uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N4A_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DACC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N4A_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DACC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART0.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/UART1.h"
|
||||
#include "instance/EFC.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N4A_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC ( 6) /**< \brief Enhanced Flash Controller (EFC) */
|
||||
#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */
|
||||
#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */
|
||||
#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */
|
||||
#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (14) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (15) /**< \brief USART 1 (USART1) */
|
||||
#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */
|
||||
#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */
|
||||
#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */
|
||||
#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */
|
||||
#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */
|
||||
#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */
|
||||
#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */
|
||||
#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */
|
||||
#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N4A_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define PDC_SPI CAST(Pdc , 0x40008100U) /**< \brief (PDC_SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40010000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40018000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x4001C000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x40020000U) /**< \brief (PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40024000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40024100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define ADC CAST(Adc , 0x40038000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x40038100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DACC CAST(Dacc , 0x4003C000U) /**< \brief (DACC ) Base Address */
|
||||
#define PDC_DACC CAST(Pdc , 0x4003C100U) /**< \brief (PDC_DACC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART0 CAST(Uart , 0x400E0600U) /**< \brief (UART0 ) Base Address */
|
||||
#define PDC_UART0 CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define UART1 CAST(Uart , 0x400E0800U) /**< \brief (UART1 ) Base Address */
|
||||
#define EFC CAST(Efc , 0x400E0A00U) /**< \brief (EFC ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0E00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E1000U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1400U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1410U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1430U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1450U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1460U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1490U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3N4A_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3N4A.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3N4A */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x40000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 16384
|
||||
#define IFLASH_NB_OF_PAGES 1024
|
||||
#define IFLASH_NB_OF_LOCK_BITS 16
|
||||
#define IRAM_SIZE 0x6000
|
||||
|
||||
#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
|
||||
#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
|
||||
#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3N4A_ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue