mirror of https://github.com/noisymime/Arduino.git
[sam] adding up to date sam3u headers
This commit is contained in:
Thibaut VIARD
parent
b9935eb38c
commit
d09f81d623
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/* %ATMEL_LICENCE% */
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#ifndef _SAM3U_ADC_COMPONENT_
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#define _SAM3U_ADC_COMPONENT_
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/* ============================================================================= */
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/** SOFTWARE API DEFINITION FOR Analog-to-digital Converter */
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/* ============================================================================= */
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/** \addtogroup SAM3U_ADC Analog-to-digital Converter */
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/*@{*/
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#ifndef __ASSEMBLY__
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/** \brief Adc hardware registers */
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typedef struct {
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WoReg ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */
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RwReg ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */
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RoReg Reserved1[2];
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WoReg ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */
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WoReg ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */
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RoReg ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */
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RoReg ADC_SR; /**< \brief (Adc Offset: 0x1C) Status Register */
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RoReg ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */
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WoReg ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */
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WoReg ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */
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RoReg ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */
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RoReg ADC_CDR[8]; /**< \brief (Adc Offset: 0x30) Channel Data Register */
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RoReg Reserved2[44];
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RwReg ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */
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RwReg ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */
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RwReg ADC_TPR; /**< \brief (Adc Offset: 0x108) Transmit Pointer Register */
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RwReg ADC_TCR; /**< \brief (Adc Offset: 0x10C) Transmit Counter Register */
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RwReg ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */
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RwReg ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */
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RwReg ADC_TNPR; /**< \brief (Adc Offset: 0x118) Transmit Next Pointer Register */
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RwReg ADC_TNCR; /**< \brief (Adc Offset: 0x11C) Transmit Next Counter Register */
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WoReg ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */
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RoReg ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */
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} Adc;
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#endif /* __ASSEMBLY__ */
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/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */
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#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */
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#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */
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/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */
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#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */
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#define ADC_MR_TRGSEL_Pos 1
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#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */
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#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos)))
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#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */
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#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */
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#define ADC_MR_PRESCAL_Pos 8
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#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */
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#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos)))
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#define ADC_MR_STARTUP_Pos 16
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#define ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */
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#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos)))
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#define ADC_MR_SHTIM_Pos 24
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#define ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) /**< \brief (ADC_MR) Sample & Hold Time */
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#define ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos)))
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/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */
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#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */
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#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */
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#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */
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#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */
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#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */
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#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */
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#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */
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#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */
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/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */
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#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */
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#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */
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#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */
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#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */
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#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */
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#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */
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#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */
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#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */
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/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */
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#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */
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#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */
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#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */
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#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */
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#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */
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#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */
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#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */
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#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */
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/* -------- ADC_SR : (ADC Offset: 0x1C) Status Register -------- */
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#define ADC_SR_EOC0 (0x1u << 0) /**< \brief (ADC_SR) End of Conversion 0 */
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#define ADC_SR_EOC1 (0x1u << 1) /**< \brief (ADC_SR) End of Conversion 1 */
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#define ADC_SR_EOC2 (0x1u << 2) /**< \brief (ADC_SR) End of Conversion 2 */
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#define ADC_SR_EOC3 (0x1u << 3) /**< \brief (ADC_SR) End of Conversion 3 */
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#define ADC_SR_EOC4 (0x1u << 4) /**< \brief (ADC_SR) End of Conversion 4 */
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#define ADC_SR_EOC5 (0x1u << 5) /**< \brief (ADC_SR) End of Conversion 5 */
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#define ADC_SR_EOC6 (0x1u << 6) /**< \brief (ADC_SR) End of Conversion 6 */
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#define ADC_SR_EOC7 (0x1u << 7) /**< \brief (ADC_SR) End of Conversion 7 */
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#define ADC_SR_OVRE0 (0x1u << 8) /**< \brief (ADC_SR) Overrun Error 0 */
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#define ADC_SR_OVRE1 (0x1u << 9) /**< \brief (ADC_SR) Overrun Error 1 */
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#define ADC_SR_OVRE2 (0x1u << 10) /**< \brief (ADC_SR) Overrun Error 2 */
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#define ADC_SR_OVRE3 (0x1u << 11) /**< \brief (ADC_SR) Overrun Error 3 */
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#define ADC_SR_OVRE4 (0x1u << 12) /**< \brief (ADC_SR) Overrun Error 4 */
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#define ADC_SR_OVRE5 (0x1u << 13) /**< \brief (ADC_SR) Overrun Error 5 */
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#define ADC_SR_OVRE6 (0x1u << 14) /**< \brief (ADC_SR) Overrun Error 6 */
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#define ADC_SR_OVRE7 (0x1u << 15) /**< \brief (ADC_SR) Overrun Error 7 */
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#define ADC_SR_DRDY (0x1u << 16) /**< \brief (ADC_SR) Data Ready */
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#define ADC_SR_GOVRE (0x1u << 17) /**< \brief (ADC_SR) General Overrun Error */
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#define ADC_SR_ENDRX (0x1u << 18) /**< \brief (ADC_SR) End of RX Buffer */
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#define ADC_SR_RXBUFF (0x1u << 19) /**< \brief (ADC_SR) RX Buffer Full */
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/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */
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#define ADC_LCDR_LDATA_Pos 0
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#define ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */
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/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */
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#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */
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#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */
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#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */
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#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */
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#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */
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#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */
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#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */
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#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */
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#define ADC_IER_OVRE0 (0x1u << 8) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 0 */
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#define ADC_IER_OVRE1 (0x1u << 9) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 1 */
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#define ADC_IER_OVRE2 (0x1u << 10) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 2 */
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#define ADC_IER_OVRE3 (0x1u << 11) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 3 */
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#define ADC_IER_OVRE4 (0x1u << 12) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 4 */
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#define ADC_IER_OVRE5 (0x1u << 13) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 5 */
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#define ADC_IER_OVRE6 (0x1u << 14) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 6 */
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#define ADC_IER_OVRE7 (0x1u << 15) /**< \brief (ADC_IER) Overrun Error Interrupt Enable 7 */
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#define ADC_IER_DRDY (0x1u << 16) /**< \brief (ADC_IER) Data Ready Interrupt Enable */
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#define ADC_IER_GOVRE (0x1u << 17) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */
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#define ADC_IER_ENDRX (0x1u << 18) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */
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#define ADC_IER_RXBUFF (0x1u << 19) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */
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/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */
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#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */
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#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */
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#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */
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#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */
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#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */
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#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */
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#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */
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#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */
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#define ADC_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 0 */
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#define ADC_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 1 */
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#define ADC_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 2 */
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#define ADC_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 3 */
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#define ADC_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 4 */
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#define ADC_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 5 */
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#define ADC_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 6 */
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#define ADC_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC_IDR) Overrun Error Interrupt Disable 7 */
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#define ADC_IDR_DRDY (0x1u << 16) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */
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#define ADC_IDR_GOVRE (0x1u << 17) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */
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#define ADC_IDR_ENDRX (0x1u << 18) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */
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#define ADC_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */
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/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */
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#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */
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#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */
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#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */
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#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */
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#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */
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#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */
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#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */
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#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */
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#define ADC_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 0 */
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#define ADC_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 1 */
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#define ADC_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 2 */
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#define ADC_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 3 */
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#define ADC_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 4 */
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#define ADC_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 5 */
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#define ADC_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 6 */
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#define ADC_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC_IMR) Overrun Error Interrupt Mask 7 */
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#define ADC_IMR_DRDY (0x1u << 16) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */
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#define ADC_IMR_GOVRE (0x1u << 17) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */
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#define ADC_IMR_ENDRX (0x1u << 18) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */
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#define ADC_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */
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/* -------- ADC_CDR[8] : (ADC Offset: 0x30) Channel Data Register -------- */
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#define ADC_CDR_DATA_Pos 0
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#define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[8]) Converted Data */
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/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */
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#define ADC_RPR_RXPTR_Pos 0
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#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */
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#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos)))
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/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */
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#define ADC_RCR_RXCTR_Pos 0
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#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */
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#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos)))
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/* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */
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#define ADC_TPR_TXPTR_Pos 0
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#define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /**< \brief (ADC_TPR) Transmit Counter Register */
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#define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos)))
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/* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */
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#define ADC_TCR_TXCTR_Pos 0
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#define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /**< \brief (ADC_TCR) Transmit Counter Register */
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#define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos)))
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/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */
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#define ADC_RNPR_RXNPTR_Pos 0
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#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */
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#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos)))
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/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */
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#define ADC_RNCR_RXNCTR_Pos 0
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#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */
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#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos)))
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/* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */
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#define ADC_TNPR_TXNPTR_Pos 0
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#define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /**< \brief (ADC_TNPR) Transmit Next Pointer */
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#define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos)))
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/* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */
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#define ADC_TNCR_TXNCTR_Pos 0
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#define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /**< \brief (ADC_TNCR) Transmit Counter Next */
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#define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos)))
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/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */
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#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */
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#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */
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#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */
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#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */
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/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */
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#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */
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#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */
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/*@}*/
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#endif /* _SAM3U_ADC_COMPONENT_ */
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@ -0,0 +1,237 @@
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/* %ATMEL_LICENCE% */
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#ifndef _SAM3U_ADC12B_COMPONENT_
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#define _SAM3U_ADC12B_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Analog-to-Digital-Converter 12bits */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_ADC12B Analog-to-Digital-Converter 12bits */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Adc12b hardware registers */
|
||||
typedef struct {
|
||||
WoReg ADC12B_CR; /**< \brief (Adc12b Offset: 0x00) Control Register */
|
||||
RwReg ADC12B_MR; /**< \brief (Adc12b Offset: 0x04) Mode Register */
|
||||
RoReg Reserved1[2];
|
||||
WoReg ADC12B_CHER; /**< \brief (Adc12b Offset: 0x10) Channel Enable Register */
|
||||
WoReg ADC12B_CHDR; /**< \brief (Adc12b Offset: 0x14) Channel Disable Register */
|
||||
RoReg ADC12B_CHSR; /**< \brief (Adc12b Offset: 0x18) Channel Status Register */
|
||||
RoReg ADC12B_SR; /**< \brief (Adc12b Offset: 0x1C) Status Register */
|
||||
RoReg ADC12B_LCDR; /**< \brief (Adc12b Offset: 0x20) Last Converted Data Register */
|
||||
WoReg ADC12B_IER; /**< \brief (Adc12b Offset: 0x24) Interrupt Enable Register */
|
||||
WoReg ADC12B_IDR; /**< \brief (Adc12b Offset: 0x28) Interrupt Disable Register */
|
||||
RoReg ADC12B_IMR; /**< \brief (Adc12b Offset: 0x2C) Interrupt Mask Register */
|
||||
RoReg ADC12B_CDR[8]; /**< \brief (Adc12b Offset: 0x30) Channel Data Register */
|
||||
RoReg Reserved2[5];
|
||||
RwReg ADC12B_ACR; /**< \brief (Adc12b Offset: 0x64) Analog Control Register */
|
||||
RwReg ADC12B_EMR; /**< \brief (Adc12b Offset: 0x68) Extended Mode Register */
|
||||
RoReg Reserved3[37];
|
||||
RwReg ADC12B_RPR; /**< \brief (Adc12b Offset: 0x100) Receive Pointer Register */
|
||||
RwReg ADC12B_RCR; /**< \brief (Adc12b Offset: 0x104) Receive Counter Register */
|
||||
RwReg ADC12B_TPR; /**< \brief (Adc12b Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg ADC12B_TCR; /**< \brief (Adc12b Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg ADC12B_RNPR; /**< \brief (Adc12b Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg ADC12B_RNCR; /**< \brief (Adc12b Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg ADC12B_TNPR; /**< \brief (Adc12b Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg ADC12B_TNCR; /**< \brief (Adc12b Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg ADC12B_PTCR; /**< \brief (Adc12b Offset: 0x120) Transfer Control Register */
|
||||
RoReg ADC12B_PTSR; /**< \brief (Adc12b Offset: 0x124) Transfer Status Register */
|
||||
} Adc12b;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- ADC12B_CR : (ADC12B Offset: 0x00) Control Register -------- */
|
||||
#define ADC12B_CR_SWRST (0x1u << 0) /**< \brief (ADC12B_CR) Software Reset */
|
||||
#define ADC12B_CR_START (0x1u << 1) /**< \brief (ADC12B_CR) Start Conversion */
|
||||
/* -------- ADC12B_MR : (ADC12B Offset: 0x04) Mode Register -------- */
|
||||
#define ADC12B_MR_TRGEN (0x1u << 0) /**< \brief (ADC12B_MR) Trigger Enable */
|
||||
#define ADC12B_MR_TRGSEL_Pos 1
|
||||
#define ADC12B_MR_TRGSEL_Msk (0x7u << ADC12B_MR_TRGSEL_Pos) /**< \brief (ADC12B_MR) Trigger Selection */
|
||||
#define ADC12B_MR_TRGSEL(value) ((ADC12B_MR_TRGSEL_Msk & ((value) << ADC12B_MR_TRGSEL_Pos)))
|
||||
#define ADC12B_MR_LOWRES (0x1u << 4) /**< \brief (ADC12B_MR) Resolution */
|
||||
#define ADC12B_MR_SLEEP (0x1u << 5) /**< \brief (ADC12B_MR) Sleep Mode */
|
||||
#define ADC12B_MR_PRESCAL_Pos 8
|
||||
#define ADC12B_MR_PRESCAL_Msk (0xffu << ADC12B_MR_PRESCAL_Pos) /**< \brief (ADC12B_MR) Prescaler Rate Selection */
|
||||
#define ADC12B_MR_PRESCAL(value) ((ADC12B_MR_PRESCAL_Msk & ((value) << ADC12B_MR_PRESCAL_Pos)))
|
||||
#define ADC12B_MR_STARTUP_Pos 16
|
||||
#define ADC12B_MR_STARTUP_Msk (0xffu << ADC12B_MR_STARTUP_Pos) /**< \brief (ADC12B_MR) Start Up Time */
|
||||
#define ADC12B_MR_STARTUP(value) ((ADC12B_MR_STARTUP_Msk & ((value) << ADC12B_MR_STARTUP_Pos)))
|
||||
#define ADC12B_MR_SHTIM_Pos 24
|
||||
#define ADC12B_MR_SHTIM_Msk (0xfu << ADC12B_MR_SHTIM_Pos) /**< \brief (ADC12B_MR) Sample & Hold Time */
|
||||
#define ADC12B_MR_SHTIM(value) ((ADC12B_MR_SHTIM_Msk & ((value) << ADC12B_MR_SHTIM_Pos)))
|
||||
/* -------- ADC12B_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- */
|
||||
#define ADC12B_CHER_CH0 (0x1u << 0) /**< \brief (ADC12B_CHER) Channel 0 Enable */
|
||||
#define ADC12B_CHER_CH1 (0x1u << 1) /**< \brief (ADC12B_CHER) Channel 1 Enable */
|
||||
#define ADC12B_CHER_CH2 (0x1u << 2) /**< \brief (ADC12B_CHER) Channel 2 Enable */
|
||||
#define ADC12B_CHER_CH3 (0x1u << 3) /**< \brief (ADC12B_CHER) Channel 3 Enable */
|
||||
#define ADC12B_CHER_CH4 (0x1u << 4) /**< \brief (ADC12B_CHER) Channel 4 Enable */
|
||||
#define ADC12B_CHER_CH5 (0x1u << 5) /**< \brief (ADC12B_CHER) Channel 5 Enable */
|
||||
#define ADC12B_CHER_CH6 (0x1u << 6) /**< \brief (ADC12B_CHER) Channel 6 Enable */
|
||||
#define ADC12B_CHER_CH7 (0x1u << 7) /**< \brief (ADC12B_CHER) Channel 7 Enable */
|
||||
/* -------- ADC12B_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- */
|
||||
#define ADC12B_CHDR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHDR) */
|
||||
#define ADC12B_CHDR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHDR) */
|
||||
/* -------- ADC12B_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- */
|
||||
#define ADC12B_CHSR_CH0 (0x1u << 0) /**< \brief (ADC12B_CHSR) Channel 0 Status */
|
||||
#define ADC12B_CHSR_CH1 (0x1u << 1) /**< \brief (ADC12B_CHSR) Channel 1 Status */
|
||||
#define ADC12B_CHSR_CH2 (0x1u << 2) /**< \brief (ADC12B_CHSR) Channel 2 Status */
|
||||
#define ADC12B_CHSR_CH3 (0x1u << 3) /**< \brief (ADC12B_CHSR) Channel 3 Status */
|
||||
#define ADC12B_CHSR_CH4 (0x1u << 4) /**< \brief (ADC12B_CHSR) Channel 4 Status */
|
||||
#define ADC12B_CHSR_CH5 (0x1u << 5) /**< \brief (ADC12B_CHSR) Channel 5 Status */
|
||||
#define ADC12B_CHSR_CH6 (0x1u << 6) /**< \brief (ADC12B_CHSR) Channel 6 Status */
|
||||
#define ADC12B_CHSR_CH7 (0x1u << 7) /**< \brief (ADC12B_CHSR) Channel 7 Status */
|
||||
/* -------- ADC12B_SR : (ADC12B Offset: 0x1C) Status Register -------- */
|
||||
#define ADC12B_SR_EOC0 (0x1u << 0) /**< \brief (ADC12B_SR) End of Conversion 0 */
|
||||
#define ADC12B_SR_EOC1 (0x1u << 1) /**< \brief (ADC12B_SR) End of Conversion 1 */
|
||||
#define ADC12B_SR_EOC2 (0x1u << 2) /**< \brief (ADC12B_SR) End of Conversion 2 */
|
||||
#define ADC12B_SR_EOC3 (0x1u << 3) /**< \brief (ADC12B_SR) End of Conversion 3 */
|
||||
#define ADC12B_SR_EOC4 (0x1u << 4) /**< \brief (ADC12B_SR) End of Conversion 4 */
|
||||
#define ADC12B_SR_EOC5 (0x1u << 5) /**< \brief (ADC12B_SR) End of Conversion 5 */
|
||||
#define ADC12B_SR_EOC6 (0x1u << 6) /**< \brief (ADC12B_SR) End of Conversion 6 */
|
||||
#define ADC12B_SR_EOC7 (0x1u << 7) /**< \brief (ADC12B_SR) End of Conversion 7 */
|
||||
#define ADC12B_SR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_SR) Overrun Error 0 */
|
||||
#define ADC12B_SR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_SR) Overrun Error 1 */
|
||||
#define ADC12B_SR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_SR) Overrun Error 2 */
|
||||
#define ADC12B_SR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_SR) Overrun Error 3 */
|
||||
#define ADC12B_SR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_SR) Overrun Error 4 */
|
||||
#define ADC12B_SR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_SR) Overrun Error 5 */
|
||||
#define ADC12B_SR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_SR) Overrun Error 6 */
|
||||
#define ADC12B_SR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_SR) Overrun Error 7 */
|
||||
#define ADC12B_SR_DRDY (0x1u << 16) /**< \brief (ADC12B_SR) Data Ready */
|
||||
#define ADC12B_SR_GOVRE (0x1u << 17) /**< \brief (ADC12B_SR) General Overrun Error */
|
||||
#define ADC12B_SR_ENDRX (0x1u << 18) /**< \brief (ADC12B_SR) End of RX Buffer */
|
||||
#define ADC12B_SR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_SR) RX Buffer Full */
|
||||
/* -------- ADC12B_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- */
|
||||
#define ADC12B_LCDR_LDATA_Pos 0
|
||||
#define ADC12B_LCDR_LDATA_Msk (0xfffu << ADC12B_LCDR_LDATA_Pos) /**< \brief (ADC12B_LCDR) Last Data Converted */
|
||||
/* -------- ADC12B_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- */
|
||||
#define ADC12B_IER_EOC0 (0x1u << 0) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 0 */
|
||||
#define ADC12B_IER_EOC1 (0x1u << 1) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 1 */
|
||||
#define ADC12B_IER_EOC2 (0x1u << 2) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 2 */
|
||||
#define ADC12B_IER_EOC3 (0x1u << 3) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 3 */
|
||||
#define ADC12B_IER_EOC4 (0x1u << 4) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 4 */
|
||||
#define ADC12B_IER_EOC5 (0x1u << 5) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 5 */
|
||||
#define ADC12B_IER_EOC6 (0x1u << 6) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 6 */
|
||||
#define ADC12B_IER_EOC7 (0x1u << 7) /**< \brief (ADC12B_IER) End of Conversion Interrupt Enable 7 */
|
||||
#define ADC12B_IER_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 0 */
|
||||
#define ADC12B_IER_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 1 */
|
||||
#define ADC12B_IER_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 2 */
|
||||
#define ADC12B_IER_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 3 */
|
||||
#define ADC12B_IER_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 4 */
|
||||
#define ADC12B_IER_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 5 */
|
||||
#define ADC12B_IER_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 6 */
|
||||
#define ADC12B_IER_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IER) Overrun Error Interrupt Enable 7 */
|
||||
#define ADC12B_IER_DRDY (0x1u << 16) /**< \brief (ADC12B_IER) Data Ready Interrupt Enable */
|
||||
#define ADC12B_IER_GOVRE (0x1u << 17) /**< \brief (ADC12B_IER) General Overrun Error Interrupt Enable */
|
||||
#define ADC12B_IER_ENDRX (0x1u << 18) /**< \brief (ADC12B_IER) End of Receive Buffer Interrupt Enable */
|
||||
#define ADC12B_IER_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IER) Receive Buffer Full Interrupt Enable */
|
||||
/* -------- ADC12B_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- */
|
||||
#define ADC12B_IDR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 0 */
|
||||
#define ADC12B_IDR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 1 */
|
||||
#define ADC12B_IDR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 2 */
|
||||
#define ADC12B_IDR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 3 */
|
||||
#define ADC12B_IDR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 4 */
|
||||
#define ADC12B_IDR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 5 */
|
||||
#define ADC12B_IDR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 6 */
|
||||
#define ADC12B_IDR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IDR) End of Conversion Interrupt Disable 7 */
|
||||
#define ADC12B_IDR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 0 */
|
||||
#define ADC12B_IDR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 1 */
|
||||
#define ADC12B_IDR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 2 */
|
||||
#define ADC12B_IDR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 3 */
|
||||
#define ADC12B_IDR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 4 */
|
||||
#define ADC12B_IDR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 5 */
|
||||
#define ADC12B_IDR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 6 */
|
||||
#define ADC12B_IDR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IDR) Overrun Error Interrupt Disable 7 */
|
||||
#define ADC12B_IDR_DRDY (0x1u << 16) /**< \brief (ADC12B_IDR) Data Ready Interrupt Disable */
|
||||
#define ADC12B_IDR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IDR) General Overrun Error Interrupt Disable */
|
||||
#define ADC12B_IDR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IDR) End of Receive Buffer Interrupt Disable */
|
||||
#define ADC12B_IDR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IDR) Receive Buffer Full Interrupt Disable */
|
||||
/* -------- ADC12B_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- */
|
||||
#define ADC12B_IMR_EOC0 (0x1u << 0) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 0 */
|
||||
#define ADC12B_IMR_EOC1 (0x1u << 1) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 1 */
|
||||
#define ADC12B_IMR_EOC2 (0x1u << 2) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 2 */
|
||||
#define ADC12B_IMR_EOC3 (0x1u << 3) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 3 */
|
||||
#define ADC12B_IMR_EOC4 (0x1u << 4) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 4 */
|
||||
#define ADC12B_IMR_EOC5 (0x1u << 5) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 5 */
|
||||
#define ADC12B_IMR_EOC6 (0x1u << 6) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 6 */
|
||||
#define ADC12B_IMR_EOC7 (0x1u << 7) /**< \brief (ADC12B_IMR) End of Conversion Interrupt Mask 7 */
|
||||
#define ADC12B_IMR_OVRE0 (0x1u << 8) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 0 */
|
||||
#define ADC12B_IMR_OVRE1 (0x1u << 9) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 1 */
|
||||
#define ADC12B_IMR_OVRE2 (0x1u << 10) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 2 */
|
||||
#define ADC12B_IMR_OVRE3 (0x1u << 11) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 3 */
|
||||
#define ADC12B_IMR_OVRE4 (0x1u << 12) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 4 */
|
||||
#define ADC12B_IMR_OVRE5 (0x1u << 13) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 5 */
|
||||
#define ADC12B_IMR_OVRE6 (0x1u << 14) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 6 */
|
||||
#define ADC12B_IMR_OVRE7 (0x1u << 15) /**< \brief (ADC12B_IMR) Overrun Error Interrupt Mask 7 */
|
||||
#define ADC12B_IMR_DRDY (0x1u << 16) /**< \brief (ADC12B_IMR) Data Ready Interrupt Mask */
|
||||
#define ADC12B_IMR_GOVRE (0x1u << 17) /**< \brief (ADC12B_IMR) General Overrun Error Interrupt Mask */
|
||||
#define ADC12B_IMR_ENDRX (0x1u << 18) /**< \brief (ADC12B_IMR) End of Receive Buffer Interrupt Mask */
|
||||
#define ADC12B_IMR_RXBUFF (0x1u << 19) /**< \brief (ADC12B_IMR) Receive Buffer Full Interrupt Mask */
|
||||
/* -------- ADC12B_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- */
|
||||
#define ADC12B_CDR_DATA_Pos 0
|
||||
#define ADC12B_CDR_DATA_Msk (0xfffu << ADC12B_CDR_DATA_Pos) /**< \brief (ADC12B_CDR[8]) Converted Data */
|
||||
/* -------- ADC12B_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- */
|
||||
#define ADC12B_ACR_GAIN_Pos 0
|
||||
#define ADC12B_ACR_GAIN_Msk (0x3u << ADC12B_ACR_GAIN_Pos) /**< \brief (ADC12B_ACR) Input Gain */
|
||||
#define ADC12B_ACR_GAIN(value) ((ADC12B_ACR_GAIN_Msk & ((value) << ADC12B_ACR_GAIN_Pos)))
|
||||
#define ADC12B_ACR_IBCTL_Pos 8
|
||||
#define ADC12B_ACR_IBCTL_Msk (0x3u << ADC12B_ACR_IBCTL_Pos) /**< \brief (ADC12B_ACR) Bias Current Control */
|
||||
#define ADC12B_ACR_IBCTL(value) ((ADC12B_ACR_IBCTL_Msk & ((value) << ADC12B_ACR_IBCTL_Pos)))
|
||||
#define ADC12B_ACR_DIFF (0x1u << 16) /**< \brief (ADC12B_ACR) Differential Mode */
|
||||
#define ADC12B_ACR_OFFSET (0x1u << 17) /**< \brief (ADC12B_ACR) Input OFFSET */
|
||||
/* -------- ADC12B_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- */
|
||||
#define ADC12B_EMR_OFFMODES (0x1u << 0) /**< \brief (ADC12B_EMR) Off Mode if Sleep Bit (ADC12B_MR) = 1 */
|
||||
#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos 16
|
||||
#define ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk (0xffu << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos) /**< \brief (ADC12B_EMR) Startup Time */
|
||||
#define ADC12B_EMR_OFF_MODE_STARTUP_TIME(value) ((ADC12B_EMR_OFF_MODE_STARTUP_TIME_Msk & ((value) << ADC12B_EMR_OFF_MODE_STARTUP_TIME_Pos)))
|
||||
/* -------- ADC12B_RPR : (ADC12B Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define ADC12B_RPR_RXPTR_Pos 0
|
||||
#define ADC12B_RPR_RXPTR_Msk (0xffffffffu << ADC12B_RPR_RXPTR_Pos) /**< \brief (ADC12B_RPR) Receive Pointer Register */
|
||||
#define ADC12B_RPR_RXPTR(value) ((ADC12B_RPR_RXPTR_Msk & ((value) << ADC12B_RPR_RXPTR_Pos)))
|
||||
/* -------- ADC12B_RCR : (ADC12B Offset: 0x104) Receive Counter Register -------- */
|
||||
#define ADC12B_RCR_RXCTR_Pos 0
|
||||
#define ADC12B_RCR_RXCTR_Msk (0xffffu << ADC12B_RCR_RXCTR_Pos) /**< \brief (ADC12B_RCR) Receive Counter Register */
|
||||
#define ADC12B_RCR_RXCTR(value) ((ADC12B_RCR_RXCTR_Msk & ((value) << ADC12B_RCR_RXCTR_Pos)))
|
||||
/* -------- ADC12B_TPR : (ADC12B Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define ADC12B_TPR_TXPTR_Pos 0
|
||||
#define ADC12B_TPR_TXPTR_Msk (0xffffffffu << ADC12B_TPR_TXPTR_Pos) /**< \brief (ADC12B_TPR) Transmit Counter Register */
|
||||
#define ADC12B_TPR_TXPTR(value) ((ADC12B_TPR_TXPTR_Msk & ((value) << ADC12B_TPR_TXPTR_Pos)))
|
||||
/* -------- ADC12B_TCR : (ADC12B Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define ADC12B_TCR_TXCTR_Pos 0
|
||||
#define ADC12B_TCR_TXCTR_Msk (0xffffu << ADC12B_TCR_TXCTR_Pos) /**< \brief (ADC12B_TCR) Transmit Counter Register */
|
||||
#define ADC12B_TCR_TXCTR(value) ((ADC12B_TCR_TXCTR_Msk & ((value) << ADC12B_TCR_TXCTR_Pos)))
|
||||
/* -------- ADC12B_RNPR : (ADC12B Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define ADC12B_RNPR_RXNPTR_Pos 0
|
||||
#define ADC12B_RNPR_RXNPTR_Msk (0xffffffffu << ADC12B_RNPR_RXNPTR_Pos) /**< \brief (ADC12B_RNPR) Receive Next Pointer */
|
||||
#define ADC12B_RNPR_RXNPTR(value) ((ADC12B_RNPR_RXNPTR_Msk & ((value) << ADC12B_RNPR_RXNPTR_Pos)))
|
||||
/* -------- ADC12B_RNCR : (ADC12B Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define ADC12B_RNCR_RXNCTR_Pos 0
|
||||
#define ADC12B_RNCR_RXNCTR_Msk (0xffffu << ADC12B_RNCR_RXNCTR_Pos) /**< \brief (ADC12B_RNCR) Receive Next Counter */
|
||||
#define ADC12B_RNCR_RXNCTR(value) ((ADC12B_RNCR_RXNCTR_Msk & ((value) << ADC12B_RNCR_RXNCTR_Pos)))
|
||||
/* -------- ADC12B_TNPR : (ADC12B Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define ADC12B_TNPR_TXNPTR_Pos 0
|
||||
#define ADC12B_TNPR_TXNPTR_Msk (0xffffffffu << ADC12B_TNPR_TXNPTR_Pos) /**< \brief (ADC12B_TNPR) Transmit Next Pointer */
|
||||
#define ADC12B_TNPR_TXNPTR(value) ((ADC12B_TNPR_TXNPTR_Msk & ((value) << ADC12B_TNPR_TXNPTR_Pos)))
|
||||
/* -------- ADC12B_TNCR : (ADC12B Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define ADC12B_TNCR_TXNCTR_Pos 0
|
||||
#define ADC12B_TNCR_TXNCTR_Msk (0xffffu << ADC12B_TNCR_TXNCTR_Pos) /**< \brief (ADC12B_TNCR) Transmit Counter Next */
|
||||
#define ADC12B_TNCR_TXNCTR(value) ((ADC12B_TNCR_TXNCTR_Msk & ((value) << ADC12B_TNCR_TXNCTR_Pos)))
|
||||
/* -------- ADC12B_PTCR : (ADC12B Offset: 0x120) Transfer Control Register -------- */
|
||||
#define ADC12B_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTCR) Receiver Transfer Enable */
|
||||
#define ADC12B_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC12B_PTCR) Receiver Transfer Disable */
|
||||
#define ADC12B_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTCR) Transmitter Transfer Enable */
|
||||
#define ADC12B_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC12B_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- ADC12B_PTSR : (ADC12B Offset: 0x124) Transfer Status Register -------- */
|
||||
#define ADC12B_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC12B_PTSR) Receiver Transfer Enable */
|
||||
#define ADC12B_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC12B_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_ADC12B_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_CHIPID_COMPONENT_
|
||||
#define _SAM3U_CHIPID_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Chip Identifier */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_CHIPID Chip Identifier */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Chipid hardware registers */
|
||||
typedef struct {
|
||||
RoReg CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */
|
||||
RoReg CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */
|
||||
} Chipid;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */
|
||||
#define CHIPID_CIDR_VERSION_Pos 0
|
||||
#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */
|
||||
#define CHIPID_CIDR_EPROC_Pos 5
|
||||
#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */
|
||||
#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */
|
||||
#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */
|
||||
#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */
|
||||
#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */
|
||||
#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */
|
||||
#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */
|
||||
#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */
|
||||
#define CHIPID_CIDR_NVPSIZ_Pos 8
|
||||
#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */
|
||||
#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */
|
||||
#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_Pos 12
|
||||
#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */
|
||||
#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */
|
||||
#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_Pos 16
|
||||
#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */
|
||||
#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */
|
||||
#define CHIPID_CIDR_ARCH_Pos 20
|
||||
#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */
|
||||
#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */
|
||||
#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */
|
||||
#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */
|
||||
#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */
|
||||
#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */
|
||||
#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */
|
||||
#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */
|
||||
#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */
|
||||
#define CHIPID_CIDR_NVPTYP_Pos 28
|
||||
#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */
|
||||
#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */
|
||||
#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */
|
||||
#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */
|
||||
#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */
|
||||
/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */
|
||||
#define CHIPID_EXID_EXID_Pos 0
|
||||
#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_CHIPID_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_DMAC_COMPONENT_
|
||||
#define _SAM3U_DMAC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR DMA Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_DMAC DMA Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief DmacCh_num hardware registers */
|
||||
typedef struct {
|
||||
RwReg DMAC_SADDR; /**< \brief (DmacCh_num Offset: 0x0) DMAC Channel Source Address Register */
|
||||
RwReg DMAC_DADDR; /**< \brief (DmacCh_num Offset: 0x4) DMAC Channel Destination Address Register */
|
||||
RwReg DMAC_DSCR; /**< \brief (DmacCh_num Offset: 0x8) DMAC Channel Descriptor Address Register */
|
||||
RwReg DMAC_CTRLA; /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
|
||||
RwReg DMAC_CTRLB; /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
|
||||
RwReg DMAC_CFG; /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
|
||||
RwReg DMAC_SPIP; /**< \brief (DmacCh_num Offset: 0x18) DMAC Channel Source Picture in Picture Configuration Register */
|
||||
RwReg DMAC_DPIP; /**< \brief (DmacCh_num Offset: 0x1C) DMAC Channel Destination Picture in Picture Configuration Register */
|
||||
RoReg Reserved1[2];
|
||||
} DmacCh_num;
|
||||
/** \brief Dmac hardware registers */
|
||||
#define DMACCH_NUM_NUMBER 4
|
||||
typedef struct {
|
||||
RwReg DMAC_GCFG; /**< \brief (Dmac Offset: 0x000) DMAC Global Configuration Register */
|
||||
RwReg DMAC_EN; /**< \brief (Dmac Offset: 0x004) DMAC Enable Register */
|
||||
RwReg DMAC_SREQ; /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
|
||||
RwReg DMAC_CREQ; /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
|
||||
RwReg DMAC_LAST; /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
|
||||
RwReg DMAC_SYNC; /**< \brief (Dmac Offset: 0x014) DMAC Request Synchronization Register */
|
||||
WoReg DMAC_EBCIER; /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
|
||||
WoReg DMAC_EBCIDR; /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
|
||||
RoReg DMAC_EBCIMR; /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
|
||||
RoReg DMAC_EBCISR; /**< \brief (Dmac Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
|
||||
WoReg DMAC_CHER; /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
|
||||
WoReg DMAC_CHDR; /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
|
||||
RoReg DMAC_CHSR; /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
|
||||
RoReg Reserved1[2];
|
||||
DmacCh_num DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
|
||||
} Dmac;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
|
||||
#define DMAC_GCFG_IF0_BIGEND (0x1u << 0) /**< \brief (DMAC_GCFG) */
|
||||
#define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG) */
|
||||
/* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
|
||||
#define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN) */
|
||||
/* -------- DMAC_SREQ : (DMAC Offset: 0x008) DMAC Software Single Request Register -------- */
|
||||
#define DMAC_SREQ_SSREQ0 (0x1u << 0) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ) */
|
||||
#define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ) */
|
||||
/* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
|
||||
#define DMAC_CREQ_SCREQ0 (0x1u << 0) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ) */
|
||||
#define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ) */
|
||||
/* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
|
||||
#define DMAC_LAST_SLAST0 (0x1u << 0) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_DLAST0 (0x1u << 1) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_SLAST1 (0x1u << 2) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_DLAST1 (0x1u << 3) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_SLAST2 (0x1u << 4) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST) */
|
||||
#define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST) */
|
||||
/* -------- DMAC_SYNC : (DMAC Offset: 0x014) DMAC Request Synchronization Register -------- */
|
||||
#define DMAC_SYNC_SYR0 (0x1u << 0) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR1 (0x1u << 1) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR2 (0x1u << 2) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR3 (0x1u << 3) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR4 (0x1u << 4) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR5 (0x1u << 5) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR6 (0x1u << 6) /**< \brief (DMAC_SYNC) */
|
||||
#define DMAC_SYNC_SYR7 (0x1u << 7) /**< \brief (DMAC_SYNC) */
|
||||
/* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */
|
||||
#define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIER) */
|
||||
#define DMAC_EBCIER_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIER) */
|
||||
/* -------- DMAC_EBCIDR : (DMAC Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. -------- */
|
||||
#define DMAC_EBCIDR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIDR) */
|
||||
#define DMAC_EBCIDR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIDR) */
|
||||
/* -------- DMAC_EBCIMR : (DMAC Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. -------- */
|
||||
#define DMAC_EBCIMR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCIMR) */
|
||||
#define DMAC_EBCIMR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCIMR) */
|
||||
/* -------- DMAC_EBCISR : (DMAC Offset: 0x024) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. -------- */
|
||||
#define DMAC_EBCISR_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_BTC2 (0x1u << 2) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_BTC3 (0x1u << 3) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_CBTC0 (0x1u << 8) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_CBTC1 (0x1u << 9) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_CBTC2 (0x1u << 10) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_CBTC3 (0x1u << 11) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_ERR0 (0x1u << 16) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_ERR1 (0x1u << 17) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_ERR2 (0x1u << 18) /**< \brief (DMAC_EBCISR) */
|
||||
#define DMAC_EBCISR_ERR3 (0x1u << 19) /**< \brief (DMAC_EBCISR) */
|
||||
/* -------- DMAC_CHER : (DMAC Offset: 0x028) DMAC Channel Handler Enable Register -------- */
|
||||
#define DMAC_CHER_ENA0 (0x1u << 0) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_ENA1 (0x1u << 1) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_ENA2 (0x1u << 2) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_ENA3 (0x1u << 3) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_KEEP0 (0x1u << 24) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_KEEP1 (0x1u << 25) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_KEEP2 (0x1u << 26) /**< \brief (DMAC_CHER) */
|
||||
#define DMAC_CHER_KEEP3 (0x1u << 27) /**< \brief (DMAC_CHER) */
|
||||
/* -------- DMAC_CHDR : (DMAC Offset: 0x02C) DMAC Channel Handler Disable Register -------- */
|
||||
#define DMAC_CHDR_DIS0 (0x1u << 0) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_DIS1 (0x1u << 1) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_DIS2 (0x1u << 2) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_DIS3 (0x1u << 3) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_RES0 (0x1u << 8) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_RES1 (0x1u << 9) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_RES2 (0x1u << 10) /**< \brief (DMAC_CHDR) */
|
||||
#define DMAC_CHDR_RES3 (0x1u << 11) /**< \brief (DMAC_CHDR) */
|
||||
/* -------- DMAC_CHSR : (DMAC Offset: 0x030) DMAC Channel Handler Status Register -------- */
|
||||
#define DMAC_CHSR_ENA0 (0x1u << 0) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_ENA1 (0x1u << 1) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_ENA2 (0x1u << 2) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_ENA3 (0x1u << 3) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_SUSP0 (0x1u << 8) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_SUSP1 (0x1u << 9) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_SUSP2 (0x1u << 10) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_SUSP3 (0x1u << 11) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_EMPT0 (0x1u << 16) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_EMPT1 (0x1u << 17) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_EMPT2 (0x1u << 18) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_EMPT3 (0x1u << 19) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_STAL0 (0x1u << 24) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_STAL1 (0x1u << 25) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_STAL2 (0x1u << 26) /**< \brief (DMAC_CHSR) */
|
||||
#define DMAC_CHSR_STAL3 (0x1u << 27) /**< \brief (DMAC_CHSR) */
|
||||
/* -------- DMAC_SADDR : (DMAC Offset: N/A) DMAC Channel Source Address Register -------- */
|
||||
#define DMAC_SADDR_SADDRx_Pos 0
|
||||
#define DMAC_SADDR_SADDRx_Msk (0xffffffffu << DMAC_SADDR_SADDRx_Pos) /**< \brief (DMAC_SADDR) */
|
||||
#define DMAC_SADDR_SADDRx(value) ((DMAC_SADDR_SADDRx_Msk & ((value) << DMAC_SADDR_SADDRx_Pos)))
|
||||
/* -------- DMAC_DADDR : (DMAC Offset: N/A) DMAC Channel Destination Address Register -------- */
|
||||
#define DMAC_DADDR_DADDRx_Pos 0
|
||||
#define DMAC_DADDR_DADDRx_Msk (0xffffffffu << DMAC_DADDR_DADDRx_Pos) /**< \brief (DMAC_DADDR) */
|
||||
#define DMAC_DADDR_DADDRx(value) ((DMAC_DADDR_DADDRx_Msk & ((value) << DMAC_DADDR_DADDRx_Pos)))
|
||||
/* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
|
||||
#define DMAC_DSCR_DSCRx_IF_Pos 0
|
||||
#define DMAC_DSCR_DSCRx_IF_Msk (0x3u << DMAC_DSCR_DSCRx_IF_Pos) /**< \brief (DMAC_DSCR) */
|
||||
#define DMAC_DSCR_DSCRx_IF(value) ((DMAC_DSCR_DSCRx_IF_Msk & ((value) << DMAC_DSCR_DSCRx_IF_Pos)))
|
||||
#define DMAC_DSCR_DSCRx_Pos 2
|
||||
#define DMAC_DSCR_DSCRx_Msk (0x3fffffffu << DMAC_DSCR_DSCRx_Pos) /**< \brief (DMAC_DSCR) */
|
||||
#define DMAC_DSCR_DSCRx(value) ((DMAC_DSCR_DSCRx_Msk & ((value) << DMAC_DSCR_DSCRx_Pos)))
|
||||
/* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
|
||||
#define DMAC_CTRLA_BTSIZE_Pos 0
|
||||
#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA) */
|
||||
#define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
|
||||
#define DMAC_CTRLA_SCSIZE_Pos 16
|
||||
#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA) */
|
||||
#define DMAC_CTRLA_SCSIZE(value) ((DMAC_CTRLA_SCSIZE_Msk & ((value) << DMAC_CTRLA_SCSIZE_Pos)))
|
||||
#define DMAC_CTRLA_DCSIZE_Pos 20
|
||||
#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA) */
|
||||
#define DMAC_CTRLA_DCSIZE(value) ((DMAC_CTRLA_DCSIZE_Msk & ((value) << DMAC_CTRLA_DCSIZE_Pos)))
|
||||
#define DMAC_CTRLA_SRC_WIDTH_Pos 24
|
||||
#define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA) */
|
||||
#define DMAC_CTRLA_SRC_WIDTH(value) ((DMAC_CTRLA_SRC_WIDTH_Msk & ((value) << DMAC_CTRLA_SRC_WIDTH_Pos)))
|
||||
#define DMAC_CTRLA_DST_WIDTH_Pos 28
|
||||
#define DMAC_CTRLA_DST_WIDTH_Msk (0x3u << DMAC_CTRLA_DST_WIDTH_Pos) /**< \brief (DMAC_CTRLA) */
|
||||
#define DMAC_CTRLA_DST_WIDTH(value) ((DMAC_CTRLA_DST_WIDTH_Msk & ((value) << DMAC_CTRLA_DST_WIDTH_Pos)))
|
||||
#define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA) */
|
||||
/* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
|
||||
#define DMAC_CTRLB_SIF_Pos 0
|
||||
#define DMAC_CTRLB_SIF_Msk (0x3u << DMAC_CTRLB_SIF_Pos) /**< \brief (DMAC_CTRLB) Source Interface Selection Field */
|
||||
#define DMAC_CTRLB_SIF(value) ((DMAC_CTRLB_SIF_Msk & ((value) << DMAC_CTRLB_SIF_Pos)))
|
||||
#define DMAC_CTRLB_DIF_Pos 4
|
||||
#define DMAC_CTRLB_DIF_Msk (0x3u << DMAC_CTRLB_DIF_Pos) /**< \brief (DMAC_CTRLB) Destination Interface Selection Field */
|
||||
#define DMAC_CTRLB_DIF(value) ((DMAC_CTRLB_DIF_Msk & ((value) << DMAC_CTRLB_DIF_Pos)))
|
||||
#define DMAC_CTRLB_SRC_PIP (0x1u << 8) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_DST_PIP (0x1u << 12) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_FC_Pos 21
|
||||
#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_FC(value) ((DMAC_CTRLB_FC_Msk & ((value) << DMAC_CTRLB_FC_Pos)))
|
||||
#define DMAC_CTRLB_SRC_INCR_Pos 24
|
||||
#define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_SRC_INCR(value) ((DMAC_CTRLB_SRC_INCR_Msk & ((value) << DMAC_CTRLB_SRC_INCR_Pos)))
|
||||
#define DMAC_CTRLB_DST_INCR_Pos 28
|
||||
#define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_DST_INCR(value) ((DMAC_CTRLB_DST_INCR_Msk & ((value) << DMAC_CTRLB_DST_INCR_Pos)))
|
||||
#define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB) */
|
||||
#define DMAC_CTRLB_AUTO (0x1u << 31) /**< \brief (DMAC_CTRLB) */
|
||||
/* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
|
||||
#define DMAC_CFG_SRC_PER_Pos 0
|
||||
#define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_SRC_PER(value) ((DMAC_CFG_SRC_PER_Msk & ((value) << DMAC_CFG_SRC_PER_Pos)))
|
||||
#define DMAC_CFG_DST_PER_Pos 4
|
||||
#define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
|
||||
#define DMAC_CFG_SRC_REP (0x1u << 8) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_DST_REP (0x1u << 12) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_LOCK_B (0x1u << 21) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_LOCK_IF_L (0x1u << 22) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_AHB_PROT_Pos 24
|
||||
#define DMAC_CFG_AHB_PROT_Msk (0x7u << DMAC_CFG_AHB_PROT_Pos) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_AHB_PROT(value) ((DMAC_CFG_AHB_PROT_Msk & ((value) << DMAC_CFG_AHB_PROT_Pos)))
|
||||
#define DMAC_CFG_FIFOCFG_Pos 28
|
||||
#define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG) */
|
||||
#define DMAC_CFG_FIFOCFG(value) ((DMAC_CFG_FIFOCFG_Msk & ((value) << DMAC_CFG_FIFOCFG_Pos)))
|
||||
/* -------- DMAC_SPIP : (DMAC Offset: N/A) DMAC Channel Source Picture in Picture Configuration Register -------- */
|
||||
#define DMAC_SPIP_SPIP_HOLE_Pos 0
|
||||
#define DMAC_SPIP_SPIP_HOLE_Msk (0xffffu << DMAC_SPIP_SPIP_HOLE_Pos) /**< \brief (DMAC_SPIP) */
|
||||
#define DMAC_SPIP_SPIP_HOLE(value) ((DMAC_SPIP_SPIP_HOLE_Msk & ((value) << DMAC_SPIP_SPIP_HOLE_Pos)))
|
||||
#define DMAC_SPIP_SPIP_BOUNDARY_Pos 16
|
||||
#define DMAC_SPIP_SPIP_BOUNDARY_Msk (0x3ffu << DMAC_SPIP_SPIP_BOUNDARY_Pos) /**< \brief (DMAC_SPIP) */
|
||||
#define DMAC_SPIP_SPIP_BOUNDARY(value) ((DMAC_SPIP_SPIP_BOUNDARY_Msk & ((value) << DMAC_SPIP_SPIP_BOUNDARY_Pos)))
|
||||
/* -------- DMAC_DPIP : (DMAC Offset: N/A) DMAC Channel Destination Picture in Picture Configuration Register -------- */
|
||||
#define DMAC_DPIP_DPIP_HOLE_Pos 0
|
||||
#define DMAC_DPIP_DPIP_HOLE_Msk (0xffffu << DMAC_DPIP_DPIP_HOLE_Pos) /**< \brief (DMAC_DPIP) */
|
||||
#define DMAC_DPIP_DPIP_HOLE(value) ((DMAC_DPIP_DPIP_HOLE_Msk & ((value) << DMAC_DPIP_DPIP_HOLE_Pos)))
|
||||
#define DMAC_DPIP_DPIP_BOUNDARY_Pos 16
|
||||
#define DMAC_DPIP_DPIP_BOUNDARY_Msk (0x3ffu << DMAC_DPIP_DPIP_BOUNDARY_Pos) /**< \brief (DMAC_DPIP) */
|
||||
#define DMAC_DPIP_DPIP_BOUNDARY(value) ((DMAC_DPIP_DPIP_BOUNDARY_Msk & ((value) << DMAC_DPIP_DPIP_BOUNDARY_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_DMAC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_EFC_COMPONENT_
|
||||
#define _SAM3U_EFC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_EFC Embedded Flash Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Efc hardware registers */
|
||||
typedef struct {
|
||||
RwReg EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */
|
||||
WoReg EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */
|
||||
RoReg EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */
|
||||
RoReg EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */
|
||||
} Efc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */
|
||||
#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */
|
||||
#define EEFC_FMR_FWS_Pos 8
|
||||
#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */
|
||||
#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)))
|
||||
#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */
|
||||
#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */
|
||||
/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */
|
||||
#define EEFC_FCR_FCMD_Pos 0
|
||||
#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */
|
||||
#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)))
|
||||
#define EEFC_FCR_FARG_Pos 8
|
||||
#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */
|
||||
#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)))
|
||||
#define EEFC_FCR_FKEY_Pos 24
|
||||
#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */
|
||||
#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)))
|
||||
/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */
|
||||
#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */
|
||||
#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */
|
||||
#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */
|
||||
/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */
|
||||
#define EEFC_FRR_FVALUE_Pos 0
|
||||
#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_EFC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_GPBR_COMPONENT_
|
||||
#define _SAM3U_GPBR_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_GPBR General Purpose Backup Register */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Gpbr hardware registers */
|
||||
typedef struct {
|
||||
RwReg SYS_GPBR[4]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */
|
||||
} Gpbr;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SYS_GPBR[4] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */
|
||||
#define SYS_GPBR_GPBR_VALUE_Pos 0
|
||||
#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[4]) Value of GPBR x */
|
||||
#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_GPBR_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,313 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_HSMCI_COMPONENT_
|
||||
#define _SAM3U_HSMCI_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_HSMCI High Speed MultiMedia Card Interface */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Hsmci hardware registers */
|
||||
typedef struct {
|
||||
WoReg HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */
|
||||
RwReg HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */
|
||||
RwReg HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */
|
||||
RwReg HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */
|
||||
RwReg HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */
|
||||
WoReg HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */
|
||||
RwReg HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */
|
||||
RwReg HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */
|
||||
RoReg HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */
|
||||
RoReg HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */
|
||||
WoReg HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */
|
||||
RoReg Reserved1[2];
|
||||
RoReg HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */
|
||||
WoReg HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */
|
||||
WoReg HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */
|
||||
RoReg HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */
|
||||
RwReg HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */
|
||||
RwReg HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */
|
||||
RoReg Reserved2[35];
|
||||
RwReg HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */
|
||||
RoReg HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */
|
||||
RoReg Reserved3[69];
|
||||
RwReg HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */
|
||||
} Hsmci;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */
|
||||
#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */
|
||||
#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */
|
||||
#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */
|
||||
#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */
|
||||
#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */
|
||||
/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */
|
||||
#define HSMCI_MR_CLKDIV_Pos 0
|
||||
#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */
|
||||
#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)))
|
||||
#define HSMCI_MR_PWSDIV_Pos 8
|
||||
#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */
|
||||
#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)))
|
||||
#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */
|
||||
#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */
|
||||
#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */
|
||||
#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */
|
||||
#define HSMCI_MR_BLKLEN_Pos 16
|
||||
#define HSMCI_MR_BLKLEN_Msk (0xffffu << HSMCI_MR_BLKLEN_Pos) /**< \brief (HSMCI_MR) Data Block Length */
|
||||
#define HSMCI_MR_BLKLEN(value) ((HSMCI_MR_BLKLEN_Msk & ((value) << HSMCI_MR_BLKLEN_Pos)))
|
||||
/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */
|
||||
#define HSMCI_DTOR_DTOCYC_Pos 0
|
||||
#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */
|
||||
#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)))
|
||||
#define HSMCI_DTOR_DTOMUL_Pos 4
|
||||
#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */
|
||||
#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */
|
||||
#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */
|
||||
#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */
|
||||
#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */
|
||||
#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */
|
||||
#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */
|
||||
#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */
|
||||
#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */
|
||||
/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */
|
||||
#define HSMCI_SDCR_SDCSEL_Pos 0
|
||||
#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */
|
||||
#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */
|
||||
#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */
|
||||
#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */
|
||||
#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */
|
||||
#define HSMCI_SDCR_SDCBUS_Pos 6
|
||||
#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */
|
||||
#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */
|
||||
#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */
|
||||
#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */
|
||||
/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */
|
||||
#define HSMCI_ARGR_ARG_Pos 0
|
||||
#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */
|
||||
#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)))
|
||||
/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */
|
||||
#define HSMCI_CMDR_CMDNB_Pos 0
|
||||
#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */
|
||||
#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)))
|
||||
#define HSMCI_CMDR_RSPTYP_Pos 6
|
||||
#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */
|
||||
#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */
|
||||
#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */
|
||||
#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */
|
||||
#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */
|
||||
#define HSMCI_CMDR_SPCMD_Pos 8
|
||||
#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */
|
||||
#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */
|
||||
#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
|
||||
#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
|
||||
#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
|
||||
#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
|
||||
#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
|
||||
#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
|
||||
#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
|
||||
#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */
|
||||
#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */
|
||||
#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */
|
||||
#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */
|
||||
#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */
|
||||
#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */
|
||||
#define HSMCI_CMDR_TRCMD_Pos 16
|
||||
#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */
|
||||
#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */
|
||||
#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */
|
||||
#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */
|
||||
#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */
|
||||
#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */
|
||||
#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */
|
||||
#define HSMCI_CMDR_TRTYP_Pos 19
|
||||
#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */
|
||||
#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */
|
||||
#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */
|
||||
#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */
|
||||
#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */
|
||||
#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */
|
||||
#define HSMCI_CMDR_IOSPCMD_Pos 24
|
||||
#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */
|
||||
#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */
|
||||
#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */
|
||||
#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
|
||||
#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */
|
||||
/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */
|
||||
#define HSMCI_BLKR_BCNT_Pos 0
|
||||
#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */
|
||||
#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */
|
||||
#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */
|
||||
#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */
|
||||
#define HSMCI_BLKR_BLKLEN_Pos 16
|
||||
#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */
|
||||
#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)))
|
||||
/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */
|
||||
#define HSMCI_CSTOR_CSTOCYC_Pos 0
|
||||
#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */
|
||||
#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)))
|
||||
#define HSMCI_CSTOR_CSTOMUL_Pos 4
|
||||
#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */
|
||||
/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */
|
||||
#define HSMCI_RSPR_RSP_Pos 0
|
||||
#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */
|
||||
/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */
|
||||
#define HSMCI_RDR_DATA_Pos 0
|
||||
#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */
|
||||
/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */
|
||||
#define HSMCI_TDR_DATA_Pos 0
|
||||
#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */
|
||||
#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)))
|
||||
/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */
|
||||
#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */
|
||||
#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */
|
||||
#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */
|
||||
#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */
|
||||
#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */
|
||||
#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */
|
||||
#define HSMCI_SR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) */
|
||||
#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */
|
||||
#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */
|
||||
#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */
|
||||
#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */
|
||||
#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */
|
||||
#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */
|
||||
#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */
|
||||
#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */
|
||||
#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */
|
||||
#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */
|
||||
#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error */
|
||||
#define HSMCI_SR_DMADONE (0x1u << 25) /**< \brief (HSMCI_SR) DMA Transfer done */
|
||||
#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */
|
||||
#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */
|
||||
#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */
|
||||
#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */
|
||||
#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */
|
||||
#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */
|
||||
/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */
|
||||
#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */
|
||||
#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */
|
||||
#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */
|
||||
#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */
|
||||
#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */
|
||||
#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */
|
||||
#define HSMCI_IER_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) */
|
||||
#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */
|
||||
#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */
|
||||
#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */
|
||||
#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */
|
||||
#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */
|
||||
#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */
|
||||
#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */
|
||||
#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */
|
||||
#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */
|
||||
#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */
|
||||
#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */
|
||||
#define HSMCI_IER_DMADONE (0x1u << 25) /**< \brief (HSMCI_IER) DMA Transfer completed Interrupt Enable */
|
||||
#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */
|
||||
#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */
|
||||
#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */
|
||||
#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */
|
||||
#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */
|
||||
#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */
|
||||
/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */
|
||||
#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */
|
||||
#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */
|
||||
#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */
|
||||
#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */
|
||||
#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */
|
||||
#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */
|
||||
#define HSMCI_IDR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) */
|
||||
#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */
|
||||
#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */
|
||||
#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */
|
||||
#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */
|
||||
#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */
|
||||
#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */
|
||||
#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */
|
||||
#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */
|
||||
#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */
|
||||
#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */
|
||||
#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */
|
||||
#define HSMCI_IDR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IDR) DMA Transfer completed Interrupt Disable */
|
||||
#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */
|
||||
#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */
|
||||
#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */
|
||||
#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */
|
||||
#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */
|
||||
#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */
|
||||
/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */
|
||||
#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */
|
||||
#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */
|
||||
#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */
|
||||
#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */
|
||||
#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */
|
||||
#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */
|
||||
#define HSMCI_IMR_MCI_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) */
|
||||
#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */
|
||||
#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */
|
||||
#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */
|
||||
#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */
|
||||
#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */
|
||||
#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */
|
||||
#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */
|
||||
#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */
|
||||
#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */
|
||||
#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */
|
||||
#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */
|
||||
#define HSMCI_IMR_DMADONE (0x1u << 25) /**< \brief (HSMCI_IMR) DMA Transfer Completed Interrupt Mask */
|
||||
#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */
|
||||
#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */
|
||||
#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */
|
||||
#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */
|
||||
#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */
|
||||
#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */
|
||||
/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */
|
||||
#define HSMCI_DMA_OFFSET_Pos 0
|
||||
#define HSMCI_DMA_OFFSET_Msk (0x3u << HSMCI_DMA_OFFSET_Pos) /**< \brief (HSMCI_DMA) DMA Write Buffer Offset */
|
||||
#define HSMCI_DMA_OFFSET(value) ((HSMCI_DMA_OFFSET_Msk & ((value) << HSMCI_DMA_OFFSET_Pos)))
|
||||
#define HSMCI_DMA_CHKSIZE (0x1u << 4) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */
|
||||
#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */
|
||||
#define HSMCI_DMA_CHKSIZE_4 (0x1u << 4) /**< \brief (HSMCI_DMA) 4 data available */
|
||||
#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */
|
||||
#define HSMCI_DMA_ROPT (0x1u << 12) /**< \brief (HSMCI_DMA) Read Optimization with padding */
|
||||
/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */
|
||||
#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */
|
||||
#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */
|
||||
#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */
|
||||
#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */
|
||||
/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */
|
||||
#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */
|
||||
#define HSMCI_WPMR_WP_KEY_Pos 8
|
||||
#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */
|
||||
#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos)))
|
||||
/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */
|
||||
#define HSMCI_WPSR_WP_VS_Pos 0
|
||||
#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */
|
||||
#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */
|
||||
#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */
|
||||
#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */
|
||||
#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */
|
||||
#define HSMCI_WPSR_WP_VSRC_Pos 8
|
||||
#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */
|
||||
/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */
|
||||
#define HSMCI_FIFO_DATA_Pos 0
|
||||
#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */
|
||||
#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_HSMCI_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,242 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_MATRIX_COMPONENT_
|
||||
#define _SAM3U_MATRIX_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_MATRIX AHB Bus Matrix */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Matrix hardware registers */
|
||||
typedef struct {
|
||||
RwReg MATRIX_MCFG[5]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */
|
||||
RoReg Reserved1[11];
|
||||
RwReg MATRIX_SCFG[10]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */
|
||||
RoReg Reserved2[6];
|
||||
RwReg MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */
|
||||
RoReg Reserved3[1];
|
||||
RwReg MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */
|
||||
RoReg Reserved4[1];
|
||||
RwReg MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */
|
||||
RoReg Reserved5[1];
|
||||
RwReg MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */
|
||||
RoReg Reserved6[1];
|
||||
RwReg MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */
|
||||
RoReg Reserved7[1];
|
||||
RwReg MATRIX_PRAS5; /**< \brief (Matrix Offset: 0x00A8) Priority Register A for Slave 5 */
|
||||
RoReg Reserved8[1];
|
||||
RwReg MATRIX_PRAS6; /**< \brief (Matrix Offset: 0x00B0) Priority Register A for Slave 6 */
|
||||
RoReg Reserved9[1];
|
||||
RwReg MATRIX_PRAS7; /**< \brief (Matrix Offset: 0x00B8) Priority Register A for Slave 7 */
|
||||
RoReg Reserved10[1];
|
||||
RwReg MATRIX_PRAS8; /**< \brief (Matrix Offset: 0x00C0) Priority Register A for Slave 8 */
|
||||
RoReg Reserved11[1];
|
||||
RwReg MATRIX_PRAS9; /**< \brief (Matrix Offset: 0x00C8) Priority Register A for Slave 9 */
|
||||
RoReg Reserved12[1];
|
||||
RoReg Reserved13[12];
|
||||
RwReg MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */
|
||||
RoReg Reserved14[56];
|
||||
RwReg MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */
|
||||
RoReg MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */
|
||||
} Matrix;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- MATRIX_MCFG[5] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */
|
||||
#define MATRIX_MCFG_ULBT_Pos 0
|
||||
#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[5]) Undefined Length Burst Type */
|
||||
#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))
|
||||
/* -------- MATRIX_SCFG[10] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE_Pos 0
|
||||
#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[10]) Maximum Number of Allowed Cycles for a Burst */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[10]) Default Master Type */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[10]) Fixed Default Master */
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))
|
||||
#define MATRIX_SCFG_ARBT_Pos 24
|
||||
#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[10]) Arbitration Type */
|
||||
#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))
|
||||
/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */
|
||||
#define MATRIX_PRAS0_M0PR_Pos 0
|
||||
#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */
|
||||
#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))
|
||||
#define MATRIX_PRAS0_M1PR_Pos 4
|
||||
#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */
|
||||
#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))
|
||||
#define MATRIX_PRAS0_M2PR_Pos 8
|
||||
#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */
|
||||
#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))
|
||||
#define MATRIX_PRAS0_M3PR_Pos 12
|
||||
#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */
|
||||
#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))
|
||||
#define MATRIX_PRAS0_M4PR_Pos 16
|
||||
#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */
|
||||
#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */
|
||||
#define MATRIX_PRAS1_M0PR_Pos 0
|
||||
#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */
|
||||
#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))
|
||||
#define MATRIX_PRAS1_M1PR_Pos 4
|
||||
#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */
|
||||
#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))
|
||||
#define MATRIX_PRAS1_M2PR_Pos 8
|
||||
#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */
|
||||
#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))
|
||||
#define MATRIX_PRAS1_M3PR_Pos 12
|
||||
#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */
|
||||
#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))
|
||||
#define MATRIX_PRAS1_M4PR_Pos 16
|
||||
#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */
|
||||
#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */
|
||||
#define MATRIX_PRAS2_M0PR_Pos 0
|
||||
#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */
|
||||
#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))
|
||||
#define MATRIX_PRAS2_M1PR_Pos 4
|
||||
#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */
|
||||
#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))
|
||||
#define MATRIX_PRAS2_M2PR_Pos 8
|
||||
#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */
|
||||
#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))
|
||||
#define MATRIX_PRAS2_M3PR_Pos 12
|
||||
#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */
|
||||
#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))
|
||||
#define MATRIX_PRAS2_M4PR_Pos 16
|
||||
#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */
|
||||
#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */
|
||||
#define MATRIX_PRAS3_M0PR_Pos 0
|
||||
#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */
|
||||
#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))
|
||||
#define MATRIX_PRAS3_M1PR_Pos 4
|
||||
#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */
|
||||
#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))
|
||||
#define MATRIX_PRAS3_M2PR_Pos 8
|
||||
#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */
|
||||
#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))
|
||||
#define MATRIX_PRAS3_M3PR_Pos 12
|
||||
#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */
|
||||
#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))
|
||||
#define MATRIX_PRAS3_M4PR_Pos 16
|
||||
#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */
|
||||
#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */
|
||||
#define MATRIX_PRAS4_M0PR_Pos 0
|
||||
#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */
|
||||
#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos)))
|
||||
#define MATRIX_PRAS4_M1PR_Pos 4
|
||||
#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */
|
||||
#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos)))
|
||||
#define MATRIX_PRAS4_M2PR_Pos 8
|
||||
#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */
|
||||
#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos)))
|
||||
#define MATRIX_PRAS4_M3PR_Pos 12
|
||||
#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */
|
||||
#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos)))
|
||||
#define MATRIX_PRAS4_M4PR_Pos 16
|
||||
#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */
|
||||
#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS5 : (MATRIX Offset: 0x00A8) Priority Register A for Slave 5 -------- */
|
||||
#define MATRIX_PRAS5_M0PR_Pos 0
|
||||
#define MATRIX_PRAS5_M0PR_Msk (0x3u << MATRIX_PRAS5_M0PR_Pos) /**< \brief (MATRIX_PRAS5) Master 0 Priority */
|
||||
#define MATRIX_PRAS5_M0PR(value) ((MATRIX_PRAS5_M0PR_Msk & ((value) << MATRIX_PRAS5_M0PR_Pos)))
|
||||
#define MATRIX_PRAS5_M1PR_Pos 4
|
||||
#define MATRIX_PRAS5_M1PR_Msk (0x3u << MATRIX_PRAS5_M1PR_Pos) /**< \brief (MATRIX_PRAS5) Master 1 Priority */
|
||||
#define MATRIX_PRAS5_M1PR(value) ((MATRIX_PRAS5_M1PR_Msk & ((value) << MATRIX_PRAS5_M1PR_Pos)))
|
||||
#define MATRIX_PRAS5_M2PR_Pos 8
|
||||
#define MATRIX_PRAS5_M2PR_Msk (0x3u << MATRIX_PRAS5_M2PR_Pos) /**< \brief (MATRIX_PRAS5) Master 2 Priority */
|
||||
#define MATRIX_PRAS5_M2PR(value) ((MATRIX_PRAS5_M2PR_Msk & ((value) << MATRIX_PRAS5_M2PR_Pos)))
|
||||
#define MATRIX_PRAS5_M3PR_Pos 12
|
||||
#define MATRIX_PRAS5_M3PR_Msk (0x3u << MATRIX_PRAS5_M3PR_Pos) /**< \brief (MATRIX_PRAS5) Master 3 Priority */
|
||||
#define MATRIX_PRAS5_M3PR(value) ((MATRIX_PRAS5_M3PR_Msk & ((value) << MATRIX_PRAS5_M3PR_Pos)))
|
||||
#define MATRIX_PRAS5_M4PR_Pos 16
|
||||
#define MATRIX_PRAS5_M4PR_Msk (0x3u << MATRIX_PRAS5_M4PR_Pos) /**< \brief (MATRIX_PRAS5) Master 4 Priority */
|
||||
#define MATRIX_PRAS5_M4PR(value) ((MATRIX_PRAS5_M4PR_Msk & ((value) << MATRIX_PRAS5_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS6 : (MATRIX Offset: 0x00B0) Priority Register A for Slave 6 -------- */
|
||||
#define MATRIX_PRAS6_M0PR_Pos 0
|
||||
#define MATRIX_PRAS6_M0PR_Msk (0x3u << MATRIX_PRAS6_M0PR_Pos) /**< \brief (MATRIX_PRAS6) Master 0 Priority */
|
||||
#define MATRIX_PRAS6_M0PR(value) ((MATRIX_PRAS6_M0PR_Msk & ((value) << MATRIX_PRAS6_M0PR_Pos)))
|
||||
#define MATRIX_PRAS6_M1PR_Pos 4
|
||||
#define MATRIX_PRAS6_M1PR_Msk (0x3u << MATRIX_PRAS6_M1PR_Pos) /**< \brief (MATRIX_PRAS6) Master 1 Priority */
|
||||
#define MATRIX_PRAS6_M1PR(value) ((MATRIX_PRAS6_M1PR_Msk & ((value) << MATRIX_PRAS6_M1PR_Pos)))
|
||||
#define MATRIX_PRAS6_M2PR_Pos 8
|
||||
#define MATRIX_PRAS6_M2PR_Msk (0x3u << MATRIX_PRAS6_M2PR_Pos) /**< \brief (MATRIX_PRAS6) Master 2 Priority */
|
||||
#define MATRIX_PRAS6_M2PR(value) ((MATRIX_PRAS6_M2PR_Msk & ((value) << MATRIX_PRAS6_M2PR_Pos)))
|
||||
#define MATRIX_PRAS6_M3PR_Pos 12
|
||||
#define MATRIX_PRAS6_M3PR_Msk (0x3u << MATRIX_PRAS6_M3PR_Pos) /**< \brief (MATRIX_PRAS6) Master 3 Priority */
|
||||
#define MATRIX_PRAS6_M3PR(value) ((MATRIX_PRAS6_M3PR_Msk & ((value) << MATRIX_PRAS6_M3PR_Pos)))
|
||||
#define MATRIX_PRAS6_M4PR_Pos 16
|
||||
#define MATRIX_PRAS6_M4PR_Msk (0x3u << MATRIX_PRAS6_M4PR_Pos) /**< \brief (MATRIX_PRAS6) Master 4 Priority */
|
||||
#define MATRIX_PRAS6_M4PR(value) ((MATRIX_PRAS6_M4PR_Msk & ((value) << MATRIX_PRAS6_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS7 : (MATRIX Offset: 0x00B8) Priority Register A for Slave 7 -------- */
|
||||
#define MATRIX_PRAS7_M0PR_Pos 0
|
||||
#define MATRIX_PRAS7_M0PR_Msk (0x3u << MATRIX_PRAS7_M0PR_Pos) /**< \brief (MATRIX_PRAS7) Master 0 Priority */
|
||||
#define MATRIX_PRAS7_M0PR(value) ((MATRIX_PRAS7_M0PR_Msk & ((value) << MATRIX_PRAS7_M0PR_Pos)))
|
||||
#define MATRIX_PRAS7_M1PR_Pos 4
|
||||
#define MATRIX_PRAS7_M1PR_Msk (0x3u << MATRIX_PRAS7_M1PR_Pos) /**< \brief (MATRIX_PRAS7) Master 1 Priority */
|
||||
#define MATRIX_PRAS7_M1PR(value) ((MATRIX_PRAS7_M1PR_Msk & ((value) << MATRIX_PRAS7_M1PR_Pos)))
|
||||
#define MATRIX_PRAS7_M2PR_Pos 8
|
||||
#define MATRIX_PRAS7_M2PR_Msk (0x3u << MATRIX_PRAS7_M2PR_Pos) /**< \brief (MATRIX_PRAS7) Master 2 Priority */
|
||||
#define MATRIX_PRAS7_M2PR(value) ((MATRIX_PRAS7_M2PR_Msk & ((value) << MATRIX_PRAS7_M2PR_Pos)))
|
||||
#define MATRIX_PRAS7_M3PR_Pos 12
|
||||
#define MATRIX_PRAS7_M3PR_Msk (0x3u << MATRIX_PRAS7_M3PR_Pos) /**< \brief (MATRIX_PRAS7) Master 3 Priority */
|
||||
#define MATRIX_PRAS7_M3PR(value) ((MATRIX_PRAS7_M3PR_Msk & ((value) << MATRIX_PRAS7_M3PR_Pos)))
|
||||
#define MATRIX_PRAS7_M4PR_Pos 16
|
||||
#define MATRIX_PRAS7_M4PR_Msk (0x3u << MATRIX_PRAS7_M4PR_Pos) /**< \brief (MATRIX_PRAS7) Master 4 Priority */
|
||||
#define MATRIX_PRAS7_M4PR(value) ((MATRIX_PRAS7_M4PR_Msk & ((value) << MATRIX_PRAS7_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS8 : (MATRIX Offset: 0x00C0) Priority Register A for Slave 8 -------- */
|
||||
#define MATRIX_PRAS8_M0PR_Pos 0
|
||||
#define MATRIX_PRAS8_M0PR_Msk (0x3u << MATRIX_PRAS8_M0PR_Pos) /**< \brief (MATRIX_PRAS8) Master 0 Priority */
|
||||
#define MATRIX_PRAS8_M0PR(value) ((MATRIX_PRAS8_M0PR_Msk & ((value) << MATRIX_PRAS8_M0PR_Pos)))
|
||||
#define MATRIX_PRAS8_M1PR_Pos 4
|
||||
#define MATRIX_PRAS8_M1PR_Msk (0x3u << MATRIX_PRAS8_M1PR_Pos) /**< \brief (MATRIX_PRAS8) Master 1 Priority */
|
||||
#define MATRIX_PRAS8_M1PR(value) ((MATRIX_PRAS8_M1PR_Msk & ((value) << MATRIX_PRAS8_M1PR_Pos)))
|
||||
#define MATRIX_PRAS8_M2PR_Pos 8
|
||||
#define MATRIX_PRAS8_M2PR_Msk (0x3u << MATRIX_PRAS8_M2PR_Pos) /**< \brief (MATRIX_PRAS8) Master 2 Priority */
|
||||
#define MATRIX_PRAS8_M2PR(value) ((MATRIX_PRAS8_M2PR_Msk & ((value) << MATRIX_PRAS8_M2PR_Pos)))
|
||||
#define MATRIX_PRAS8_M3PR_Pos 12
|
||||
#define MATRIX_PRAS8_M3PR_Msk (0x3u << MATRIX_PRAS8_M3PR_Pos) /**< \brief (MATRIX_PRAS8) Master 3 Priority */
|
||||
#define MATRIX_PRAS8_M3PR(value) ((MATRIX_PRAS8_M3PR_Msk & ((value) << MATRIX_PRAS8_M3PR_Pos)))
|
||||
#define MATRIX_PRAS8_M4PR_Pos 16
|
||||
#define MATRIX_PRAS8_M4PR_Msk (0x3u << MATRIX_PRAS8_M4PR_Pos) /**< \brief (MATRIX_PRAS8) Master 4 Priority */
|
||||
#define MATRIX_PRAS8_M4PR(value) ((MATRIX_PRAS8_M4PR_Msk & ((value) << MATRIX_PRAS8_M4PR_Pos)))
|
||||
/* -------- MATRIX_PRAS9 : (MATRIX Offset: 0x00C8) Priority Register A for Slave 9 -------- */
|
||||
#define MATRIX_PRAS9_M0PR_Pos 0
|
||||
#define MATRIX_PRAS9_M0PR_Msk (0x3u << MATRIX_PRAS9_M0PR_Pos) /**< \brief (MATRIX_PRAS9) Master 0 Priority */
|
||||
#define MATRIX_PRAS9_M0PR(value) ((MATRIX_PRAS9_M0PR_Msk & ((value) << MATRIX_PRAS9_M0PR_Pos)))
|
||||
#define MATRIX_PRAS9_M1PR_Pos 4
|
||||
#define MATRIX_PRAS9_M1PR_Msk (0x3u << MATRIX_PRAS9_M1PR_Pos) /**< \brief (MATRIX_PRAS9) Master 1 Priority */
|
||||
#define MATRIX_PRAS9_M1PR(value) ((MATRIX_PRAS9_M1PR_Msk & ((value) << MATRIX_PRAS9_M1PR_Pos)))
|
||||
#define MATRIX_PRAS9_M2PR_Pos 8
|
||||
#define MATRIX_PRAS9_M2PR_Msk (0x3u << MATRIX_PRAS9_M2PR_Pos) /**< \brief (MATRIX_PRAS9) Master 2 Priority */
|
||||
#define MATRIX_PRAS9_M2PR(value) ((MATRIX_PRAS9_M2PR_Msk & ((value) << MATRIX_PRAS9_M2PR_Pos)))
|
||||
#define MATRIX_PRAS9_M3PR_Pos 12
|
||||
#define MATRIX_PRAS9_M3PR_Msk (0x3u << MATRIX_PRAS9_M3PR_Pos) /**< \brief (MATRIX_PRAS9) Master 3 Priority */
|
||||
#define MATRIX_PRAS9_M3PR(value) ((MATRIX_PRAS9_M3PR_Msk & ((value) << MATRIX_PRAS9_M3PR_Pos)))
|
||||
#define MATRIX_PRAS9_M4PR_Pos 16
|
||||
#define MATRIX_PRAS9_M4PR_Msk (0x3u << MATRIX_PRAS9_M4PR_Pos) /**< \brief (MATRIX_PRAS9) Master 4 Priority */
|
||||
#define MATRIX_PRAS9_M4PR(value) ((MATRIX_PRAS9_M4PR_Msk & ((value) << MATRIX_PRAS9_M4PR_Pos)))
|
||||
/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */
|
||||
#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 0 */
|
||||
#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 1 */
|
||||
#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 2 */
|
||||
#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 3 */
|
||||
#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for AHB Master 4 */
|
||||
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */
|
||||
#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */
|
||||
#define MATRIX_WPMR_WPKEY_Pos 8
|
||||
#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */
|
||||
#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))
|
||||
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */
|
||||
#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */
|
||||
#define MATRIX_WPSR_WPVSRC_Pos 8
|
||||
#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_MATRIX_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PDC_COMPONENT_
|
||||
#define _SAM3U_PDC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_PDC Peripheral DMA Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Pdc hardware registers */
|
||||
typedef struct {
|
||||
RwReg PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */
|
||||
RwReg PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */
|
||||
RwReg PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */
|
||||
RwReg PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */
|
||||
RwReg PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */
|
||||
RwReg PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */
|
||||
RwReg PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */
|
||||
RwReg PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */
|
||||
WoReg PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */
|
||||
RoReg PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */
|
||||
} Pdc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */
|
||||
#define PERIPH_RPR_RXPTR_Pos 0
|
||||
#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */
|
||||
#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos)))
|
||||
/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */
|
||||
#define PERIPH_RCR_RXCTR_Pos 0
|
||||
#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */
|
||||
#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos)))
|
||||
/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */
|
||||
#define PERIPH_TPR_TXPTR_Pos 0
|
||||
#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */
|
||||
#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos)))
|
||||
/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */
|
||||
#define PERIPH_TCR_TXCTR_Pos 0
|
||||
#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */
|
||||
#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos)))
|
||||
/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */
|
||||
#define PERIPH_RNPR_RXNPTR_Pos 0
|
||||
#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */
|
||||
#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos)))
|
||||
/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */
|
||||
#define PERIPH_RNCR_RXNCTR_Pos 0
|
||||
#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */
|
||||
#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos)))
|
||||
/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */
|
||||
#define PERIPH_TNPR_TXNPTR_Pos 0
|
||||
#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */
|
||||
#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos)))
|
||||
/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */
|
||||
#define PERIPH_TNCR_TXNCTR_Pos 0
|
||||
#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */
|
||||
#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos)))
|
||||
/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */
|
||||
#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */
|
||||
#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */
|
||||
#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */
|
||||
#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */
|
||||
#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */
|
||||
#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_PDC_COMPONENT_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,302 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PMC_COMPONENT_
|
||||
#define _SAM3U_PMC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Power Management Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_PMC Power Management Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Pmc hardware registers */
|
||||
typedef struct {
|
||||
WoReg PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */
|
||||
WoReg PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */
|
||||
RoReg PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */
|
||||
RoReg Reserved1[1];
|
||||
WoReg PMC_PCER; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register */
|
||||
WoReg PMC_PCDR; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register */
|
||||
RoReg PMC_PCSR; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register */
|
||||
RwReg CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */
|
||||
RwReg CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */
|
||||
RoReg CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */
|
||||
RwReg CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */
|
||||
RoReg Reserved2[1];
|
||||
RwReg PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */
|
||||
RoReg Reserved3[3];
|
||||
RwReg PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */
|
||||
RoReg Reserved4[5];
|
||||
WoReg PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */
|
||||
WoReg PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */
|
||||
RoReg PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */
|
||||
RoReg PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */
|
||||
RwReg PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */
|
||||
RwReg PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */
|
||||
WoReg PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */
|
||||
RoReg Reserved5[26];
|
||||
RwReg PMC_WPMR; /**< \brief (Pmc Offset: 0xE4) Write Protect Mode Register */
|
||||
RoReg PMC_WPSR; /**< \brief (Pmc Offset: 0xE8) Write Protect Status Register */
|
||||
} Pmc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
|
||||
#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */
|
||||
#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */
|
||||
#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */
|
||||
/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
|
||||
#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */
|
||||
#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */
|
||||
#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */
|
||||
/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
|
||||
#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */
|
||||
#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */
|
||||
#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */
|
||||
/* -------- PMC_PCER : (PMC Offset: 0x0010) Peripheral Clock Enable Register -------- */
|
||||
#define PMC_PCER_PID2 (0x1u << 2) /**< \brief (PMC_PCER) Peripheral Clock 2 Enable */
|
||||
#define PMC_PCER_PID3 (0x1u << 3) /**< \brief (PMC_PCER) Peripheral Clock 3 Enable */
|
||||
#define PMC_PCER_PID4 (0x1u << 4) /**< \brief (PMC_PCER) Peripheral Clock 4 Enable */
|
||||
#define PMC_PCER_PID5 (0x1u << 5) /**< \brief (PMC_PCER) Peripheral Clock 5 Enable */
|
||||
#define PMC_PCER_PID6 (0x1u << 6) /**< \brief (PMC_PCER) Peripheral Clock 6 Enable */
|
||||
#define PMC_PCER_PID7 (0x1u << 7) /**< \brief (PMC_PCER) Peripheral Clock 7 Enable */
|
||||
#define PMC_PCER_PID8 (0x1u << 8) /**< \brief (PMC_PCER) Peripheral Clock 8 Enable */
|
||||
#define PMC_PCER_PID9 (0x1u << 9) /**< \brief (PMC_PCER) Peripheral Clock 9 Enable */
|
||||
#define PMC_PCER_PID10 (0x1u << 10) /**< \brief (PMC_PCER) Peripheral Clock 10 Enable */
|
||||
#define PMC_PCER_PID11 (0x1u << 11) /**< \brief (PMC_PCER) Peripheral Clock 11 Enable */
|
||||
#define PMC_PCER_PID12 (0x1u << 12) /**< \brief (PMC_PCER) Peripheral Clock 12 Enable */
|
||||
#define PMC_PCER_PID13 (0x1u << 13) /**< \brief (PMC_PCER) Peripheral Clock 13 Enable */
|
||||
#define PMC_PCER_PID14 (0x1u << 14) /**< \brief (PMC_PCER) Peripheral Clock 14 Enable */
|
||||
#define PMC_PCER_PID15 (0x1u << 15) /**< \brief (PMC_PCER) Peripheral Clock 15 Enable */
|
||||
#define PMC_PCER_PID16 (0x1u << 16) /**< \brief (PMC_PCER) Peripheral Clock 16 Enable */
|
||||
#define PMC_PCER_PID17 (0x1u << 17) /**< \brief (PMC_PCER) Peripheral Clock 17 Enable */
|
||||
#define PMC_PCER_PID18 (0x1u << 18) /**< \brief (PMC_PCER) Peripheral Clock 18 Enable */
|
||||
#define PMC_PCER_PID19 (0x1u << 19) /**< \brief (PMC_PCER) Peripheral Clock 19 Enable */
|
||||
#define PMC_PCER_PID20 (0x1u << 20) /**< \brief (PMC_PCER) Peripheral Clock 20 Enable */
|
||||
#define PMC_PCER_PID21 (0x1u << 21) /**< \brief (PMC_PCER) Peripheral Clock 21 Enable */
|
||||
#define PMC_PCER_PID22 (0x1u << 22) /**< \brief (PMC_PCER) Peripheral Clock 22 Enable */
|
||||
#define PMC_PCER_PID23 (0x1u << 23) /**< \brief (PMC_PCER) Peripheral Clock 23 Enable */
|
||||
#define PMC_PCER_PID24 (0x1u << 24) /**< \brief (PMC_PCER) Peripheral Clock 24 Enable */
|
||||
#define PMC_PCER_PID25 (0x1u << 25) /**< \brief (PMC_PCER) Peripheral Clock 25 Enable */
|
||||
#define PMC_PCER_PID26 (0x1u << 26) /**< \brief (PMC_PCER) Peripheral Clock 26 Enable */
|
||||
#define PMC_PCER_PID27 (0x1u << 27) /**< \brief (PMC_PCER) Peripheral Clock 27 Enable */
|
||||
#define PMC_PCER_PID28 (0x1u << 28) /**< \brief (PMC_PCER) Peripheral Clock 28 Enable */
|
||||
#define PMC_PCER_PID29 (0x1u << 29) /**< \brief (PMC_PCER) Peripheral Clock 29 Enable */
|
||||
#define PMC_PCER_PID30 (0x1u << 30) /**< \brief (PMC_PCER) Peripheral Clock 30 Enable */
|
||||
#define PMC_PCER_PID31 (0x1u << 31) /**< \brief (PMC_PCER) Peripheral Clock 31 Enable */
|
||||
/* -------- PMC_PCDR : (PMC Offset: 0x0014) Peripheral Clock Disable Register -------- */
|
||||
#define PMC_PCDR_PID2 (0x1u << 2) /**< \brief (PMC_PCDR) Peripheral Clock 2 Disable */
|
||||
#define PMC_PCDR_PID3 (0x1u << 3) /**< \brief (PMC_PCDR) Peripheral Clock 3 Disable */
|
||||
#define PMC_PCDR_PID4 (0x1u << 4) /**< \brief (PMC_PCDR) Peripheral Clock 4 Disable */
|
||||
#define PMC_PCDR_PID5 (0x1u << 5) /**< \brief (PMC_PCDR) Peripheral Clock 5 Disable */
|
||||
#define PMC_PCDR_PID6 (0x1u << 6) /**< \brief (PMC_PCDR) Peripheral Clock 6 Disable */
|
||||
#define PMC_PCDR_PID7 (0x1u << 7) /**< \brief (PMC_PCDR) Peripheral Clock 7 Disable */
|
||||
#define PMC_PCDR_PID8 (0x1u << 8) /**< \brief (PMC_PCDR) Peripheral Clock 8 Disable */
|
||||
#define PMC_PCDR_PID9 (0x1u << 9) /**< \brief (PMC_PCDR) Peripheral Clock 9 Disable */
|
||||
#define PMC_PCDR_PID10 (0x1u << 10) /**< \brief (PMC_PCDR) Peripheral Clock 10 Disable */
|
||||
#define PMC_PCDR_PID11 (0x1u << 11) /**< \brief (PMC_PCDR) Peripheral Clock 11 Disable */
|
||||
#define PMC_PCDR_PID12 (0x1u << 12) /**< \brief (PMC_PCDR) Peripheral Clock 12 Disable */
|
||||
#define PMC_PCDR_PID13 (0x1u << 13) /**< \brief (PMC_PCDR) Peripheral Clock 13 Disable */
|
||||
#define PMC_PCDR_PID14 (0x1u << 14) /**< \brief (PMC_PCDR) Peripheral Clock 14 Disable */
|
||||
#define PMC_PCDR_PID15 (0x1u << 15) /**< \brief (PMC_PCDR) Peripheral Clock 15 Disable */
|
||||
#define PMC_PCDR_PID16 (0x1u << 16) /**< \brief (PMC_PCDR) Peripheral Clock 16 Disable */
|
||||
#define PMC_PCDR_PID17 (0x1u << 17) /**< \brief (PMC_PCDR) Peripheral Clock 17 Disable */
|
||||
#define PMC_PCDR_PID18 (0x1u << 18) /**< \brief (PMC_PCDR) Peripheral Clock 18 Disable */
|
||||
#define PMC_PCDR_PID19 (0x1u << 19) /**< \brief (PMC_PCDR) Peripheral Clock 19 Disable */
|
||||
#define PMC_PCDR_PID20 (0x1u << 20) /**< \brief (PMC_PCDR) Peripheral Clock 20 Disable */
|
||||
#define PMC_PCDR_PID21 (0x1u << 21) /**< \brief (PMC_PCDR) Peripheral Clock 21 Disable */
|
||||
#define PMC_PCDR_PID22 (0x1u << 22) /**< \brief (PMC_PCDR) Peripheral Clock 22 Disable */
|
||||
#define PMC_PCDR_PID23 (0x1u << 23) /**< \brief (PMC_PCDR) Peripheral Clock 23 Disable */
|
||||
#define PMC_PCDR_PID24 (0x1u << 24) /**< \brief (PMC_PCDR) Peripheral Clock 24 Disable */
|
||||
#define PMC_PCDR_PID25 (0x1u << 25) /**< \brief (PMC_PCDR) Peripheral Clock 25 Disable */
|
||||
#define PMC_PCDR_PID26 (0x1u << 26) /**< \brief (PMC_PCDR) Peripheral Clock 26 Disable */
|
||||
#define PMC_PCDR_PID27 (0x1u << 27) /**< \brief (PMC_PCDR) Peripheral Clock 27 Disable */
|
||||
#define PMC_PCDR_PID28 (0x1u << 28) /**< \brief (PMC_PCDR) Peripheral Clock 28 Disable */
|
||||
#define PMC_PCDR_PID29 (0x1u << 29) /**< \brief (PMC_PCDR) Peripheral Clock 29 Disable */
|
||||
#define PMC_PCDR_PID30 (0x1u << 30) /**< \brief (PMC_PCDR) Peripheral Clock 30 Disable */
|
||||
#define PMC_PCDR_PID31 (0x1u << 31) /**< \brief (PMC_PCDR) Peripheral Clock 31 Disable */
|
||||
/* -------- PMC_PCSR : (PMC Offset: 0x0018) Peripheral Clock Status Register -------- */
|
||||
#define PMC_PCSR_PID2 (0x1u << 2) /**< \brief (PMC_PCSR) Peripheral Clock 2 Status */
|
||||
#define PMC_PCSR_PID3 (0x1u << 3) /**< \brief (PMC_PCSR) Peripheral Clock 3 Status */
|
||||
#define PMC_PCSR_PID4 (0x1u << 4) /**< \brief (PMC_PCSR) Peripheral Clock 4 Status */
|
||||
#define PMC_PCSR_PID5 (0x1u << 5) /**< \brief (PMC_PCSR) Peripheral Clock 5 Status */
|
||||
#define PMC_PCSR_PID6 (0x1u << 6) /**< \brief (PMC_PCSR) Peripheral Clock 6 Status */
|
||||
#define PMC_PCSR_PID7 (0x1u << 7) /**< \brief (PMC_PCSR) Peripheral Clock 7 Status */
|
||||
#define PMC_PCSR_PID8 (0x1u << 8) /**< \brief (PMC_PCSR) Peripheral Clock 8 Status */
|
||||
#define PMC_PCSR_PID9 (0x1u << 9) /**< \brief (PMC_PCSR) Peripheral Clock 9 Status */
|
||||
#define PMC_PCSR_PID10 (0x1u << 10) /**< \brief (PMC_PCSR) Peripheral Clock 10 Status */
|
||||
#define PMC_PCSR_PID11 (0x1u << 11) /**< \brief (PMC_PCSR) Peripheral Clock 11 Status */
|
||||
#define PMC_PCSR_PID12 (0x1u << 12) /**< \brief (PMC_PCSR) Peripheral Clock 12 Status */
|
||||
#define PMC_PCSR_PID13 (0x1u << 13) /**< \brief (PMC_PCSR) Peripheral Clock 13 Status */
|
||||
#define PMC_PCSR_PID14 (0x1u << 14) /**< \brief (PMC_PCSR) Peripheral Clock 14 Status */
|
||||
#define PMC_PCSR_PID15 (0x1u << 15) /**< \brief (PMC_PCSR) Peripheral Clock 15 Status */
|
||||
#define PMC_PCSR_PID16 (0x1u << 16) /**< \brief (PMC_PCSR) Peripheral Clock 16 Status */
|
||||
#define PMC_PCSR_PID17 (0x1u << 17) /**< \brief (PMC_PCSR) Peripheral Clock 17 Status */
|
||||
#define PMC_PCSR_PID18 (0x1u << 18) /**< \brief (PMC_PCSR) Peripheral Clock 18 Status */
|
||||
#define PMC_PCSR_PID19 (0x1u << 19) /**< \brief (PMC_PCSR) Peripheral Clock 19 Status */
|
||||
#define PMC_PCSR_PID20 (0x1u << 20) /**< \brief (PMC_PCSR) Peripheral Clock 20 Status */
|
||||
#define PMC_PCSR_PID21 (0x1u << 21) /**< \brief (PMC_PCSR) Peripheral Clock 21 Status */
|
||||
#define PMC_PCSR_PID22 (0x1u << 22) /**< \brief (PMC_PCSR) Peripheral Clock 22 Status */
|
||||
#define PMC_PCSR_PID23 (0x1u << 23) /**< \brief (PMC_PCSR) Peripheral Clock 23 Status */
|
||||
#define PMC_PCSR_PID24 (0x1u << 24) /**< \brief (PMC_PCSR) Peripheral Clock 24 Status */
|
||||
#define PMC_PCSR_PID25 (0x1u << 25) /**< \brief (PMC_PCSR) Peripheral Clock 25 Status */
|
||||
#define PMC_PCSR_PID26 (0x1u << 26) /**< \brief (PMC_PCSR) Peripheral Clock 26 Status */
|
||||
#define PMC_PCSR_PID27 (0x1u << 27) /**< \brief (PMC_PCSR) Peripheral Clock 27 Status */
|
||||
#define PMC_PCSR_PID28 (0x1u << 28) /**< \brief (PMC_PCSR) Peripheral Clock 28 Status */
|
||||
#define PMC_PCSR_PID29 (0x1u << 29) /**< \brief (PMC_PCSR) Peripheral Clock 29 Status */
|
||||
#define PMC_PCSR_PID30 (0x1u << 30) /**< \brief (PMC_PCSR) Peripheral Clock 30 Status */
|
||||
#define PMC_PCSR_PID31 (0x1u << 31) /**< \brief (PMC_PCSR) Peripheral Clock 31 Status */
|
||||
/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
|
||||
#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */
|
||||
#define CKGR_UCKR_UPLLCOUNT_Pos 20
|
||||
#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */
|
||||
#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
|
||||
/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
|
||||
#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */
|
||||
#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */
|
||||
#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command */
|
||||
#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */
|
||||
#define CKGR_MOR_MOSCRCF_Pos 4
|
||||
#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */
|
||||
#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos)))
|
||||
#define CKGR_MOR_MOSCXTST_Pos 8
|
||||
#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */
|
||||
#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
|
||||
#define CKGR_MOR_KEY_Pos 16
|
||||
#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */
|
||||
#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
|
||||
#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */
|
||||
#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */
|
||||
/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
|
||||
#define CKGR_MCFR_MAINF_Pos 0
|
||||
#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */
|
||||
#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */
|
||||
/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
|
||||
#define CKGR_PLLAR_DIVA_Pos 0
|
||||
#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */
|
||||
#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
|
||||
#define CKGR_PLLAR_PLLACOUNT_Pos 8
|
||||
#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */
|
||||
#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
|
||||
#define CKGR_PLLAR_STMODE_Pos 14
|
||||
#define CKGR_PLLAR_STMODE_Msk (0x3u << CKGR_PLLAR_STMODE_Pos) /**< \brief (CKGR_PLLAR) Start Mode */
|
||||
#define CKGR_PLLAR_STMODE(value) ((CKGR_PLLAR_STMODE_Msk & ((value) << CKGR_PLLAR_STMODE_Pos)))
|
||||
#define CKGR_PLLAR_MULA_Pos 16
|
||||
#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */
|
||||
#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
|
||||
#define CKGR_PLLAR_STUCKTO1 (0x1u << 29) /**< \brief (CKGR_PLLAR) */
|
||||
/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
|
||||
#define PMC_MCKR_CSS_Pos 0
|
||||
#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */
|
||||
#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos)))
|
||||
#define PMC_MCKR_PRES_Pos 4
|
||||
#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */
|
||||
#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos)))
|
||||
#define PMC_MCKR_UPLLDIV (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divider */
|
||||
/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
|
||||
#define PMC_PCK_CSS_Pos 0
|
||||
#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */
|
||||
#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos)))
|
||||
#define PMC_PCK_PRES_Pos 4
|
||||
#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */
|
||||
#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos)))
|
||||
/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
|
||||
#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */
|
||||
#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLL A Lock Interrupt Enable */
|
||||
#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */
|
||||
#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */
|
||||
#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */
|
||||
#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */
|
||||
#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */
|
||||
#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */
|
||||
/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
|
||||
#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */
|
||||
#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLL A Lock Interrupt Disable */
|
||||
#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */
|
||||
#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */
|
||||
#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */
|
||||
#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */
|
||||
#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */
|
||||
#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */
|
||||
/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
|
||||
#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */
|
||||
#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLL A Lock Status */
|
||||
#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */
|
||||
#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */
|
||||
#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */
|
||||
#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */
|
||||
#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */
|
||||
#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */
|
||||
#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */
|
||||
#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */
|
||||
#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */
|
||||
#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */
|
||||
#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */
|
||||
/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
|
||||
#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */
|
||||
#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLL A Lock Interrupt Mask */
|
||||
#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */
|
||||
#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */
|
||||
#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */
|
||||
#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */
|
||||
#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */
|
||||
#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */
|
||||
/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
|
||||
#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */
|
||||
#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */
|
||||
#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */
|
||||
#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */
|
||||
#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */
|
||||
#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */
|
||||
#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */
|
||||
#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */
|
||||
#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */
|
||||
#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */
|
||||
#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */
|
||||
#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */
|
||||
#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */
|
||||
#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */
|
||||
#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */
|
||||
#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */
|
||||
#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */
|
||||
#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */
|
||||
#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */
|
||||
#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */
|
||||
/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
|
||||
#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) */
|
||||
#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) */
|
||||
/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
|
||||
#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */
|
||||
/* -------- PMC_WPMR : (PMC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */
|
||||
#define PMC_WPMR_WPKEY_Pos 8
|
||||
#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */
|
||||
#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
|
||||
/* -------- PMC_WPSR : (PMC Offset: 0xE8) Write Protect Status Register -------- */
|
||||
#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Proteact Violation Status */
|
||||
#define PMC_WPSR_WPVSRC_Pos 8
|
||||
#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_PMC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,530 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PWM_COMPONENT_
|
||||
#define _SAM3U_PWM_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_PWM Pulse Width Modulation Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief PwmCh_num hardware registers */
|
||||
typedef struct {
|
||||
RwReg PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */
|
||||
RwReg PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */
|
||||
RwReg PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */
|
||||
RwReg PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */
|
||||
RwReg PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */
|
||||
RwReg PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */
|
||||
RwReg PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */
|
||||
RwReg PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */
|
||||
} PwmCh_num;
|
||||
/** \brief PwmCmp hardware registers */
|
||||
typedef struct {
|
||||
RwReg PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */
|
||||
RwReg PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */
|
||||
RwReg PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */
|
||||
RwReg PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */
|
||||
} PwmCmp;
|
||||
/** \brief Pwm hardware registers */
|
||||
#define PWMCMP_NUMBER 8
|
||||
#define PWMCH_NUM_NUMBER 4
|
||||
typedef struct {
|
||||
RwReg PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */
|
||||
WoReg PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */
|
||||
WoReg PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */
|
||||
RoReg PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */
|
||||
WoReg PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */
|
||||
WoReg PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */
|
||||
RoReg PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */
|
||||
RoReg PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */
|
||||
RwReg PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */
|
||||
RoReg Reserved1[1];
|
||||
RwReg PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */
|
||||
RwReg PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */
|
||||
WoReg PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */
|
||||
WoReg PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */
|
||||
WoReg PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */
|
||||
RoReg PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */
|
||||
RoReg PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */
|
||||
RwReg PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */
|
||||
RwReg PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */
|
||||
WoReg PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */
|
||||
WoReg PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */
|
||||
WoReg PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */
|
||||
WoReg PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */
|
||||
RwReg PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */
|
||||
RoReg PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */
|
||||
WoReg PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */
|
||||
RwReg PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */
|
||||
RwReg PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */
|
||||
RoReg Reserved2[3];
|
||||
RwReg PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */
|
||||
RoReg Reserved3[24];
|
||||
WoReg PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */
|
||||
RoReg PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */
|
||||
RoReg Reserved4[5];
|
||||
RwReg PWM_RPR; /**< \brief (Pwm Offset: 0x100) Receive Pointer Register */
|
||||
RwReg PWM_RCR; /**< \brief (Pwm Offset: 0x104) Receive Counter Register */
|
||||
RwReg PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg PWM_RNPR; /**< \brief (Pwm Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg PWM_RNCR; /**< \brief (Pwm Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */
|
||||
RoReg PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */
|
||||
RoReg Reserved5[2];
|
||||
PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */
|
||||
RoReg Reserved6[20];
|
||||
PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */
|
||||
} Pwm;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */
|
||||
#define PWM_CLK_DIVA_Pos 0
|
||||
#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
|
||||
#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos)))
|
||||
#define PWM_CLK_PREA_Pos 8
|
||||
#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
|
||||
#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos)))
|
||||
#define PWM_CLK_DIVB_Pos 16
|
||||
#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */
|
||||
#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos)))
|
||||
#define PWM_CLK_PREB_Pos 24
|
||||
#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */
|
||||
#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos)))
|
||||
/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */
|
||||
#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */
|
||||
#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */
|
||||
#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */
|
||||
#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */
|
||||
/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */
|
||||
#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */
|
||||
#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */
|
||||
#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */
|
||||
#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */
|
||||
/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */
|
||||
#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */
|
||||
#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */
|
||||
#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */
|
||||
#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */
|
||||
/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */
|
||||
#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */
|
||||
#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */
|
||||
#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */
|
||||
#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */
|
||||
#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */
|
||||
#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */
|
||||
#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */
|
||||
#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */
|
||||
/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */
|
||||
#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */
|
||||
#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */
|
||||
#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */
|
||||
#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */
|
||||
#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */
|
||||
#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */
|
||||
#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */
|
||||
#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */
|
||||
/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */
|
||||
#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */
|
||||
#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */
|
||||
#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */
|
||||
#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */
|
||||
#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */
|
||||
#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */
|
||||
#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */
|
||||
#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */
|
||||
/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */
|
||||
#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */
|
||||
#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */
|
||||
#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */
|
||||
#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */
|
||||
#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */
|
||||
#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */
|
||||
#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */
|
||||
#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */
|
||||
/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */
|
||||
#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */
|
||||
#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */
|
||||
#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */
|
||||
#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */
|
||||
#define PWM_SCM_UPDM_Pos 16
|
||||
#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */
|
||||
#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */
|
||||
#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */
|
||||
#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */
|
||||
#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */
|
||||
#define PWM_SCM_PTRCS_Pos 21
|
||||
#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */
|
||||
#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos)))
|
||||
/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */
|
||||
#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */
|
||||
/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */
|
||||
#define PWM_SCUP_UPR_Pos 0
|
||||
#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */
|
||||
#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos)))
|
||||
#define PWM_SCUP_UPRCNT_Pos 4
|
||||
#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */
|
||||
#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos)))
|
||||
/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */
|
||||
#define PWM_SCUPUPD_UPRUPD_Pos 0
|
||||
#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */
|
||||
#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos)))
|
||||
/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */
|
||||
#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */
|
||||
#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */
|
||||
#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */
|
||||
#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */
|
||||
#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */
|
||||
#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */
|
||||
#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */
|
||||
/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */
|
||||
#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */
|
||||
#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */
|
||||
#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */
|
||||
#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */
|
||||
#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */
|
||||
/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */
|
||||
#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */
|
||||
#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */
|
||||
#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */
|
||||
#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */
|
||||
#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */
|
||||
/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */
|
||||
#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */
|
||||
#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */
|
||||
#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */
|
||||
#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */
|
||||
#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */
|
||||
#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */
|
||||
#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */
|
||||
#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */
|
||||
#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */
|
||||
#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */
|
||||
#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */
|
||||
#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */
|
||||
#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */
|
||||
#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */
|
||||
#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */
|
||||
#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */
|
||||
#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */
|
||||
#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */
|
||||
#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */
|
||||
#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */
|
||||
/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */
|
||||
#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */
|
||||
#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */
|
||||
#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */
|
||||
#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */
|
||||
#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */
|
||||
#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */
|
||||
#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */
|
||||
#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */
|
||||
/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */
|
||||
#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */
|
||||
#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */
|
||||
#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */
|
||||
#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */
|
||||
#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */
|
||||
#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */
|
||||
#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */
|
||||
#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */
|
||||
/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */
|
||||
#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */
|
||||
#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */
|
||||
#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */
|
||||
#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */
|
||||
#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */
|
||||
#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */
|
||||
#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */
|
||||
#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */
|
||||
/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */
|
||||
#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */
|
||||
#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */
|
||||
#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */
|
||||
#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */
|
||||
#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */
|
||||
#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */
|
||||
#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */
|
||||
#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */
|
||||
/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */
|
||||
#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */
|
||||
#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */
|
||||
#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */
|
||||
#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */
|
||||
#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */
|
||||
#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */
|
||||
#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */
|
||||
#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */
|
||||
/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */
|
||||
#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */
|
||||
#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */
|
||||
#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */
|
||||
#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */
|
||||
#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */
|
||||
#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */
|
||||
#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */
|
||||
#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */
|
||||
/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */
|
||||
#define PWM_FMR_FPOL_Pos 0
|
||||
#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos)))
|
||||
#define PWM_FMR_FMOD_Pos 8
|
||||
#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos)))
|
||||
#define PWM_FMR_FFIL_Pos 16
|
||||
#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos)))
|
||||
/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */
|
||||
#define PWM_FSR_FIV_Pos 0
|
||||
#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FSR_FS_Pos 8
|
||||
#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 3) */
|
||||
/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */
|
||||
#define PWM_FCR_FCLR_Pos 0
|
||||
#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos)))
|
||||
/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */
|
||||
#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */
|
||||
#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */
|
||||
#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */
|
||||
#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */
|
||||
#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */
|
||||
#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */
|
||||
#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */
|
||||
#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */
|
||||
/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */
|
||||
#define PWM_FPE_FPE0_Pos 0
|
||||
#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos)))
|
||||
#define PWM_FPE_FPE1_Pos 8
|
||||
#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos)))
|
||||
#define PWM_FPE_FPE2_Pos 16
|
||||
#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos)))
|
||||
#define PWM_FPE_FPE3_Pos 24
|
||||
#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 3) */
|
||||
#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos)))
|
||||
/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */
|
||||
#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */
|
||||
#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */
|
||||
#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */
|
||||
#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */
|
||||
#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */
|
||||
#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */
|
||||
#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */
|
||||
#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */
|
||||
/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */
|
||||
#define PWM_WPCR_WPCMD_Pos 0
|
||||
#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */
|
||||
#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos)))
|
||||
#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */
|
||||
#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */
|
||||
#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */
|
||||
#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */
|
||||
#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */
|
||||
#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */
|
||||
#define PWM_WPCR_WPKEY_Pos 8
|
||||
#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */
|
||||
#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos)))
|
||||
/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */
|
||||
#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */
|
||||
#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */
|
||||
#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */
|
||||
#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */
|
||||
#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */
|
||||
#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */
|
||||
#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */
|
||||
#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */
|
||||
#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */
|
||||
#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */
|
||||
#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */
|
||||
#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */
|
||||
#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */
|
||||
#define PWM_WPSR_WPVSRC_Pos 16
|
||||
#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */
|
||||
/* -------- PWM_RPR : (PWM Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define PWM_RPR_RXPTR_Pos 0
|
||||
#define PWM_RPR_RXPTR_Msk (0xffffffffu << PWM_RPR_RXPTR_Pos) /**< \brief (PWM_RPR) Receive Pointer Register */
|
||||
#define PWM_RPR_RXPTR(value) ((PWM_RPR_RXPTR_Msk & ((value) << PWM_RPR_RXPTR_Pos)))
|
||||
/* -------- PWM_RCR : (PWM Offset: 0x104) Receive Counter Register -------- */
|
||||
#define PWM_RCR_RXCTR_Pos 0
|
||||
#define PWM_RCR_RXCTR_Msk (0xffffu << PWM_RCR_RXCTR_Pos) /**< \brief (PWM_RCR) Receive Counter Register */
|
||||
#define PWM_RCR_RXCTR(value) ((PWM_RCR_RXCTR_Msk & ((value) << PWM_RCR_RXCTR_Pos)))
|
||||
/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define PWM_TPR_TXPTR_Pos 0
|
||||
#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */
|
||||
#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos)))
|
||||
/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define PWM_TCR_TXCTR_Pos 0
|
||||
#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */
|
||||
#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos)))
|
||||
/* -------- PWM_RNPR : (PWM Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define PWM_RNPR_RXNPTR_Pos 0
|
||||
#define PWM_RNPR_RXNPTR_Msk (0xffffffffu << PWM_RNPR_RXNPTR_Pos) /**< \brief (PWM_RNPR) Receive Next Pointer */
|
||||
#define PWM_RNPR_RXNPTR(value) ((PWM_RNPR_RXNPTR_Msk & ((value) << PWM_RNPR_RXNPTR_Pos)))
|
||||
/* -------- PWM_RNCR : (PWM Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define PWM_RNCR_RXNCTR_Pos 0
|
||||
#define PWM_RNCR_RXNCTR_Msk (0xffffu << PWM_RNCR_RXNCTR_Pos) /**< \brief (PWM_RNCR) Receive Next Counter */
|
||||
#define PWM_RNCR_RXNCTR(value) ((PWM_RNCR_RXNCTR_Msk & ((value) << PWM_RNCR_RXNCTR_Pos)))
|
||||
/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define PWM_TNPR_TXNPTR_Pos 0
|
||||
#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */
|
||||
#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos)))
|
||||
/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define PWM_TNCR_TXNCTR_Pos 0
|
||||
#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */
|
||||
#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos)))
|
||||
/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */
|
||||
#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */
|
||||
#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */
|
||||
#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */
|
||||
#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */
|
||||
#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */
|
||||
#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */
|
||||
/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */
|
||||
#define PWM_CMPV_CV_Pos 0
|
||||
#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */
|
||||
#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos)))
|
||||
#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */
|
||||
/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */
|
||||
#define PWM_CMPVUPD_CVUPD_Pos 0
|
||||
#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */
|
||||
#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos)))
|
||||
#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */
|
||||
/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */
|
||||
#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */
|
||||
#define PWM_CMPM_CTR_Pos 4
|
||||
#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */
|
||||
#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos)))
|
||||
#define PWM_CMPM_CPR_Pos 8
|
||||
#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */
|
||||
#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos)))
|
||||
#define PWM_CMPM_CPRCNT_Pos 12
|
||||
#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */
|
||||
#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos)))
|
||||
#define PWM_CMPM_CUPR_Pos 16
|
||||
#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */
|
||||
#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos)))
|
||||
#define PWM_CMPM_CUPRCNT_Pos 20
|
||||
#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */
|
||||
#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos)))
|
||||
/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */
|
||||
#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */
|
||||
#define PWM_CMPMUPD_CTRUPD_Pos 4
|
||||
#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */
|
||||
#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos)))
|
||||
#define PWM_CMPMUPD_CPRUPD_Pos 8
|
||||
#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */
|
||||
#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos)))
|
||||
#define PWM_CMPMUPD_CUPRUPD_Pos 16
|
||||
#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */
|
||||
#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos)))
|
||||
/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */
|
||||
#define PWM_CMR_CPRE_Pos 0
|
||||
#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */
|
||||
#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */
|
||||
#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */
|
||||
#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */
|
||||
#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */
|
||||
#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */
|
||||
#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */
|
||||
#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */
|
||||
#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */
|
||||
#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */
|
||||
#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */
|
||||
/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */
|
||||
#define PWM_CDTY_CDTY_Pos 0
|
||||
#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */
|
||||
#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
|
||||
/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */
|
||||
#define PWM_CDTYUPD_CDTYUPD_Pos 0
|
||||
#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */
|
||||
#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos)))
|
||||
/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */
|
||||
#define PWM_CPRD_CPRD_Pos 0
|
||||
#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */
|
||||
#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
|
||||
/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */
|
||||
#define PWM_CPRDUPD_CPRDUPD_Pos 0
|
||||
#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */
|
||||
#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos)))
|
||||
/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */
|
||||
#define PWM_CCNT_CNT_Pos 0
|
||||
#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */
|
||||
/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */
|
||||
#define PWM_DT_DTH_Pos 0
|
||||
#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */
|
||||
#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos)))
|
||||
#define PWM_DT_DTL_Pos 16
|
||||
#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */
|
||||
#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos)))
|
||||
/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */
|
||||
#define PWM_DTUPD_DTHUPD_Pos 0
|
||||
#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */
|
||||
#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos)))
|
||||
#define PWM_DTUPD_DTLUPD_Pos 16
|
||||
#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */
|
||||
#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_PWM_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_RSTC_COMPONENT_
|
||||
#define _SAM3U_RSTC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Reset Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_RSTC Reset Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Rstc hardware registers */
|
||||
typedef struct {
|
||||
WoReg RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */
|
||||
RoReg RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */
|
||||
RwReg RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */
|
||||
} Rstc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */
|
||||
#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */
|
||||
#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */
|
||||
#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */
|
||||
#define RSTC_CR_KEY_Pos 24
|
||||
#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) Password */
|
||||
#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos)))
|
||||
/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */
|
||||
#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */
|
||||
#define RSTC_SR_RSTTYP_Pos 8
|
||||
#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */
|
||||
#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */
|
||||
#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */
|
||||
/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */
|
||||
#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */
|
||||
#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */
|
||||
#define RSTC_MR_ERSTL_Pos 8
|
||||
#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */
|
||||
#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos)))
|
||||
#define RSTC_MR_KEY_Pos 24
|
||||
#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */
|
||||
#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_RSTC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_RTC_COMPONENT_
|
||||
#define _SAM3U_RTC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Real-time Clock */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_RTC Real-time Clock */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Rtc hardware registers */
|
||||
typedef struct {
|
||||
RwReg RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */
|
||||
RwReg RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */
|
||||
RwReg RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */
|
||||
RwReg RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */
|
||||
RwReg RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */
|
||||
RwReg RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */
|
||||
RoReg RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */
|
||||
WoReg RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */
|
||||
WoReg RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */
|
||||
WoReg RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */
|
||||
RoReg RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */
|
||||
RoReg RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */
|
||||
RoReg Reserved1[45];
|
||||
RwReg RTC_WPMR; /**< \brief (Rtc Offset: 0xE4) Write Protect Mode Register */
|
||||
} Rtc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */
|
||||
#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */
|
||||
#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */
|
||||
#define RTC_CR_TIMEVSEL_Pos 8
|
||||
#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */
|
||||
#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */
|
||||
#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */
|
||||
#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */
|
||||
#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */
|
||||
#define RTC_CR_CALEVSEL_Pos 16
|
||||
#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */
|
||||
#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */
|
||||
#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */
|
||||
#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */
|
||||
/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */
|
||||
#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */
|
||||
/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */
|
||||
#define RTC_TIMR_SEC_Pos 0
|
||||
#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */
|
||||
#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)))
|
||||
#define RTC_TIMR_MIN_Pos 8
|
||||
#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */
|
||||
#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)))
|
||||
#define RTC_TIMR_HOUR_Pos 16
|
||||
#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */
|
||||
#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)))
|
||||
#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */
|
||||
/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */
|
||||
#define RTC_CALR_CENT_Pos 0
|
||||
#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */
|
||||
#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)))
|
||||
#define RTC_CALR_YEAR_Pos 8
|
||||
#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */
|
||||
#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)))
|
||||
#define RTC_CALR_MONTH_Pos 16
|
||||
#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */
|
||||
#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)))
|
||||
#define RTC_CALR_DAY_Pos 21
|
||||
#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */
|
||||
#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)))
|
||||
#define RTC_CALR_DATE_Pos 24
|
||||
#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */
|
||||
#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)))
|
||||
/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */
|
||||
#define RTC_TIMALR_SEC_Pos 0
|
||||
#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */
|
||||
#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)))
|
||||
#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */
|
||||
#define RTC_TIMALR_MIN_Pos 8
|
||||
#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */
|
||||
#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)))
|
||||
#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */
|
||||
#define RTC_TIMALR_HOUR_Pos 16
|
||||
#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */
|
||||
#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)))
|
||||
#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */
|
||||
#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */
|
||||
/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */
|
||||
#define RTC_CALALR_MONTH_Pos 16
|
||||
#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */
|
||||
#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)))
|
||||
#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */
|
||||
#define RTC_CALALR_DATE_Pos 24
|
||||
#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */
|
||||
#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)))
|
||||
#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */
|
||||
/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */
|
||||
#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */
|
||||
#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */
|
||||
#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */
|
||||
#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */
|
||||
#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */
|
||||
/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */
|
||||
#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */
|
||||
#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */
|
||||
#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */
|
||||
#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */
|
||||
#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */
|
||||
/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */
|
||||
#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */
|
||||
#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */
|
||||
#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */
|
||||
#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */
|
||||
#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */
|
||||
/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */
|
||||
#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */
|
||||
#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */
|
||||
#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */
|
||||
#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */
|
||||
#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */
|
||||
/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */
|
||||
#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */
|
||||
#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */
|
||||
#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */
|
||||
#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */
|
||||
#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */
|
||||
/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */
|
||||
#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */
|
||||
#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */
|
||||
#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */
|
||||
#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */
|
||||
/* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define RTC_WPMR_WPEN (0x1u << 0) /**< \brief (RTC_WPMR) Write Protect Enable */
|
||||
#define RTC_WPMR_WPKEY_Pos 8
|
||||
#define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /**< \brief (RTC_WPMR) */
|
||||
#define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_RTC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_RTT_COMPONENT_
|
||||
#define _SAM3U_RTT_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Real-time Timer */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_RTT Real-time Timer */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Rtt hardware registers */
|
||||
typedef struct {
|
||||
RwReg RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */
|
||||
RwReg RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */
|
||||
RoReg RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */
|
||||
RoReg RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */
|
||||
} Rtt;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */
|
||||
#define RTT_MR_RTPRES_Pos 0
|
||||
#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */
|
||||
#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos)))
|
||||
#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
|
||||
#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
|
||||
#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
|
||||
/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
|
||||
#define RTT_AR_ALMV_Pos 0
|
||||
#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
|
||||
#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos)))
|
||||
/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */
|
||||
#define RTT_VR_CRTV_Pos 0
|
||||
#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */
|
||||
/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */
|
||||
#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */
|
||||
#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_RTT_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,458 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SMC_COMPONENT_
|
||||
#define _SAM3U_SMC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Static Memory Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_SMC Static Memory Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief SmcCs_number hardware registers */
|
||||
typedef struct {
|
||||
RwReg SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */
|
||||
RwReg SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */
|
||||
RwReg SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */
|
||||
RwReg SMC_TIMINGS; /**< \brief (SmcCs_number Offset: 0xC) SMC Timings Register */
|
||||
RwReg SMC_MODE; /**< \brief (SmcCs_number Offset: 0x10) SMC Mode Register */
|
||||
} SmcCs_number;
|
||||
/** \brief Smc hardware registers */
|
||||
#define SMCCS_NUMBER_NUMBER 4
|
||||
typedef struct {
|
||||
RwReg SMC_CFG; /**< \brief (Smc Offset: 0x000) SMC NFC Configuration Register */
|
||||
WoReg SMC_CTRL; /**< \brief (Smc Offset: 0x004) SMC NFC Control Register */
|
||||
RoReg SMC_SR; /**< \brief (Smc Offset: 0x008) SMC NFC Status Register */
|
||||
WoReg SMC_IER; /**< \brief (Smc Offset: 0x00C) SMC NFC Interrupt Enable Register */
|
||||
WoReg SMC_IDR; /**< \brief (Smc Offset: 0x010) SMC NFC Interrupt Disable Register */
|
||||
RoReg SMC_IMR; /**< \brief (Smc Offset: 0x014) SMC NFC Interrupt Mask Register */
|
||||
RwReg SMC_ADDR; /**< \brief (Smc Offset: 0x018) SMC NFC Address Cycle Zero Register */
|
||||
RwReg SMC_BANK; /**< \brief (Smc Offset: 0x01C) SMC Bank Address Register */
|
||||
WoReg SMC_ECC_CTRL; /**< \brief (Smc Offset: 0x020) SMC ECC Control Register */
|
||||
RwReg SMC_ECC_MD; /**< \brief (Smc Offset: 0x024) SMC ECC Mode Register */
|
||||
RoReg SMC_ECC_SR1; /**< \brief (Smc Offset: 0x028) SMC ECC Status 1 Register */
|
||||
RoReg SMC_ECC_PR0; /**< \brief (Smc Offset: 0x02C) SMC ECC Parity 0 Register */
|
||||
RoReg SMC_ECC_PR1; /**< \brief (Smc Offset: 0x030) SMC ECC parity 1 Register */
|
||||
RoReg SMC_ECC_SR2; /**< \brief (Smc Offset: 0x034) SMC ECC status 2 Register */
|
||||
RoReg SMC_ECC_PR2; /**< \brief (Smc Offset: 0x038) SMC ECC parity 2 Register */
|
||||
RoReg SMC_ECC_PR3; /**< \brief (Smc Offset: 0x03C) SMC ECC parity 3 Register */
|
||||
RoReg SMC_ECC_PR4; /**< \brief (Smc Offset: 0x040) SMC ECC parity 4 Register */
|
||||
RoReg SMC_ECC_PR5; /**< \brief (Smc Offset: 0x044) SMC ECC parity 5 Register */
|
||||
RoReg SMC_ECC_PR6; /**< \brief (Smc Offset: 0x048) SMC ECC parity 6 Register */
|
||||
RoReg SMC_ECC_PR7; /**< \brief (Smc Offset: 0x04C) SMC ECC parity 7 Register */
|
||||
RoReg SMC_ECC_PR8; /**< \brief (Smc Offset: 0x050) SMC ECC parity 8 Register */
|
||||
RoReg SMC_ECC_PR9; /**< \brief (Smc Offset: 0x054) SMC ECC parity 9 Register */
|
||||
RoReg SMC_ECC_PR10; /**< \brief (Smc Offset: 0x058) SMC ECC parity 10 Register */
|
||||
RoReg SMC_ECC_PR11; /**< \brief (Smc Offset: 0x05C) SMC ECC parity 11 Register */
|
||||
RoReg SMC_ECC_PR12; /**< \brief (Smc Offset: 0x060) SMC ECC parity 12 Register */
|
||||
RoReg SMC_ECC_PR13; /**< \brief (Smc Offset: 0x064) SMC ECC parity 13 Register */
|
||||
RoReg SMC_ECC_PR14; /**< \brief (Smc Offset: 0x068) SMC ECC parity 14 Register */
|
||||
RoReg SMC_ECC_PR15; /**< \brief (Smc Offset: 0x06C) SMC ECC parity 15 Register */
|
||||
SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x70) CS_number = 0 .. 3 */
|
||||
RoReg Reserved1[20];
|
||||
RwReg SMC_OCMS; /**< \brief (Smc Offset: 0x110) SMC OCMS Register */
|
||||
WoReg SMC_KEY1; /**< \brief (Smc Offset: 0x114) SMC OCMS KEY1 Register */
|
||||
WoReg SMC_KEY2; /**< \brief (Smc Offset: 0x118) SMC OCMS KEY2 Register */
|
||||
RoReg Reserved2[50];
|
||||
WoReg SMC_WPCR; /**< \brief (Smc Offset: 0x1E4) Write Protection Control Register */
|
||||
RoReg SMC_WPSR; /**< \brief (Smc Offset: 0x1E8) Write Protection Status Register */
|
||||
} Smc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SMC_CFG : (SMC Offset: 0x000) SMC NFC Configuration Register -------- */
|
||||
#define SMC_CFG_PAGESIZE_Pos 0
|
||||
#define SMC_CFG_PAGESIZE_Msk (0x3u << SMC_CFG_PAGESIZE_Pos) /**< \brief (SMC_CFG) */
|
||||
#define SMC_CFG_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_CFG) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
|
||||
#define SMC_CFG_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_CFG) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
|
||||
#define SMC_CFG_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_CFG) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
|
||||
#define SMC_CFG_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_CFG) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
|
||||
#define SMC_CFG_WSPARE (0x1u << 8) /**< \brief (SMC_CFG) Write Spare Area */
|
||||
#define SMC_CFG_RSPARE (0x1u << 9) /**< \brief (SMC_CFG) Read Spare Area */
|
||||
#define SMC_CFG_EDGECTRL (0x1u << 12) /**< \brief (SMC_CFG) Rising/Falling Edge Detection Control */
|
||||
#define SMC_CFG_RBEDGE (0x1u << 13) /**< \brief (SMC_CFG) Ready/Busy Signal Edge Detection */
|
||||
#define SMC_CFG_DTOCYC_Pos 16
|
||||
#define SMC_CFG_DTOCYC_Msk (0xfu << SMC_CFG_DTOCYC_Pos) /**< \brief (SMC_CFG) Data Timeout Cycle Number */
|
||||
#define SMC_CFG_DTOCYC(value) ((SMC_CFG_DTOCYC_Msk & ((value) << SMC_CFG_DTOCYC_Pos)))
|
||||
#define SMC_CFG_DTOMUL_Pos 20
|
||||
#define SMC_CFG_DTOMUL_Msk (0x7u << SMC_CFG_DTOMUL_Pos) /**< \brief (SMC_CFG) Data Timeout Multiplier */
|
||||
#define SMC_CFG_DTOMUL_X1 (0x0u << 20) /**< \brief (SMC_CFG) DTOCYC */
|
||||
#define SMC_CFG_DTOMUL_X16 (0x1u << 20) /**< \brief (SMC_CFG) DTOCYC x 16 */
|
||||
#define SMC_CFG_DTOMUL_X128 (0x2u << 20) /**< \brief (SMC_CFG) DTOCYC x 128 */
|
||||
#define SMC_CFG_DTOMUL_X256 (0x3u << 20) /**< \brief (SMC_CFG) DTOCYC x 256 */
|
||||
#define SMC_CFG_DTOMUL_X1024 (0x4u << 20) /**< \brief (SMC_CFG) DTOCYC x 1024 */
|
||||
#define SMC_CFG_DTOMUL_X4096 (0x5u << 20) /**< \brief (SMC_CFG) DTOCYC x 4096 */
|
||||
#define SMC_CFG_DTOMUL_X65536 (0x6u << 20) /**< \brief (SMC_CFG) DTOCYC x 65536 */
|
||||
#define SMC_CFG_DTOMUL_X1048576 (0x7u << 20) /**< \brief (SMC_CFG) DTOCYC x 1048576 */
|
||||
/* -------- SMC_CTRL : (SMC Offset: 0x004) SMC NFC Control Register -------- */
|
||||
#define SMC_CTRL_NFCEN (0x1u << 0) /**< \brief (SMC_CTRL) NAND Flash Controller Enable */
|
||||
#define SMC_CTRL_NFCDIS (0x1u << 1) /**< \brief (SMC_CTRL) NAND Flash Controller Disable */
|
||||
/* -------- SMC_SR : (SMC Offset: 0x008) SMC NFC Status Register -------- */
|
||||
#define SMC_SR_SMCSTS (0x1u << 0) /**< \brief (SMC_SR) NAND Flash Controller status (this field cannot be reset) */
|
||||
#define SMC_SR_RB_RISE (0x1u << 4) /**< \brief (SMC_SR) Selected Ready Busy Rising Edge Detected */
|
||||
#define SMC_SR_RB_FALL (0x1u << 5) /**< \brief (SMC_SR) Selected Ready Busy Falling Edge Detected */
|
||||
#define SMC_SR_NFCBUSY (0x1u << 8) /**< \brief (SMC_SR) NFC Busy (this field cannot be reset) */
|
||||
#define SMC_SR_NFCWR (0x1u << 11) /**< \brief (SMC_SR) NFC Write/Read Operation (this field cannot be reset) */
|
||||
#define SMC_SR_NFCSID_Pos 12
|
||||
#define SMC_SR_NFCSID_Msk (0x7u << SMC_SR_NFCSID_Pos) /**< \brief (SMC_SR) NFC Chip Select ID (this field cannot be reset) */
|
||||
#define SMC_SR_XFRDONE (0x1u << 16) /**< \brief (SMC_SR) NFC Data Transfer Terminated */
|
||||
#define SMC_SR_CMDDONE (0x1u << 17) /**< \brief (SMC_SR) Command Done */
|
||||
#define SMC_SR_DTOE (0x1u << 20) /**< \brief (SMC_SR) Data Timeout Error */
|
||||
#define SMC_SR_UNDEF (0x1u << 21) /**< \brief (SMC_SR) Undefined Area Error */
|
||||
#define SMC_SR_AWB (0x1u << 22) /**< \brief (SMC_SR) Accessing While Busy */
|
||||
#define SMC_SR_NFCASE (0x1u << 23) /**< \brief (SMC_SR) NFC Access Size Error */
|
||||
#define SMC_SR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_SR) Ready/Busy Line 0 Edge Detected */
|
||||
/* -------- SMC_IER : (SMC Offset: 0x00C) SMC NFC Interrupt Enable Register -------- */
|
||||
#define SMC_IER_RB_RISE (0x1u << 4) /**< \brief (SMC_IER) Ready Busy Rising Edge Detection Interrupt Enable */
|
||||
#define SMC_IER_RB_FALL (0x1u << 5) /**< \brief (SMC_IER) Ready Busy Falling Edge Detection Interrupt Enable */
|
||||
#define SMC_IER_XFRDONE (0x1u << 16) /**< \brief (SMC_IER) Transfer Done Interrupt Enable */
|
||||
#define SMC_IER_CMDDONE (0x1u << 17) /**< \brief (SMC_IER) Command Done Interrupt Enable */
|
||||
#define SMC_IER_DTOE (0x1u << 20) /**< \brief (SMC_IER) Data Timeout Error Interrupt Enable */
|
||||
#define SMC_IER_UNDEF (0x1u << 21) /**< \brief (SMC_IER) Undefined Area Access Interrupt Enable */
|
||||
#define SMC_IER_AWB (0x1u << 22) /**< \brief (SMC_IER) Accessing While Busy Interrupt Enable */
|
||||
#define SMC_IER_NFCASE (0x1u << 23) /**< \brief (SMC_IER) NFC Access Size Error Interrupt Enable */
|
||||
#define SMC_IER_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IER) Ready/Busy Line 0 Interrupt Enable */
|
||||
/* -------- SMC_IDR : (SMC Offset: 0x010) SMC NFC Interrupt Disable Register -------- */
|
||||
#define SMC_IDR_RB_RISE (0x1u << 4) /**< \brief (SMC_IDR) Ready Busy Rising Edge Detection Interrupt Disable */
|
||||
#define SMC_IDR_RB_FALL (0x1u << 5) /**< \brief (SMC_IDR) Ready Busy Falling Edge Detection Interrupt Disable */
|
||||
#define SMC_IDR_XFRDONE (0x1u << 16) /**< \brief (SMC_IDR) Transfer Done Interrupt Disable */
|
||||
#define SMC_IDR_CMDDONE (0x1u << 17) /**< \brief (SMC_IDR) Command Done Interrupt Disable */
|
||||
#define SMC_IDR_DTOE (0x1u << 20) /**< \brief (SMC_IDR) Data Timeout Error Interrupt Disable */
|
||||
#define SMC_IDR_UNDEF (0x1u << 21) /**< \brief (SMC_IDR) Undefined Area Access Interrupt Disable */
|
||||
#define SMC_IDR_AWB (0x1u << 22) /**< \brief (SMC_IDR) Accessing While Busy Interrupt Disable */
|
||||
#define SMC_IDR_NFCASE (0x1u << 23) /**< \brief (SMC_IDR) NFC Access Size Error Interrupt Disable */
|
||||
#define SMC_IDR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IDR) Ready/Busy Line 0 Interrupt Disable */
|
||||
/* -------- SMC_IMR : (SMC Offset: 0x014) SMC NFC Interrupt Mask Register -------- */
|
||||
#define SMC_IMR_RB_RISE (0x1u << 4) /**< \brief (SMC_IMR) Ready Busy Rising Edge Detection Interrupt Mask */
|
||||
#define SMC_IMR_RB_FALL (0x1u << 5) /**< \brief (SMC_IMR) Ready Busy Falling Edge Detection Interrupt Mask */
|
||||
#define SMC_IMR_XFRDONE (0x1u << 16) /**< \brief (SMC_IMR) Transfer Done Interrupt Mask */
|
||||
#define SMC_IMR_CMDDONE (0x1u << 17) /**< \brief (SMC_IMR) Command Done Interrupt Mask */
|
||||
#define SMC_IMR_DTOE (0x1u << 20) /**< \brief (SMC_IMR) Data Timeout Error Interrupt Mask */
|
||||
#define SMC_IMR_UNDEF (0x1u << 21) /**< \brief (SMC_IMR) Undefined Area Access Interrupt Mask5 */
|
||||
#define SMC_IMR_AWB (0x1u << 22) /**< \brief (SMC_IMR) Accessing While Busy Interrupt Mask */
|
||||
#define SMC_IMR_NFCASE (0x1u << 23) /**< \brief (SMC_IMR) NFC Access Size Error Interrupt Mask */
|
||||
#define SMC_IMR_RB_EDGE0 (0x1u << 24) /**< \brief (SMC_IMR) Ready/Busy Line 0 Interrupt Mask */
|
||||
/* -------- SMC_ADDR : (SMC Offset: 0x018) SMC NFC Address Cycle Zero Register -------- */
|
||||
#define SMC_ADDR_ADDR_CYCLE0_Pos 0
|
||||
#define SMC_ADDR_ADDR_CYCLE0_Msk (0xffu << SMC_ADDR_ADDR_CYCLE0_Pos) /**< \brief (SMC_ADDR) NAND Flash Array Address cycle 0 */
|
||||
#define SMC_ADDR_ADDR_CYCLE0(value) ((SMC_ADDR_ADDR_CYCLE0_Msk & ((value) << SMC_ADDR_ADDR_CYCLE0_Pos)))
|
||||
/* -------- SMC_BANK : (SMC Offset: 0x01C) SMC Bank Address Register -------- */
|
||||
#define SMC_BANK_BANK_Pos 0
|
||||
#define SMC_BANK_BANK_Msk (0x7u << SMC_BANK_BANK_Pos) /**< \brief (SMC_BANK) Bank Identifier */
|
||||
#define SMC_BANK_BANK(value) ((SMC_BANK_BANK_Msk & ((value) << SMC_BANK_BANK_Pos)))
|
||||
/* -------- SMC_ECC_CTRL : (SMC Offset: 0x020) SMC ECC Control Register -------- */
|
||||
#define SMC_ECC_CTRL_RST (0x1u << 0) /**< \brief (SMC_ECC_CTRL) Reset ECC */
|
||||
#define SMC_ECC_CTRL_SWRST (0x1u << 1) /**< \brief (SMC_ECC_CTRL) Software Reset */
|
||||
/* -------- SMC_ECC_MD : (SMC Offset: 0x024) SMC ECC Mode Register -------- */
|
||||
#define SMC_ECC_MD_ECC_PAGESIZE_Pos 0
|
||||
#define SMC_ECC_MD_ECC_PAGESIZE_Msk (0x3u << SMC_ECC_MD_ECC_PAGESIZE_Pos) /**< \brief (SMC_ECC_MD) ECC Page Size */
|
||||
#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x0u << 0) /**< \brief (SMC_ECC_MD) Main area 512 Bytes + Spare area 16 Bytes = 528 Bytes */
|
||||
#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x1u << 0) /**< \brief (SMC_ECC_MD) Main area 1024 Bytes + Spare area 32 Bytes = 1056 Bytes */
|
||||
#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x2u << 0) /**< \brief (SMC_ECC_MD) Main area 2048 Bytes + Spare area 64 Bytes = 2112 Bytes */
|
||||
#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x3u << 0) /**< \brief (SMC_ECC_MD) Main area 4096 Bytes + Spare area 128 Bytes = 4224 Bytes */
|
||||
#define SMC_ECC_MD_TYPCORREC_Pos 4
|
||||
#define SMC_ECC_MD_TYPCORREC_Msk (0x3u << SMC_ECC_MD_TYPCORREC_Pos) /**< \brief (SMC_ECC_MD) Type of Correction */
|
||||
#define SMC_ECC_MD_TYPCORREC_CPAGE (0x0u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for a page of 512/1024/2048/4096 Bytes (for 8 or 16-bit NAND Flash) */
|
||||
#define SMC_ECC_MD_TYPCORREC_C256B (0x1u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 256 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
|
||||
#define SMC_ECC_MD_TYPCORREC_C512B (0x2u << 4) /**< \brief (SMC_ECC_MD) 1 bit correction for 512 Bytes of data for a page of 512/2048/4096 bytes (for 8-bit NAND Flash only) */
|
||||
/* -------- SMC_ECC_SR1 : (SMC Offset: 0x028) SMC ECC Status 1 Register -------- */
|
||||
#define SMC_ECC_SR1_RECERR0 (0x1u << 0) /**< \brief (SMC_ECC_SR1) Recoverable Error */
|
||||
#define SMC_ECC_SR1_ECCERR0_Pos 1
|
||||
#define SMC_ECC_SR1_ECCERR0_Msk (0x3u << SMC_ECC_SR1_ECCERR0_Pos) /**< \brief (SMC_ECC_SR1) ECC Error */
|
||||
#define SMC_ECC_SR1_RECERR1 (0x1u << 4) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 256th and the 511th bytes or the 512nd and the 1023rd bytes */
|
||||
#define SMC_ECC_SR1_ECCERR1 (0x1u << 5) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
|
||||
#define SMC_ECC_SR1_MULERR1 (0x1u << 6) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 256th and the 511th bytes or between the 512nd and the 1023rd bytes */
|
||||
#define SMC_ECC_SR1_RECERR2 (0x1u << 8) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
|
||||
#define SMC_ECC_SR1_ECCERR2 (0x1u << 9) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
|
||||
#define SMC_ECC_SR1_MULERR2 (0x1u << 10) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 512nd and the 767th bytes or between the 1024th and the 1535th bytes */
|
||||
#define SMC_ECC_SR1_RECERR3 (0x1u << 12) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
|
||||
#define SMC_ECC_SR1_ECCERR3 (0x1u << 13) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
|
||||
#define SMC_ECC_SR1_MULERR3 (0x1u << 14) /**< \brief (SMC_ECC_SR1) Multiple Error in the page between the 768th and the 1023rd bytes or between the 1536th and the 2047th bytes */
|
||||
#define SMC_ECC_SR1_RECERR4 (0x1u << 16) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
|
||||
#define SMC_ECC_SR1_ECCERR4_Pos 17
|
||||
#define SMC_ECC_SR1_ECCERR4_Msk (0x3u << SMC_ECC_SR1_ECCERR4_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1024th and the 1279th bytes or between the 2048th and the 2559th bytes */
|
||||
#define SMC_ECC_SR1_RECERR5 (0x1u << 20) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
|
||||
#define SMC_ECC_SR1_ECCERR5_Pos 21
|
||||
#define SMC_ECC_SR1_ECCERR5_Msk (0x3u << SMC_ECC_SR1_ECCERR5_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1280th and the 1535th bytes or between the 2560th and the 3071st bytes */
|
||||
#define SMC_ECC_SR1_RECERR6 (0x1u << 24) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
|
||||
#define SMC_ECC_SR1_ECCERR6_Pos 25
|
||||
#define SMC_ECC_SR1_ECCERR6_Msk (0x3u << SMC_ECC_SR1_ECCERR6_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1536th and the 1791st bytes or between the 3072nd and the 3583rd bytes */
|
||||
#define SMC_ECC_SR1_RECERR7 (0x1u << 28) /**< \brief (SMC_ECC_SR1) Recoverable Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
|
||||
#define SMC_ECC_SR1_ECCERR7_Pos 29
|
||||
#define SMC_ECC_SR1_ECCERR7_Msk (0x3u << SMC_ECC_SR1_ECCERR7_Pos) /**< \brief (SMC_ECC_SR1) ECC Error in the page between the 1792nd and the 2047th bytes or between the 3584th and the 4095th bytes */
|
||||
/* -------- SMC_ECC_PR0 : (SMC Offset: 0x02C) SMC ECC Parity 0 Register -------- */
|
||||
#define SMC_ECC_PR0_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR0_BITADDR_Msk (0xfu << SMC_ECC_PR0_BITADDR_Pos) /**< \brief (SMC_ECC_PR0) Bit Address */
|
||||
#define SMC_ECC_PR0_WORDADDR_Pos 4
|
||||
#define SMC_ECC_PR0_WORDADDR_Msk (0xfffu << SMC_ECC_PR0_WORDADDR_Pos) /**< \brief (SMC_ECC_PR0) Word Address */
|
||||
#define SMC_ECC_PR0_BITADDR_W9BIT_Pos 0
|
||||
#define SMC_ECC_PR0_BITADDR_W9BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR0_WORDADDR_W9BIT_Pos 3
|
||||
#define SMC_ECC_PR0_WORDADDR_W9BIT_Msk (0x1ffu << SMC_ECC_PR0_WORDADDR_W9BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR0_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR0_NPARITY_Msk (0xfffu << SMC_ECC_PR0_NPARITY_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
|
||||
#define SMC_ECC_PR0_BITADDR_W8BIT_Pos 0
|
||||
#define SMC_ECC_PR0_BITADDR_W8BIT_Msk (0x7u << SMC_ECC_PR0_BITADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR0_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR0_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR0_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR0_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR0_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR0_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR0) Parity N */
|
||||
/* -------- SMC_ECC_PR1 : (SMC Offset: 0x030) SMC ECC parity 1 Register -------- */
|
||||
#define SMC_ECC_PR1_NPARITY_Pos 0
|
||||
#define SMC_ECC_PR1_NPARITY_Msk (0xffffu << SMC_ECC_PR1_NPARITY_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
|
||||
#define SMC_ECC_PR1_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR1_BITADDR_Msk (0x7u << SMC_ECC_PR1_BITADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR1_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR1_WORDADDR_Msk (0x1ffu << SMC_ECC_PR1_WORDADDR_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR1_NPARITY_W9BIT_Pos 12
|
||||
#define SMC_ECC_PR1_NPARITY_W9BIT_Msk (0xfffu << SMC_ECC_PR1_NPARITY_W9BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
|
||||
#define SMC_ECC_PR1_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR1_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR1_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR1_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR1_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR1_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR1) Parity N */
|
||||
/* -------- SMC_ECC_SR2 : (SMC Offset: 0x034) SMC ECC status 2 Register -------- */
|
||||
#define SMC_ECC_SR2_RECERR8 (0x1u << 0) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2048th and the 2303rd bytes */
|
||||
#define SMC_ECC_SR2_ECCERR8_Pos 1
|
||||
#define SMC_ECC_SR2_ECCERR8_Msk (0x3u << SMC_ECC_SR2_ECCERR8_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2048th and the 2303rd bytes */
|
||||
#define SMC_ECC_SR2_RECERR9 (0x1u << 4) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2304th and the 2559th bytes */
|
||||
#define SMC_ECC_SR2_ECCERR9 (0x1u << 5) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2304th and the 2559th bytes */
|
||||
#define SMC_ECC_SR2_MULERR9 (0x1u << 6) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2304th and the 2559th bytes */
|
||||
#define SMC_ECC_SR2_RECERR10 (0x1u << 8) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2560th and the 2815th bytes */
|
||||
#define SMC_ECC_SR2_ECCERR10 (0x1u << 9) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2560th and the 2815th bytes */
|
||||
#define SMC_ECC_SR2_MULERR10 (0x1u << 10) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2560th and the 2815th bytes */
|
||||
#define SMC_ECC_SR2_RECERR11 (0x1u << 12) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 2816th and the 3071st bytes */
|
||||
#define SMC_ECC_SR2_ECCERR11 (0x1u << 13) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 2816th and the 3071st bytes */
|
||||
#define SMC_ECC_SR2_MULERR11 (0x1u << 14) /**< \brief (SMC_ECC_SR2) Multiple Error in the page between the 2816th and the 3071st bytes */
|
||||
#define SMC_ECC_SR2_RECERR12 (0x1u << 16) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3072nd and the 3327th bytes */
|
||||
#define SMC_ECC_SR2_ECCERR12_Pos 17
|
||||
#define SMC_ECC_SR2_ECCERR12_Msk (0x3u << SMC_ECC_SR2_ECCERR12_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3072nd and the 3327th bytes */
|
||||
#define SMC_ECC_SR2_RECERR13 (0x1u << 20) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3328th and the 3583rd bytes */
|
||||
#define SMC_ECC_SR2_ECCERR13_Pos 21
|
||||
#define SMC_ECC_SR2_ECCERR13_Msk (0x3u << SMC_ECC_SR2_ECCERR13_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3328th and the 3583rd bytes */
|
||||
#define SMC_ECC_SR2_RECERR14 (0x1u << 24) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3584th and the 3839th bytes */
|
||||
#define SMC_ECC_SR2_ECCERR14_Pos 25
|
||||
#define SMC_ECC_SR2_ECCERR14_Msk (0x3u << SMC_ECC_SR2_ECCERR14_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3584th and the 3839th bytes */
|
||||
#define SMC_ECC_SR2_RECERR15 (0x1u << 28) /**< \brief (SMC_ECC_SR2) Recoverable Error in the page between the 3840th and the 4095th bytes */
|
||||
#define SMC_ECC_SR2_ECCERR15_Pos 29
|
||||
#define SMC_ECC_SR2_ECCERR15_Msk (0x3u << SMC_ECC_SR2_ECCERR15_Pos) /**< \brief (SMC_ECC_SR2) ECC Error in the page between the 3840th and the 4095th bytes */
|
||||
/* -------- SMC_ECC_PR2 : (SMC Offset: 0x038) SMC ECC parity 2 Register -------- */
|
||||
#define SMC_ECC_PR2_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR2_BITADDR_Msk (0x7u << SMC_ECC_PR2_BITADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR2_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR2_WORDADDR_Msk (0x1ffu << SMC_ECC_PR2_WORDADDR_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR2_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR2_NPARITY_Msk (0xfffu << SMC_ECC_PR2_NPARITY_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
|
||||
#define SMC_ECC_PR2_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR2_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR2_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR2_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR2_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR2_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR2) Parity N */
|
||||
/* -------- SMC_ECC_PR3 : (SMC Offset: 0x03C) SMC ECC parity 3 Register -------- */
|
||||
#define SMC_ECC_PR3_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR3_BITADDR_Msk (0x7u << SMC_ECC_PR3_BITADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR3_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR3_WORDADDR_Msk (0x1ffu << SMC_ECC_PR3_WORDADDR_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR3_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR3_NPARITY_Msk (0xfffu << SMC_ECC_PR3_NPARITY_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
|
||||
#define SMC_ECC_PR3_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR3_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR3_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR3_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR3_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR3_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR3) Parity N */
|
||||
/* -------- SMC_ECC_PR4 : (SMC Offset: 0x040) SMC ECC parity 4 Register -------- */
|
||||
#define SMC_ECC_PR4_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR4_BITADDR_Msk (0x7u << SMC_ECC_PR4_BITADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR4_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR4_WORDADDR_Msk (0x1ffu << SMC_ECC_PR4_WORDADDR_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR4_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR4_NPARITY_Msk (0xfffu << SMC_ECC_PR4_NPARITY_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
|
||||
#define SMC_ECC_PR4_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR4_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR4_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR4_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR4_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR4_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR4) Parity N */
|
||||
/* -------- SMC_ECC_PR5 : (SMC Offset: 0x044) SMC ECC parity 5 Register -------- */
|
||||
#define SMC_ECC_PR5_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR5_BITADDR_Msk (0x7u << SMC_ECC_PR5_BITADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR5_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR5_WORDADDR_Msk (0x1ffu << SMC_ECC_PR5_WORDADDR_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR5_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR5_NPARITY_Msk (0xfffu << SMC_ECC_PR5_NPARITY_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
|
||||
#define SMC_ECC_PR5_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR5_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR5_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR5_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR5_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR5_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR5) Parity N */
|
||||
/* -------- SMC_ECC_PR6 : (SMC Offset: 0x048) SMC ECC parity 6 Register -------- */
|
||||
#define SMC_ECC_PR6_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR6_BITADDR_Msk (0x7u << SMC_ECC_PR6_BITADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR6_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR6_WORDADDR_Msk (0x1ffu << SMC_ECC_PR6_WORDADDR_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR6_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR6_NPARITY_Msk (0xfffu << SMC_ECC_PR6_NPARITY_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
|
||||
#define SMC_ECC_PR6_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR6_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR6_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR6_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR6_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR6_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR6) Parity N */
|
||||
/* -------- SMC_ECC_PR7 : (SMC Offset: 0x04C) SMC ECC parity 7 Register -------- */
|
||||
#define SMC_ECC_PR7_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR7_BITADDR_Msk (0x7u << SMC_ECC_PR7_BITADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Bit Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR7_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR7_WORDADDR_Msk (0x1ffu << SMC_ECC_PR7_WORDADDR_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 512) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR7_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR7_NPARITY_Msk (0xfffu << SMC_ECC_PR7_NPARITY_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
|
||||
#define SMC_ECC_PR7_WORDADDR_W8BIT_Pos 3
|
||||
#define SMC_ECC_PR7_WORDADDR_W8BIT_Msk (0xffu << SMC_ECC_PR7_WORDADDR_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR7_NPARITY_W8BIT_Pos 12
|
||||
#define SMC_ECC_PR7_NPARITY_W8BIT_Msk (0x7ffu << SMC_ECC_PR7_NPARITY_W8BIT_Pos) /**< \brief (SMC_ECC_PR7) Parity N */
|
||||
/* -------- SMC_ECC_PR8 : (SMC Offset: 0x050) SMC ECC parity 8 Register -------- */
|
||||
#define SMC_ECC_PR8_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR8_BITADDR_Msk (0x7u << SMC_ECC_PR8_BITADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR8_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR8_WORDADDR_Msk (0xffu << SMC_ECC_PR8_WORDADDR_Pos) /**< \brief (SMC_ECC_PR8) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR8_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR8_NPARITY_Msk (0x7ffu << SMC_ECC_PR8_NPARITY_Pos) /**< \brief (SMC_ECC_PR8) Parity N */
|
||||
/* -------- SMC_ECC_PR9 : (SMC Offset: 0x054) SMC ECC parity 9 Register -------- */
|
||||
#define SMC_ECC_PR9_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR9_BITADDR_Msk (0x7u << SMC_ECC_PR9_BITADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR9_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR9_WORDADDR_Msk (0xffu << SMC_ECC_PR9_WORDADDR_Pos) /**< \brief (SMC_ECC_PR9) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR9_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR9_NPARITY_Msk (0x7ffu << SMC_ECC_PR9_NPARITY_Pos) /**< \brief (SMC_ECC_PR9) Parity N */
|
||||
/* -------- SMC_ECC_PR10 : (SMC Offset: 0x058) SMC ECC parity 10 Register -------- */
|
||||
#define SMC_ECC_PR10_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR10_BITADDR_Msk (0x7u << SMC_ECC_PR10_BITADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR10_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR10_WORDADDR_Msk (0xffu << SMC_ECC_PR10_WORDADDR_Pos) /**< \brief (SMC_ECC_PR10) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR10_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR10_NPARITY_Msk (0x7ffu << SMC_ECC_PR10_NPARITY_Pos) /**< \brief (SMC_ECC_PR10) Parity N */
|
||||
/* -------- SMC_ECC_PR11 : (SMC Offset: 0x05C) SMC ECC parity 11 Register -------- */
|
||||
#define SMC_ECC_PR11_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR11_BITADDR_Msk (0x7u << SMC_ECC_PR11_BITADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR11_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR11_WORDADDR_Msk (0xffu << SMC_ECC_PR11_WORDADDR_Pos) /**< \brief (SMC_ECC_PR11) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR11_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR11_NPARITY_Msk (0x7ffu << SMC_ECC_PR11_NPARITY_Pos) /**< \brief (SMC_ECC_PR11) Parity N */
|
||||
/* -------- SMC_ECC_PR12 : (SMC Offset: 0x060) SMC ECC parity 12 Register -------- */
|
||||
#define SMC_ECC_PR12_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR12_BITADDR_Msk (0x7u << SMC_ECC_PR12_BITADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR12_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR12_WORDADDR_Msk (0xffu << SMC_ECC_PR12_WORDADDR_Pos) /**< \brief (SMC_ECC_PR12) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR12_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR12_NPARITY_Msk (0x7ffu << SMC_ECC_PR12_NPARITY_Pos) /**< \brief (SMC_ECC_PR12) Parity N */
|
||||
/* -------- SMC_ECC_PR13 : (SMC Offset: 0x064) SMC ECC parity 13 Register -------- */
|
||||
#define SMC_ECC_PR13_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR13_BITADDR_Msk (0x7u << SMC_ECC_PR13_BITADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR13_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR13_WORDADDR_Msk (0xffu << SMC_ECC_PR13_WORDADDR_Pos) /**< \brief (SMC_ECC_PR13) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR13_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR13_NPARITY_Msk (0x7ffu << SMC_ECC_PR13_NPARITY_Pos) /**< \brief (SMC_ECC_PR13) Parity N */
|
||||
/* -------- SMC_ECC_PR14 : (SMC Offset: 0x068) SMC ECC parity 14 Register -------- */
|
||||
#define SMC_ECC_PR14_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR14_BITADDR_Msk (0x7u << SMC_ECC_PR14_BITADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR14_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR14_WORDADDR_Msk (0xffu << SMC_ECC_PR14_WORDADDR_Pos) /**< \brief (SMC_ECC_PR14) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR14_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR14_NPARITY_Msk (0x7ffu << SMC_ECC_PR14_NPARITY_Pos) /**< \brief (SMC_ECC_PR14) Parity N */
|
||||
/* -------- SMC_ECC_PR15 : (SMC Offset: 0x06C) SMC ECC parity 15 Register -------- */
|
||||
#define SMC_ECC_PR15_BITADDR_Pos 0
|
||||
#define SMC_ECC_PR15_BITADDR_Msk (0x7u << SMC_ECC_PR15_BITADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Bit Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR15_WORDADDR_Pos 3
|
||||
#define SMC_ECC_PR15_WORDADDR_Msk (0xffu << SMC_ECC_PR15_WORDADDR_Pos) /**< \brief (SMC_ECC_PR15) Corrupted Word Address in the Page between (i x 256) and ((i + 1) x 512) - 1) Bytes */
|
||||
#define SMC_ECC_PR15_NPARITY_Pos 12
|
||||
#define SMC_ECC_PR15_NPARITY_Msk (0x7ffu << SMC_ECC_PR15_NPARITY_Pos) /**< \brief (SMC_ECC_PR15) Parity N */
|
||||
/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */
|
||||
#define SMC_SETUP_NWE_SETUP_Pos 0
|
||||
#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */
|
||||
#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
|
||||
#define SMC_SETUP_NCS_WR_SETUP_Pos 8
|
||||
#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Write Access */
|
||||
#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
|
||||
#define SMC_SETUP_NRD_SETUP_Pos 16
|
||||
#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */
|
||||
#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
|
||||
#define SMC_SETUP_NCS_RD_SETUP_Pos 24
|
||||
#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in Read Access */
|
||||
#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
|
||||
/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */
|
||||
#define SMC_PULSE_NWE_PULSE_Pos 0
|
||||
#define SMC_PULSE_NWE_PULSE_Msk (0x3fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */
|
||||
#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
|
||||
#define SMC_PULSE_NCS_WR_PULSE_Pos 8
|
||||
#define SMC_PULSE_NCS_WR_PULSE_Msk (0x3fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */
|
||||
#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
|
||||
#define SMC_PULSE_NRD_PULSE_Pos 16
|
||||
#define SMC_PULSE_NRD_PULSE_Msk (0x3fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */
|
||||
#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
|
||||
#define SMC_PULSE_NCS_RD_PULSE_Pos 24
|
||||
#define SMC_PULSE_NCS_RD_PULSE_Msk (0x3fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */
|
||||
#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
|
||||
/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */
|
||||
#define SMC_CYCLE_NWE_CYCLE_Pos 0
|
||||
#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */
|
||||
#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
|
||||
#define SMC_CYCLE_NRD_CYCLE_Pos 16
|
||||
#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */
|
||||
#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
|
||||
/* -------- SMC_TIMINGS : (SMC Offset: N/A) SMC Timings Register -------- */
|
||||
#define SMC_TIMINGS_TCLR_Pos 0
|
||||
#define SMC_TIMINGS_TCLR_Msk (0xfu << SMC_TIMINGS_TCLR_Pos) /**< \brief (SMC_TIMINGS) CLE to REN Low Delay */
|
||||
#define SMC_TIMINGS_TCLR(value) ((SMC_TIMINGS_TCLR_Msk & ((value) << SMC_TIMINGS_TCLR_Pos)))
|
||||
#define SMC_TIMINGS_TADL_Pos 4
|
||||
#define SMC_TIMINGS_TADL_Msk (0xfu << SMC_TIMINGS_TADL_Pos) /**< \brief (SMC_TIMINGS) ALE to Data Start */
|
||||
#define SMC_TIMINGS_TADL(value) ((SMC_TIMINGS_TADL_Msk & ((value) << SMC_TIMINGS_TADL_Pos)))
|
||||
#define SMC_TIMINGS_TAR_Pos 8
|
||||
#define SMC_TIMINGS_TAR_Msk (0xfu << SMC_TIMINGS_TAR_Pos) /**< \brief (SMC_TIMINGS) ALE to REN Low Delay */
|
||||
#define SMC_TIMINGS_TAR(value) ((SMC_TIMINGS_TAR_Msk & ((value) << SMC_TIMINGS_TAR_Pos)))
|
||||
#define SMC_TIMINGS_OCMS (0x1u << 12) /**< \brief (SMC_TIMINGS) Off Chip Memory Scrambling Enable */
|
||||
#define SMC_TIMINGS_TRR_Pos 16
|
||||
#define SMC_TIMINGS_TRR_Msk (0xfu << SMC_TIMINGS_TRR_Pos) /**< \brief (SMC_TIMINGS) Ready to REN Low Delay */
|
||||
#define SMC_TIMINGS_TRR(value) ((SMC_TIMINGS_TRR_Msk & ((value) << SMC_TIMINGS_TRR_Pos)))
|
||||
#define SMC_TIMINGS_TWB_Pos 24
|
||||
#define SMC_TIMINGS_TWB_Msk (0xfu << SMC_TIMINGS_TWB_Pos) /**< \brief (SMC_TIMINGS) WEN High to REN to Busy */
|
||||
#define SMC_TIMINGS_TWB(value) ((SMC_TIMINGS_TWB_Msk & ((value) << SMC_TIMINGS_TWB_Pos)))
|
||||
#define SMC_TIMINGS_RBNSEL_Pos 28
|
||||
#define SMC_TIMINGS_RBNSEL_Msk (0x7u << SMC_TIMINGS_RBNSEL_Pos) /**< \brief (SMC_TIMINGS) Ready/Busy Line Selection */
|
||||
#define SMC_TIMINGS_RBNSEL(value) ((SMC_TIMINGS_RBNSEL_Msk & ((value) << SMC_TIMINGS_RBNSEL_Pos)))
|
||||
#define SMC_TIMINGS_NFSEL (0x1u << 31) /**< \brief (SMC_TIMINGS) NAND Flash Selection */
|
||||
/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */
|
||||
#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */
|
||||
#define SMC_MODE_READ_MODE_NCS_CTRL (0x0u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NCS signal. */
|
||||
#define SMC_MODE_READ_MODE_NRD_CTRL (0x1u << 0) /**< \brief (SMC_MODE) The Read operation is controlled by the NRD signal. */
|
||||
#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */
|
||||
#define SMC_MODE_WRITE_MODE_NCS_CTRL (0x0u << 1) /**< \brief (SMC_MODE) The Write operation is controller by the NCS signal. */
|
||||
#define SMC_MODE_WRITE_MODE_NWE_CTRL (0x1u << 1) /**< \brief (SMC_MODE) The Write operation is controlled by the NWE signal. */
|
||||
#define SMC_MODE_EXNW_MODE_Pos 4
|
||||
#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */
|
||||
#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */
|
||||
#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */
|
||||
#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */
|
||||
#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */
|
||||
#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */
|
||||
#define SMC_MODE_DBW_BIT_8 (0x0u << 12) /**< \brief (SMC_MODE) 8-bit bus */
|
||||
#define SMC_MODE_DBW_BIT_16 (0x1u << 12) /**< \brief (SMC_MODE) 16-bit bus */
|
||||
#define SMC_MODE_TDF_CYCLES_Pos 16
|
||||
#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */
|
||||
#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
|
||||
#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */
|
||||
/* -------- SMC_OCMS : (SMC Offset: 0x110) SMC OCMS Register -------- */
|
||||
#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */
|
||||
#define SMC_OCMS_SRSE (0x1u << 1) /**< \brief (SMC_OCMS) SRAM Scrambling Enable */
|
||||
/* -------- SMC_KEY1 : (SMC Offset: 0x114) SMC OCMS KEY1 Register -------- */
|
||||
#define SMC_KEY1_KEY1_Pos 0
|
||||
#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */
|
||||
#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
|
||||
/* -------- SMC_KEY2 : (SMC Offset: 0x118) SMC OCMS KEY2 Register -------- */
|
||||
#define SMC_KEY2_KEY2_Pos 0
|
||||
#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */
|
||||
#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
|
||||
/* -------- SMC_WPCR : (SMC Offset: 0x1E4) Write Protection Control Register -------- */
|
||||
#define SMC_WPCR_WP_EN (0x1u << 0) /**< \brief (SMC_WPCR) Write Protection Enable */
|
||||
#define SMC_WPCR_WP_KEY_Pos 8
|
||||
#define SMC_WPCR_WP_KEY_Msk (0xffffffu << SMC_WPCR_WP_KEY_Pos) /**< \brief (SMC_WPCR) Write Protection KEY password */
|
||||
#define SMC_WPCR_WP_KEY(value) ((SMC_WPCR_WP_KEY_Msk & ((value) << SMC_WPCR_WP_KEY_Pos)))
|
||||
/* -------- SMC_WPSR : (SMC Offset: 0x1E8) Write Protection Status Register -------- */
|
||||
#define SMC_WPSR_WP_VS_Pos 0
|
||||
#define SMC_WPSR_WP_VS_Msk (0xfu << SMC_WPSR_WP_VS_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Status */
|
||||
#define SMC_WPSR_WP_VSRC_Pos 8
|
||||
#define SMC_WPSR_WP_VSRC_Msk (0xffffu << SMC_WPSR_WP_VSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_SMC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SPI_COMPONENT_
|
||||
#define _SAM3U_SPI_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_SPI Serial Peripheral Interface */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Spi hardware registers */
|
||||
typedef struct {
|
||||
WoReg SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */
|
||||
RwReg SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */
|
||||
RoReg SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */
|
||||
WoReg SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */
|
||||
RoReg SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */
|
||||
WoReg SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */
|
||||
WoReg SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */
|
||||
RoReg SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */
|
||||
RoReg Reserved1[4];
|
||||
RwReg SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */
|
||||
RoReg Reserved2[41];
|
||||
RwReg SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */
|
||||
RoReg SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */
|
||||
} Spi;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */
|
||||
#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */
|
||||
#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */
|
||||
#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */
|
||||
#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */
|
||||
/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */
|
||||
#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */
|
||||
#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */
|
||||
#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */
|
||||
#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */
|
||||
#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */
|
||||
#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */
|
||||
#define SPI_MR_PCS_Pos 16
|
||||
#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */
|
||||
#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos)))
|
||||
#define SPI_MR_DLYBCS_Pos 24
|
||||
#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */
|
||||
#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos)))
|
||||
/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */
|
||||
#define SPI_RDR_RD_Pos 0
|
||||
#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */
|
||||
#define SPI_RDR_PCS_Pos 16
|
||||
#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */
|
||||
/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */
|
||||
#define SPI_TDR_TD_Pos 0
|
||||
#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */
|
||||
#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos)))
|
||||
#define SPI_TDR_PCS_Pos 16
|
||||
#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */
|
||||
#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos)))
|
||||
#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */
|
||||
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
|
||||
#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */
|
||||
#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */
|
||||
#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */
|
||||
#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */
|
||||
#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */
|
||||
#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */
|
||||
#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */
|
||||
#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */
|
||||
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
|
||||
#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */
|
||||
#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */
|
||||
#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */
|
||||
#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */
|
||||
#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */
|
||||
#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */
|
||||
#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */
|
||||
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
|
||||
#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */
|
||||
#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */
|
||||
#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */
|
||||
#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */
|
||||
#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */
|
||||
#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */
|
||||
#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */
|
||||
/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */
|
||||
#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */
|
||||
#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */
|
||||
#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */
|
||||
#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */
|
||||
#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */
|
||||
#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */
|
||||
#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */
|
||||
/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */
|
||||
#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */
|
||||
#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */
|
||||
#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
|
||||
#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */
|
||||
#define SPI_CSR_BITS_Pos 4
|
||||
#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */
|
||||
#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */
|
||||
#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */
|
||||
#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */
|
||||
#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */
|
||||
#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */
|
||||
#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */
|
||||
#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */
|
||||
#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */
|
||||
#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */
|
||||
#define SPI_CSR_SCBR_Pos 8
|
||||
#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */
|
||||
#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos)))
|
||||
#define SPI_CSR_DLYBS_Pos 16
|
||||
#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */
|
||||
#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos)))
|
||||
#define SPI_CSR_DLYBCT_Pos 24
|
||||
#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */
|
||||
#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos)))
|
||||
/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */
|
||||
#define SPI_WPMR_SPIWPEN (0x1u << 0) /**< \brief (SPI_WPMR) SPI Write Protection Enable */
|
||||
#define SPI_WPMR_SPIWPKEY_Pos 8
|
||||
#define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /**< \brief (SPI_WPMR) SPI Write Protection Key Password */
|
||||
#define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos)))
|
||||
/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */
|
||||
#define SPI_WPSR_SPIWPVS_Pos 0
|
||||
#define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Status */
|
||||
#define SPI_WPSR_SPIWPVSRC_Pos 8
|
||||
#define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /**< \brief (SPI_WPSR) SPI Write Protection Violation Source */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_SPI_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SSC_COMPONENT_
|
||||
#define _SAM3U_SSC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_SSC Synchronous Serial Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Ssc hardware registers */
|
||||
typedef struct {
|
||||
WoReg SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */
|
||||
RwReg SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */
|
||||
RoReg Reserved1[2];
|
||||
RwReg SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */
|
||||
RwReg SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */
|
||||
RwReg SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */
|
||||
RwReg SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */
|
||||
RoReg SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */
|
||||
WoReg SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */
|
||||
RoReg Reserved2[2];
|
||||
RoReg SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */
|
||||
RwReg SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */
|
||||
RwReg SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */
|
||||
RwReg SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */
|
||||
RoReg SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */
|
||||
WoReg SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */
|
||||
WoReg SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */
|
||||
RoReg SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */
|
||||
RoReg Reserved3[37];
|
||||
RwReg SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */
|
||||
RoReg SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */
|
||||
} Ssc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */
|
||||
#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */
|
||||
#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */
|
||||
#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */
|
||||
#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */
|
||||
#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */
|
||||
/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */
|
||||
#define SSC_CMR_DIV_Pos 0
|
||||
#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */
|
||||
#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
|
||||
/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */
|
||||
#define SSC_RCMR_CKS_Pos 0
|
||||
#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */
|
||||
#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */
|
||||
#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */
|
||||
#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */
|
||||
#define SSC_RCMR_CKO_Pos 2
|
||||
#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */
|
||||
#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */
|
||||
#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */
|
||||
#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
|
||||
#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */
|
||||
#define SSC_RCMR_CKG_Pos 6
|
||||
#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */
|
||||
#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */
|
||||
#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */
|
||||
#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */
|
||||
#define SSC_RCMR_START_Pos 8
|
||||
#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */
|
||||
#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */
|
||||
#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */
|
||||
#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */
|
||||
#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */
|
||||
#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */
|
||||
#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */
|
||||
#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */
|
||||
#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */
|
||||
#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */
|
||||
#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */
|
||||
#define SSC_RCMR_STTDLY_Pos 16
|
||||
#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */
|
||||
#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
|
||||
#define SSC_RCMR_PERIOD_Pos 24
|
||||
#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */
|
||||
#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
|
||||
/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */
|
||||
#define SSC_RFMR_DATLEN_Pos 0
|
||||
#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */
|
||||
#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
|
||||
#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */
|
||||
#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */
|
||||
#define SSC_RFMR_DATNB_Pos 8
|
||||
#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */
|
||||
#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
|
||||
#define SSC_RFMR_FSLEN_Pos 16
|
||||
#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */
|
||||
#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
|
||||
#define SSC_RFMR_FSOS_Pos 20
|
||||
#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */
|
||||
#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */
|
||||
#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */
|
||||
#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */
|
||||
#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */
|
||||
#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */
|
||||
#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */
|
||||
#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */
|
||||
#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */
|
||||
#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */
|
||||
#define SSC_RFMR_FSLEN_EXT_Pos 28
|
||||
#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */
|
||||
#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
|
||||
/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */
|
||||
#define SSC_TCMR_CKS_Pos 0
|
||||
#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */
|
||||
#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */
|
||||
#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */
|
||||
#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */
|
||||
#define SSC_TCMR_CKO_Pos 2
|
||||
#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */
|
||||
#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */
|
||||
#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */
|
||||
#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */
|
||||
#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */
|
||||
#define SSC_TCMR_CKG_Pos 6
|
||||
#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */
|
||||
#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */
|
||||
#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */
|
||||
#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */
|
||||
#define SSC_TCMR_START_Pos 8
|
||||
#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */
|
||||
#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */
|
||||
#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */
|
||||
#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */
|
||||
#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */
|
||||
#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */
|
||||
#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */
|
||||
#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */
|
||||
#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */
|
||||
#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */
|
||||
#define SSC_TCMR_STTDLY_Pos 16
|
||||
#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */
|
||||
#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
|
||||
#define SSC_TCMR_PERIOD_Pos 24
|
||||
#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */
|
||||
#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
|
||||
/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */
|
||||
#define SSC_TFMR_DATLEN_Pos 0
|
||||
#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */
|
||||
#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
|
||||
#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */
|
||||
#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */
|
||||
#define SSC_TFMR_DATNB_Pos 8
|
||||
#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */
|
||||
#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
|
||||
#define SSC_TFMR_FSLEN_Pos 16
|
||||
#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */
|
||||
#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
|
||||
#define SSC_TFMR_FSOS_Pos 20
|
||||
#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */
|
||||
#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */
|
||||
#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */
|
||||
#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */
|
||||
#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */
|
||||
#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */
|
||||
#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */
|
||||
#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */
|
||||
#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */
|
||||
#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */
|
||||
#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */
|
||||
#define SSC_TFMR_FSLEN_EXT_Pos 28
|
||||
#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */
|
||||
#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
|
||||
/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */
|
||||
#define SSC_RHR_RDAT_Pos 0
|
||||
#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */
|
||||
/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */
|
||||
#define SSC_THR_TDAT_Pos 0
|
||||
#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */
|
||||
#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
|
||||
/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */
|
||||
#define SSC_RSHR_RSDAT_Pos 0
|
||||
#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */
|
||||
/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */
|
||||
#define SSC_TSHR_TSDAT_Pos 0
|
||||
#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */
|
||||
#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
|
||||
/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */
|
||||
#define SSC_RC0R_CP0_Pos 0
|
||||
#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */
|
||||
#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
|
||||
/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */
|
||||
#define SSC_RC1R_CP1_Pos 0
|
||||
#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */
|
||||
#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
|
||||
/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */
|
||||
#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */
|
||||
#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */
|
||||
#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */
|
||||
#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */
|
||||
#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */
|
||||
#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */
|
||||
#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */
|
||||
#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */
|
||||
#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */
|
||||
#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */
|
||||
/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */
|
||||
#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */
|
||||
#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */
|
||||
#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */
|
||||
#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */
|
||||
#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */
|
||||
#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */
|
||||
#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */
|
||||
#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */
|
||||
/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */
|
||||
#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */
|
||||
#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */
|
||||
#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */
|
||||
#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */
|
||||
#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */
|
||||
#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */
|
||||
#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */
|
||||
#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */
|
||||
/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */
|
||||
#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */
|
||||
#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */
|
||||
#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */
|
||||
#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */
|
||||
#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */
|
||||
#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */
|
||||
#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */
|
||||
#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */
|
||||
/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */
|
||||
#define SSC_WPMR_WPKEY_Pos 8
|
||||
#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */
|
||||
#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
|
||||
/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */
|
||||
#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */
|
||||
#define SSC_WPSR_WPVSRC_Pos 8
|
||||
#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_SSC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SUPC_COMPONENT_
|
||||
#define _SAM3U_SUPC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Supply Controller */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_SUPC Supply Controller */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Supc hardware registers */
|
||||
typedef struct {
|
||||
WoReg SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */
|
||||
RwReg SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */
|
||||
RwReg SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */
|
||||
RwReg SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */
|
||||
RwReg SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */
|
||||
RoReg SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */
|
||||
} Supc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */
|
||||
#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */
|
||||
#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */
|
||||
#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */
|
||||
#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */
|
||||
#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */
|
||||
#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */
|
||||
#define SUPC_CR_KEY_Pos 24
|
||||
#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */
|
||||
#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)))
|
||||
/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */
|
||||
#define SUPC_SMMR_SMTH_Pos 0
|
||||
#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */
|
||||
#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */
|
||||
#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */
|
||||
#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */
|
||||
#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */
|
||||
#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */
|
||||
#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */
|
||||
#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */
|
||||
#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */
|
||||
#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */
|
||||
#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */
|
||||
#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */
|
||||
#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */
|
||||
#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */
|
||||
#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */
|
||||
#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */
|
||||
#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */
|
||||
#define SUPC_SMMR_SMSMPL_Pos 8
|
||||
#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */
|
||||
#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */
|
||||
#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */
|
||||
#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */
|
||||
#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */
|
||||
#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */
|
||||
#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */
|
||||
#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */
|
||||
#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */
|
||||
#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */
|
||||
#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */
|
||||
#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */
|
||||
/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */
|
||||
#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */
|
||||
#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */
|
||||
#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */
|
||||
#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */
|
||||
#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */
|
||||
#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */
|
||||
#define SUPC_MR_VDDIORDYONREG (0x1u << 14) /**< \brief (SUPC_MR) */
|
||||
#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */
|
||||
#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */
|
||||
#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */
|
||||
#define SUPC_MR_KEY_Pos 24
|
||||
#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */
|
||||
#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)))
|
||||
/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */
|
||||
#define SUPC_WUMR_FWUPEN (0x1u << 0) /**< \brief (SUPC_WUMR) Force Wake Up Enable */
|
||||
#define SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin has no wake up effect. */
|
||||
#define SUPC_WUMR_FWUPEN_ENABLE (0x1u << 0) /**< \brief (SUPC_WUMR) the Force Wake Up pin low forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */
|
||||
#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */
|
||||
#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */
|
||||
#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */
|
||||
#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */
|
||||
#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */
|
||||
#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */
|
||||
#define SUPC_WUMR_FWUPDBC_Pos 8
|
||||
#define SUPC_WUMR_FWUPDBC_Msk (0x7u << SUPC_WUMR_FWUPDBC_Pos) /**< \brief (SUPC_WUMR) Force Wake Up Debouncer Period */
|
||||
#define SUPC_WUMR_FWUPDBC_IMMEDIATE (0x0u << 8) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
|
||||
#define SUPC_WUMR_FWUPDBC_3_SCLK (0x1u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 3 SLCK periods */
|
||||
#define SUPC_WUMR_FWUPDBC_32_SCLK (0x2u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32 SLCK periods */
|
||||
#define SUPC_WUMR_FWUPDBC_512_SCLK (0x3u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 512 SLCK periods */
|
||||
#define SUPC_WUMR_FWUPDBC_4096_SCLK (0x4u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 4,096 SLCK periods */
|
||||
#define SUPC_WUMR_FWUPDBC_32768_SCLK (0x5u << 8) /**< \brief (SUPC_WUMR) FWUP shall be low for at least 32,768 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_Pos 12
|
||||
#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */
|
||||
#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */
|
||||
#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */
|
||||
#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */
|
||||
/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */
|
||||
#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */
|
||||
#define SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */
|
||||
#define SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */
|
||||
#define SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */
|
||||
#define SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */
|
||||
#define SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */
|
||||
#define SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */
|
||||
#define SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */
|
||||
#define SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */
|
||||
#define SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */
|
||||
#define SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */
|
||||
#define SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */
|
||||
#define SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */
|
||||
#define SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */
|
||||
#define SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */
|
||||
#define SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */
|
||||
#define SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */
|
||||
#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Transition 0 */
|
||||
#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Transition 1 */
|
||||
#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Transition 2 */
|
||||
#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Transition 3 */
|
||||
#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Transition 4 */
|
||||
#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Transition 5 */
|
||||
#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Transition 6 */
|
||||
#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Transition 7 */
|
||||
#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Transition 8 */
|
||||
#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Transition 9 */
|
||||
#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Transition 10 */
|
||||
#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Transition 11 */
|
||||
#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Transition 12 */
|
||||
#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Transition 13 */
|
||||
#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Transition 14 */
|
||||
#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Transition 15 */
|
||||
#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. */
|
||||
/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */
|
||||
#define SUPC_SR_FWUPS (0x1u << 0) /**< \brief (SUPC_SR) FWUP Wake Up Status */
|
||||
#define SUPC_SR_FWUPS_NO (0x0u << 0) /**< \brief (SUPC_SR) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_FWUPS_PRESENT (0x1u << 0) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */
|
||||
#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */
|
||||
#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */
|
||||
#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */
|
||||
#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */
|
||||
#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */
|
||||
#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */
|
||||
#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */
|
||||
#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. */
|
||||
#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. */
|
||||
#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */
|
||||
#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */
|
||||
#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */
|
||||
#define SUPC_SR_FWUPIS (0x1u << 12) /**< \brief (SUPC_SR) FWUP Input Status */
|
||||
#define SUPC_SR_FWUPIS_LOW (0x0u << 12) /**< \brief (SUPC_SR) FWUP input is tied low. */
|
||||
#define SUPC_SR_FWUPIS_HIGH (0x1u << 12) /**< \brief (SUPC_SR) FWUP input is tied high. */
|
||||
#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */
|
||||
#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */
|
||||
#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */
|
||||
#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */
|
||||
#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */
|
||||
#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */
|
||||
#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */
|
||||
#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */
|
||||
#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */
|
||||
#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */
|
||||
#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */
|
||||
#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */
|
||||
#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */
|
||||
#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */
|
||||
#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */
|
||||
#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */
|
||||
#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */
|
||||
#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_SUPC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_TC_COMPONENT_
|
||||
#define _SAM3U_TC_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Timer Counter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_TC Timer Counter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief TcChannel hardware registers */
|
||||
typedef struct {
|
||||
RwReg TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */
|
||||
RwReg TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */
|
||||
RoReg Reserved1[2];
|
||||
RwReg TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */
|
||||
RwReg TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */
|
||||
RwReg TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */
|
||||
RwReg TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */
|
||||
RwReg TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */
|
||||
RwReg TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */
|
||||
RwReg TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */
|
||||
RwReg TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */
|
||||
RoReg Reserved2[4];
|
||||
} TcChannel;
|
||||
/** \brief Tc hardware registers */
|
||||
#define TCCHANNEL_NUMBER 3
|
||||
typedef struct {
|
||||
TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */
|
||||
WoReg TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */
|
||||
RwReg TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */
|
||||
WoReg TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */
|
||||
WoReg TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */
|
||||
RoReg TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */
|
||||
RoReg TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */
|
||||
} Tc;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */
|
||||
#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */
|
||||
#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */
|
||||
#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */
|
||||
/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */
|
||||
#define TC_CMR_TCCLKS_Pos 0
|
||||
#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */
|
||||
#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */
|
||||
#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */
|
||||
#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */
|
||||
#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */
|
||||
#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */
|
||||
#define TC_CMR_BURST_Pos 4
|
||||
#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */
|
||||
#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
|
||||
#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */
|
||||
#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */
|
||||
#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */
|
||||
#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */
|
||||
#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */
|
||||
#define TC_CMR_ETRGEDG_Pos 8
|
||||
#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */
|
||||
#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */
|
||||
#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
|
||||
#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
|
||||
#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
|
||||
#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */
|
||||
#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */
|
||||
#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */
|
||||
#define TC_CMR_LDRA_Pos 16
|
||||
#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */
|
||||
#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */
|
||||
#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */
|
||||
#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */
|
||||
#define TC_CMR_LDRB_Pos 18
|
||||
#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */
|
||||
#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */
|
||||
#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */
|
||||
#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */
|
||||
#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */
|
||||
#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */
|
||||
#define TC_CMR_EEVTEDG_Pos 8
|
||||
#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */
|
||||
#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */
|
||||
#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */
|
||||
#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */
|
||||
#define TC_CMR_EEVT_Pos 10
|
||||
#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */
|
||||
#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */
|
||||
#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */
|
||||
#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */
|
||||
#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */
|
||||
#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */
|
||||
#define TC_CMR_WAVSEL_Pos 13
|
||||
#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */
|
||||
#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */
|
||||
#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */
|
||||
#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */
|
||||
#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */
|
||||
#define TC_CMR_ACPA_Pos 16
|
||||
#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */
|
||||
#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_ACPC_Pos 18
|
||||
#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */
|
||||
#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_AEEVT_Pos 20
|
||||
#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */
|
||||
#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_ASWTRG_Pos 22
|
||||
#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */
|
||||
#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BCPB_Pos 24
|
||||
#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */
|
||||
#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BCPC_Pos 26
|
||||
#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */
|
||||
#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BEEVT_Pos 28
|
||||
#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */
|
||||
#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */
|
||||
#define TC_CMR_BSWTRG_Pos 30
|
||||
#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */
|
||||
#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */
|
||||
#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */
|
||||
#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */
|
||||
#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */
|
||||
/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */
|
||||
#define TC_CV_CV_Pos 0
|
||||
#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */
|
||||
/* -------- TC_RA : (TC Offset: N/A) Register A -------- */
|
||||
#define TC_RA_RA_Pos 0
|
||||
#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */
|
||||
#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos)))
|
||||
/* -------- TC_RB : (TC Offset: N/A) Register B -------- */
|
||||
#define TC_RB_RB_Pos 0
|
||||
#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */
|
||||
#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos)))
|
||||
/* -------- TC_RC : (TC Offset: N/A) Register C -------- */
|
||||
#define TC_RC_RC_Pos 0
|
||||
#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */
|
||||
#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos)))
|
||||
/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */
|
||||
#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */
|
||||
#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */
|
||||
#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */
|
||||
#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */
|
||||
#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */
|
||||
#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */
|
||||
#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */
|
||||
#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */
|
||||
#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */
|
||||
#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */
|
||||
#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */
|
||||
/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */
|
||||
#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */
|
||||
#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */
|
||||
#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */
|
||||
#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */
|
||||
#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */
|
||||
#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */
|
||||
#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */
|
||||
#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */
|
||||
/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */
|
||||
#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */
|
||||
#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */
|
||||
#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */
|
||||
#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */
|
||||
#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */
|
||||
#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */
|
||||
#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */
|
||||
#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */
|
||||
/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */
|
||||
#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */
|
||||
#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */
|
||||
#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */
|
||||
#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */
|
||||
#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */
|
||||
#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */
|
||||
#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */
|
||||
#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */
|
||||
/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */
|
||||
#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */
|
||||
/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */
|
||||
#define TC_BMR_TC0XC0S_Pos 0
|
||||
#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */
|
||||
#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */
|
||||
#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */
|
||||
#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */
|
||||
#define TC_BMR_TC1XC1S_Pos 2
|
||||
#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */
|
||||
#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */
|
||||
#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */
|
||||
#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */
|
||||
#define TC_BMR_TC2XC2S_Pos 4
|
||||
#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */
|
||||
#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */
|
||||
#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */
|
||||
#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */
|
||||
#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */
|
||||
#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */
|
||||
#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */
|
||||
#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */
|
||||
#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */
|
||||
#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */
|
||||
#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */
|
||||
#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */
|
||||
#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */
|
||||
#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */
|
||||
#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */
|
||||
#define TC_BMR_MAXFILT_Pos 20
|
||||
#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */
|
||||
#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos)))
|
||||
/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */
|
||||
#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */
|
||||
#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */
|
||||
#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */
|
||||
/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */
|
||||
#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */
|
||||
#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */
|
||||
#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */
|
||||
/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */
|
||||
#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */
|
||||
#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */
|
||||
#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */
|
||||
/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */
|
||||
#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */
|
||||
#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */
|
||||
#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */
|
||||
#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_TC_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_TWI_COMPONENT_
|
||||
#define _SAM3U_TWI_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Two-wire Interface */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_TWI Two-wire Interface */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Twi hardware registers */
|
||||
typedef struct {
|
||||
WoReg TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */
|
||||
RwReg TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */
|
||||
RwReg TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */
|
||||
RwReg TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */
|
||||
RwReg TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */
|
||||
RoReg Reserved1[3];
|
||||
RoReg TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */
|
||||
WoReg TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */
|
||||
WoReg TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */
|
||||
RoReg TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */
|
||||
RoReg TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */
|
||||
WoReg TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */
|
||||
RoReg Reserved2[50];
|
||||
RwReg TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */
|
||||
RwReg TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */
|
||||
RwReg TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */
|
||||
RoReg TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */
|
||||
} Twi;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */
|
||||
#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */
|
||||
#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */
|
||||
#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */
|
||||
#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */
|
||||
#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */
|
||||
#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */
|
||||
#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */
|
||||
#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */
|
||||
/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */
|
||||
#define TWI_MMR_IADRSZ_Pos 8
|
||||
#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */
|
||||
#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */
|
||||
#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */
|
||||
#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */
|
||||
#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */
|
||||
#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */
|
||||
#define TWI_MMR_DADR_Pos 16
|
||||
#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */
|
||||
#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos)))
|
||||
/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */
|
||||
#define TWI_SMR_SADR_Pos 16
|
||||
#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */
|
||||
#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos)))
|
||||
/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */
|
||||
#define TWI_IADR_IADR_Pos 0
|
||||
#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */
|
||||
#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos)))
|
||||
/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */
|
||||
#define TWI_CWGR_CLDIV_Pos 0
|
||||
#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */
|
||||
#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos)))
|
||||
#define TWI_CWGR_CHDIV_Pos 8
|
||||
#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */
|
||||
#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos)))
|
||||
#define TWI_CWGR_CKDIV_Pos 16
|
||||
#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */
|
||||
#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos)))
|
||||
/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */
|
||||
#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */
|
||||
#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */
|
||||
#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */
|
||||
#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */
|
||||
#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */
|
||||
#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */
|
||||
#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */
|
||||
#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */
|
||||
#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */
|
||||
#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */
|
||||
#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */
|
||||
#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */
|
||||
#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */
|
||||
#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */
|
||||
#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */
|
||||
/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */
|
||||
#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */
|
||||
#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */
|
||||
#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */
|
||||
#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */
|
||||
#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */
|
||||
#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */
|
||||
#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */
|
||||
#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */
|
||||
#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */
|
||||
#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */
|
||||
#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */
|
||||
#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */
|
||||
#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */
|
||||
#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */
|
||||
/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */
|
||||
#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */
|
||||
#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */
|
||||
#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */
|
||||
#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */
|
||||
#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */
|
||||
#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */
|
||||
#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */
|
||||
#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */
|
||||
#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */
|
||||
#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */
|
||||
#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */
|
||||
#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */
|
||||
#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */
|
||||
#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */
|
||||
/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */
|
||||
#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */
|
||||
#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */
|
||||
#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */
|
||||
#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */
|
||||
#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */
|
||||
#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */
|
||||
#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */
|
||||
#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */
|
||||
#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */
|
||||
#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */
|
||||
#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */
|
||||
#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */
|
||||
#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */
|
||||
#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */
|
||||
/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */
|
||||
#define TWI_RHR_RXDATA_Pos 0
|
||||
#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */
|
||||
/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */
|
||||
#define TWI_THR_TXDATA_Pos 0
|
||||
#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */
|
||||
#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos)))
|
||||
/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define TWI_RPR_RXPTR_Pos 0
|
||||
#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */
|
||||
#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos)))
|
||||
/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */
|
||||
#define TWI_RCR_RXCTR_Pos 0
|
||||
#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */
|
||||
#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos)))
|
||||
/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define TWI_TPR_TXPTR_Pos 0
|
||||
#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */
|
||||
#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos)))
|
||||
/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define TWI_TCR_TXCTR_Pos 0
|
||||
#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */
|
||||
#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos)))
|
||||
/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define TWI_RNPR_RXNPTR_Pos 0
|
||||
#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */
|
||||
#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos)))
|
||||
/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define TWI_RNCR_RXNCTR_Pos 0
|
||||
#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */
|
||||
#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos)))
|
||||
/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define TWI_TNPR_TXNPTR_Pos 0
|
||||
#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */
|
||||
#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos)))
|
||||
/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define TWI_TNCR_TXNCTR_Pos 0
|
||||
#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */
|
||||
#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos)))
|
||||
/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */
|
||||
#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */
|
||||
#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */
|
||||
#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */
|
||||
#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */
|
||||
#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */
|
||||
#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_TWI_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_UART_COMPONENT_
|
||||
#define _SAM3U_UART_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_UART Universal Asynchronous Receiver Transmitter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Uart hardware registers */
|
||||
typedef struct {
|
||||
WoReg UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */
|
||||
RwReg UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */
|
||||
WoReg UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */
|
||||
WoReg UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */
|
||||
RoReg UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */
|
||||
RoReg UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */
|
||||
RoReg UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */
|
||||
WoReg UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */
|
||||
RwReg UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */
|
||||
RoReg Reserved1[55];
|
||||
RwReg UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */
|
||||
RwReg UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */
|
||||
RwReg UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */
|
||||
RoReg UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */
|
||||
} Uart;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
|
||||
#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */
|
||||
#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */
|
||||
#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */
|
||||
#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */
|
||||
#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */
|
||||
#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */
|
||||
#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */
|
||||
/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
|
||||
#define UART_MR_PAR_Pos 9
|
||||
#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */
|
||||
#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */
|
||||
#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */
|
||||
#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */
|
||||
#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */
|
||||
#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */
|
||||
#define UART_MR_CHMODE_Pos 14
|
||||
#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */
|
||||
#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */
|
||||
#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */
|
||||
#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */
|
||||
#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */
|
||||
/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
|
||||
#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */
|
||||
#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */
|
||||
#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */
|
||||
#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */
|
||||
#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */
|
||||
#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */
|
||||
#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */
|
||||
#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */
|
||||
#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */
|
||||
#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */
|
||||
/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
|
||||
#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */
|
||||
#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */
|
||||
#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */
|
||||
#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */
|
||||
#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */
|
||||
#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */
|
||||
#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */
|
||||
#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */
|
||||
#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */
|
||||
#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */
|
||||
/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
|
||||
#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */
|
||||
#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */
|
||||
#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */
|
||||
#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */
|
||||
#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */
|
||||
#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */
|
||||
#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */
|
||||
#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */
|
||||
#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */
|
||||
#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */
|
||||
/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
|
||||
#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */
|
||||
#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */
|
||||
#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */
|
||||
#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */
|
||||
#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */
|
||||
#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */
|
||||
#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */
|
||||
#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */
|
||||
#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */
|
||||
#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */
|
||||
/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
|
||||
#define UART_RHR_RXCHR_Pos 0
|
||||
#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */
|
||||
/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
|
||||
#define UART_THR_TXCHR_Pos 0
|
||||
#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */
|
||||
#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
|
||||
/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
|
||||
#define UART_BRGR_CD_Pos 0
|
||||
#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */
|
||||
#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
|
||||
/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define UART_RPR_RXPTR_Pos 0
|
||||
#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */
|
||||
#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
|
||||
/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
|
||||
#define UART_RCR_RXCTR_Pos 0
|
||||
#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */
|
||||
#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
|
||||
/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define UART_TPR_TXPTR_Pos 0
|
||||
#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */
|
||||
#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
|
||||
/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define UART_TCR_TXCTR_Pos 0
|
||||
#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */
|
||||
#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
|
||||
/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define UART_RNPR_RXNPTR_Pos 0
|
||||
#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */
|
||||
#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
|
||||
/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define UART_RNCR_RXNCTR_Pos 0
|
||||
#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */
|
||||
#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
|
||||
/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define UART_TNPR_TXNPTR_Pos 0
|
||||
#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */
|
||||
#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
|
||||
/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define UART_TNCR_TXNCTR_Pos 0
|
||||
#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */
|
||||
#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
|
||||
/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
|
||||
#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */
|
||||
#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */
|
||||
#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */
|
||||
#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
|
||||
#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */
|
||||
#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_UART_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,348 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_UDPHS_COMPONENT_
|
||||
#define _SAM3U_UDPHS_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR USB High Speed Device Port */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_UDPHS USB High Speed Device Port */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief UdphsDma hardware registers */
|
||||
typedef struct {
|
||||
RwReg UDPHS_DMANXTDSC; /**< \brief (UdphsDma Offset: 0x0) UDPHS DMA Next Descriptor Address Register */
|
||||
RwReg UDPHS_DMAADDRESS; /**< \brief (UdphsDma Offset: 0x4) UDPHS DMA Channel Address Register */
|
||||
RwReg UDPHS_DMACONTROL; /**< \brief (UdphsDma Offset: 0x8) UDPHS DMA Channel Control Register */
|
||||
RwReg UDPHS_DMASTATUS; /**< \brief (UdphsDma Offset: 0xC) UDPHS DMA Channel Status Register */
|
||||
} UdphsDma;
|
||||
/** \brief UdphsEpt hardware registers */
|
||||
typedef struct {
|
||||
RwReg UDPHS_EPTCFG; /**< \brief (UdphsEpt Offset: 0x0) UDPHS Endpoint Configuration Register */
|
||||
RwReg UDPHS_EPTCTLENB; /**< \brief (UdphsEpt Offset: 0x4) UDPHS Endpoint Control Enable Register */
|
||||
RwReg UDPHS_EPTCTLDIS; /**< \brief (UdphsEpt Offset: 0x8) UDPHS Endpoint Control Disable Register */
|
||||
RwReg UDPHS_EPTCTL; /**< \brief (UdphsEpt Offset: 0xC) UDPHS Endpoint Control Register */
|
||||
RoReg Reserved1[1];
|
||||
RwReg UDPHS_EPTSETSTA; /**< \brief (UdphsEpt Offset: 0x14) UDPHS Endpoint Set Status Register */
|
||||
RwReg UDPHS_EPTCLRSTA; /**< \brief (UdphsEpt Offset: 0x18) UDPHS Endpoint Clear Status Register */
|
||||
RwReg UDPHS_EPTSTA; /**< \brief (UdphsEpt Offset: 0x1C) UDPHS Endpoint Status Register */
|
||||
} UdphsEpt;
|
||||
/** \brief Udphs hardware registers */
|
||||
#define UDPHSEPT_NUMBER 7
|
||||
#define UDPHSDMA_NUMBER 6
|
||||
typedef struct {
|
||||
RwReg UDPHS_CTRL; /**< \brief (Udphs Offset: 0x00) UDPHS Control Register */
|
||||
RoReg UDPHS_FNUM; /**< \brief (Udphs Offset: 0x04) UDPHS Frame Number Register */
|
||||
RoReg Reserved1[2];
|
||||
RwReg UDPHS_IEN; /**< \brief (Udphs Offset: 0x10) UDPHS Interrupt Enable Register */
|
||||
RoReg UDPHS_INTSTA; /**< \brief (Udphs Offset: 0x14) UDPHS Interrupt Status Register */
|
||||
WoReg UDPHS_CLRINT; /**< \brief (Udphs Offset: 0x18) UDPHS Clear Interrupt Register */
|
||||
WoReg UDPHS_EPTRST; /**< \brief (Udphs Offset: 0x1C) UDPHS Endpoints Reset Register */
|
||||
RoReg Reserved2[48];
|
||||
RwReg UDPHS_TST; /**< \brief (Udphs Offset: 0xE0) UDPHS Test Register */
|
||||
RoReg Reserved3[3];
|
||||
RoReg UDPHS_IPNAME1; /**< \brief (Udphs Offset: 0xF0) UDPHS Name1 Register */
|
||||
RoReg UDPHS_IPNAME2; /**< \brief (Udphs Offset: 0xF4) UDPHS Name2 Register */
|
||||
RoReg UDPHS_IPFEATURES; /**< \brief (Udphs Offset: 0xF8) UDPHS Features Register */
|
||||
RoReg Reserved4[1];
|
||||
UdphsEpt UDPHS_EPT[UDPHSEPT_NUMBER]; /**< \brief (Udphs Offset: 0x100) endpoint = 0 .. 6 */
|
||||
RoReg Reserved5[72];
|
||||
UdphsDma UDPHS_DMA[UDPHSDMA_NUMBER]; /**< \brief (Udphs Offset: 0x300) channel = 0 .. 5 */
|
||||
} Udphs;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- UDPHS_CTRL : (UDPHS Offset: 0x00) UDPHS Control Register -------- */
|
||||
#define UDPHS_CTRL_DEV_ADDR_Pos 0
|
||||
#define UDPHS_CTRL_DEV_ADDR_Msk (0x7fu << UDPHS_CTRL_DEV_ADDR_Pos) /**< \brief (UDPHS_CTRL) UDPHS Address */
|
||||
#define UDPHS_CTRL_DEV_ADDR(value) ((UDPHS_CTRL_DEV_ADDR_Msk & ((value) << UDPHS_CTRL_DEV_ADDR_Pos)))
|
||||
#define UDPHS_CTRL_FADDR_EN (0x1u << 7) /**< \brief (UDPHS_CTRL) Function Address Enable */
|
||||
#define UDPHS_CTRL_EN_UDPHS (0x1u << 8) /**< \brief (UDPHS_CTRL) UDPHS Enable */
|
||||
#define UDPHS_CTRL_DETACH (0x1u << 9) /**< \brief (UDPHS_CTRL) Detach Command */
|
||||
#define UDPHS_CTRL_REWAKEUP (0x1u << 10) /**< \brief (UDPHS_CTRL) Send Remote Wake Up */
|
||||
#define UDPHS_CTRL_PULLD_DIS (0x1u << 11) /**< \brief (UDPHS_CTRL) Pull-Down Disable */
|
||||
/* -------- UDPHS_FNUM : (UDPHS Offset: 0x04) UDPHS Frame Number Register -------- */
|
||||
#define UDPHS_FNUM_MICRO_FRAME_NUM_Pos 0
|
||||
#define UDPHS_FNUM_MICRO_FRAME_NUM_Msk (0x7u << UDPHS_FNUM_MICRO_FRAME_NUM_Pos) /**< \brief (UDPHS_FNUM) Microframe Number */
|
||||
#define UDPHS_FNUM_FRAME_NUMBER_Pos 3
|
||||
#define UDPHS_FNUM_FRAME_NUMBER_Msk (0x7ffu << UDPHS_FNUM_FRAME_NUMBER_Pos) /**< \brief (UDPHS_FNUM) Frame Number as defined in the Packet Field Formats */
|
||||
#define UDPHS_FNUM_FNUM_ERR (0x1u << 31) /**< \brief (UDPHS_FNUM) Frame Number CRC Error */
|
||||
/* -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- */
|
||||
#define UDPHS_IEN_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_IEN) Suspend Interrupt Enable */
|
||||
#define UDPHS_IEN_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_IEN) Micro-SOF Interrupt Enable */
|
||||
#define UDPHS_IEN_INT_SOF (0x1u << 3) /**< \brief (UDPHS_IEN) SOF Interrupt Enable */
|
||||
#define UDPHS_IEN_ENDRESET (0x1u << 4) /**< \brief (UDPHS_IEN) End Of Reset Interrupt Enable */
|
||||
#define UDPHS_IEN_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_IEN) Wake Up CPU Interrupt Enable */
|
||||
#define UDPHS_IEN_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_IEN) End Of Resume Interrupt Enable */
|
||||
#define UDPHS_IEN_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_IEN) Upstream Resume Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_0 (0x1u << 8) /**< \brief (UDPHS_IEN) Endpoint 0 Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_1 (0x1u << 9) /**< \brief (UDPHS_IEN) Endpoint 1 Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_2 (0x1u << 10) /**< \brief (UDPHS_IEN) Endpoint 2 Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_3 (0x1u << 11) /**< \brief (UDPHS_IEN) Endpoint 3 Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_4 (0x1u << 12) /**< \brief (UDPHS_IEN) Endpoint 4 Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_5 (0x1u << 13) /**< \brief (UDPHS_IEN) Endpoint 5 Interrupt Enable */
|
||||
#define UDPHS_IEN_EPT_6 (0x1u << 14) /**< \brief (UDPHS_IEN) Endpoint 6 Interrupt Enable */
|
||||
#define UDPHS_IEN_DMA_1 (0x1u << 25) /**< \brief (UDPHS_IEN) DMA Channel 1 Interrupt Enable */
|
||||
#define UDPHS_IEN_DMA_2 (0x1u << 26) /**< \brief (UDPHS_IEN) DMA Channel 2 Interrupt Enable */
|
||||
#define UDPHS_IEN_DMA_3 (0x1u << 27) /**< \brief (UDPHS_IEN) DMA Channel 3 Interrupt Enable */
|
||||
#define UDPHS_IEN_DMA_4 (0x1u << 28) /**< \brief (UDPHS_IEN) DMA Channel 4 Interrupt Enable */
|
||||
#define UDPHS_IEN_DMA_5 (0x1u << 29) /**< \brief (UDPHS_IEN) DMA Channel 5 Interrupt Enable */
|
||||
#define UDPHS_IEN_DMA_6 (0x1u << 30) /**< \brief (UDPHS_IEN) DMA Channel 6 Interrupt Enable */
|
||||
/* -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- */
|
||||
#define UDPHS_INTSTA_SPEED (0x1u << 0) /**< \brief (UDPHS_INTSTA) Speed Status */
|
||||
#define UDPHS_INTSTA_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_INTSTA) Suspend Interrupt */
|
||||
#define UDPHS_INTSTA_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_INTSTA) Micro Start Of Frame Interrupt */
|
||||
#define UDPHS_INTSTA_INT_SOF (0x1u << 3) /**< \brief (UDPHS_INTSTA) Start Of Frame Interrupt */
|
||||
#define UDPHS_INTSTA_ENDRESET (0x1u << 4) /**< \brief (UDPHS_INTSTA) End Of Reset Interrupt */
|
||||
#define UDPHS_INTSTA_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_INTSTA) Wake Up CPU Interrupt */
|
||||
#define UDPHS_INTSTA_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_INTSTA) End Of Resume Interrupt */
|
||||
#define UDPHS_INTSTA_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_INTSTA) Upstream Resume Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_0 (0x1u << 8) /**< \brief (UDPHS_INTSTA) Endpoint 0 Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_1 (0x1u << 9) /**< \brief (UDPHS_INTSTA) Endpoint 1 Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_2 (0x1u << 10) /**< \brief (UDPHS_INTSTA) Endpoint 2 Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_3 (0x1u << 11) /**< \brief (UDPHS_INTSTA) Endpoint 3 Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_4 (0x1u << 12) /**< \brief (UDPHS_INTSTA) Endpoint 4 Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_5 (0x1u << 13) /**< \brief (UDPHS_INTSTA) Endpoint 5 Interrupt */
|
||||
#define UDPHS_INTSTA_EPT_6 (0x1u << 14) /**< \brief (UDPHS_INTSTA) Endpoint 6 Interrupt */
|
||||
#define UDPHS_INTSTA_DMA_1 (0x1u << 25) /**< \brief (UDPHS_INTSTA) DMA Channel 1 Interrupt */
|
||||
#define UDPHS_INTSTA_DMA_2 (0x1u << 26) /**< \brief (UDPHS_INTSTA) DMA Channel 2 Interrupt */
|
||||
#define UDPHS_INTSTA_DMA_3 (0x1u << 27) /**< \brief (UDPHS_INTSTA) DMA Channel 3 Interrupt */
|
||||
#define UDPHS_INTSTA_DMA_4 (0x1u << 28) /**< \brief (UDPHS_INTSTA) DMA Channel 4 Interrupt */
|
||||
#define UDPHS_INTSTA_DMA_5 (0x1u << 29) /**< \brief (UDPHS_INTSTA) DMA Channel 5 Interrupt */
|
||||
#define UDPHS_INTSTA_DMA_6 (0x1u << 30) /**< \brief (UDPHS_INTSTA) DMA Channel 6 Interrupt */
|
||||
/* -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- */
|
||||
#define UDPHS_CLRINT_DET_SUSPD (0x1u << 1) /**< \brief (UDPHS_CLRINT) Suspend Interrupt Clear */
|
||||
#define UDPHS_CLRINT_MICRO_SOF (0x1u << 2) /**< \brief (UDPHS_CLRINT) Micro Start Of Frame Interrupt Clear */
|
||||
#define UDPHS_CLRINT_INT_SOF (0x1u << 3) /**< \brief (UDPHS_CLRINT) Start Of Frame Interrupt Clear */
|
||||
#define UDPHS_CLRINT_ENDRESET (0x1u << 4) /**< \brief (UDPHS_CLRINT) End Of Reset Interrupt Clear */
|
||||
#define UDPHS_CLRINT_WAKE_UP (0x1u << 5) /**< \brief (UDPHS_CLRINT) Wake Up CPU Interrupt Clear */
|
||||
#define UDPHS_CLRINT_ENDOFRSM (0x1u << 6) /**< \brief (UDPHS_CLRINT) End Of Resume Interrupt Clear */
|
||||
#define UDPHS_CLRINT_UPSTR_RES (0x1u << 7) /**< \brief (UDPHS_CLRINT) Upstream Resume Interrupt Clear */
|
||||
/* -------- UDPHS_EPTRST : (UDPHS Offset: 0x1C) UDPHS Endpoints Reset Register -------- */
|
||||
#define UDPHS_EPTRST_EPT_0 (0x1u << 0) /**< \brief (UDPHS_EPTRST) Endpoint 0 Reset */
|
||||
#define UDPHS_EPTRST_EPT_1 (0x1u << 1) /**< \brief (UDPHS_EPTRST) Endpoint 1 Reset */
|
||||
#define UDPHS_EPTRST_EPT_2 (0x1u << 2) /**< \brief (UDPHS_EPTRST) Endpoint 2 Reset */
|
||||
#define UDPHS_EPTRST_EPT_3 (0x1u << 3) /**< \brief (UDPHS_EPTRST) Endpoint 3 Reset */
|
||||
#define UDPHS_EPTRST_EPT_4 (0x1u << 4) /**< \brief (UDPHS_EPTRST) Endpoint 4 Reset */
|
||||
#define UDPHS_EPTRST_EPT_5 (0x1u << 5) /**< \brief (UDPHS_EPTRST) Endpoint 5 Reset */
|
||||
#define UDPHS_EPTRST_EPT_6 (0x1u << 6) /**< \brief (UDPHS_EPTRST) Endpoint 6 Reset */
|
||||
/* -------- UDPHS_TST : (UDPHS Offset: 0xE0) UDPHS Test Register -------- */
|
||||
#define UDPHS_TST_SPEED_CFG_Pos 0
|
||||
#define UDPHS_TST_SPEED_CFG_Msk (0x3u << UDPHS_TST_SPEED_CFG_Pos) /**< \brief (UDPHS_TST) Speed Configuration */
|
||||
#define UDPHS_TST_SPEED_CFG_NORMAL (0x0u << 0) /**< \brief (UDPHS_TST) Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode */
|
||||
#define UDPHS_TST_SPEED_CFG_HIGH_SPEED (0x2u << 0) /**< \brief (UDPHS_TST) Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. */
|
||||
#define UDPHS_TST_SPEED_CFG_FULL_SPEED (0x3u << 0) /**< \brief (UDPHS_TST) Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. */
|
||||
#define UDPHS_TST_TST_J (0x1u << 2) /**< \brief (UDPHS_TST) Test J Mode */
|
||||
#define UDPHS_TST_TST_K (0x1u << 3) /**< \brief (UDPHS_TST) Test K Mode */
|
||||
#define UDPHS_TST_TST_PKT (0x1u << 4) /**< \brief (UDPHS_TST) Test Packet Mode */
|
||||
#define UDPHS_TST_OPMODE2 (0x1u << 5) /**< \brief (UDPHS_TST) OpMode2 */
|
||||
/* -------- UDPHS_IPNAME1 : (UDPHS Offset: 0xF0) UDPHS Name1 Register -------- */
|
||||
#define UDPHS_IPNAME1_IP_NAME1_Pos 0
|
||||
#define UDPHS_IPNAME1_IP_NAME1_Msk (0xffffffffu << UDPHS_IPNAME1_IP_NAME1_Pos) /**< \brief (UDPHS_IPNAME1) */
|
||||
/* -------- UDPHS_IPNAME2 : (UDPHS Offset: 0xF4) UDPHS Name2 Register -------- */
|
||||
#define UDPHS_IPNAME2_IP_NAME2_Pos 0
|
||||
#define UDPHS_IPNAME2_IP_NAME2_Msk (0xffffffffu << UDPHS_IPNAME2_IP_NAME2_Pos) /**< \brief (UDPHS_IPNAME2) */
|
||||
/* -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xF8) UDPHS Features Register -------- */
|
||||
#define UDPHS_IPFEATURES_EPT_NBR_MAX_Pos 0
|
||||
#define UDPHS_IPFEATURES_EPT_NBR_MAX_Msk (0xfu << UDPHS_IPFEATURES_EPT_NBR_MAX_Pos) /**< \brief (UDPHS_IPFEATURES) Max Number of Endpoints */
|
||||
#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos 4
|
||||
#define UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk (0x7u << UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) /**< \brief (UDPHS_IPFEATURES) Number of DMA Channels */
|
||||
#define UDPHS_IPFEATURES_DMA_B_SIZ (0x1u << 7) /**< \brief (UDPHS_IPFEATURES) DMA Buffer Size */
|
||||
#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos 8
|
||||
#define UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Msk (0xfu << UDPHS_IPFEATURES_DMA_FIFO_WORD_DEPTH_Pos) /**< \brief (UDPHS_IPFEATURES) DMA FIFO Depth in Words */
|
||||
#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos 12
|
||||
#define UDPHS_IPFEATURES_FIFO_MAX_SIZE_Msk (0x7u << UDPHS_IPFEATURES_FIFO_MAX_SIZE_Pos) /**< \brief (UDPHS_IPFEATURES) DPRAM Size */
|
||||
#define UDPHS_IPFEATURES_BW_DPRAM (0x1u << 15) /**< \brief (UDPHS_IPFEATURES) DPRAM Byte Write Capability */
|
||||
#define UDPHS_IPFEATURES_DATAB16_8 (0x1u << 16) /**< \brief (UDPHS_IPFEATURES) UTMI DataBus16_8 */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_1 (0x1u << 17) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_2 (0x1u << 18) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_3 (0x1u << 19) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_4 (0x1u << 20) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_5 (0x1u << 21) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_6 (0x1u << 22) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_7 (0x1u << 23) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_8 (0x1u << 24) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_9 (0x1u << 25) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_10 (0x1u << 26) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_11 (0x1u << 27) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_12 (0x1u << 28) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_13 (0x1u << 29) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_14 (0x1u << 30) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
#define UDPHS_IPFEATURES_ISO_EPT_15 (0x1u << 31) /**< \brief (UDPHS_IPFEATURES) Endpointx High Bandwidth Isochronous Capability */
|
||||
/* -------- UDPHS_EPTCFG : (UDPHS Offset: N/A) UDPHS Endpoint Configuration Register -------- */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_Pos 0
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_Msk (0x7u << UDPHS_EPTCFG_EPT_SIZE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Size */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_8 (0x0u << 0) /**< \brief (UDPHS_EPTCFG) 8 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_16 (0x1u << 0) /**< \brief (UDPHS_EPTCFG) 16 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_32 (0x2u << 0) /**< \brief (UDPHS_EPTCFG) 32 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_64 (0x3u << 0) /**< \brief (UDPHS_EPTCFG) 64 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_128 (0x4u << 0) /**< \brief (UDPHS_EPTCFG) 128 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_256 (0x5u << 0) /**< \brief (UDPHS_EPTCFG) 256 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_512 (0x6u << 0) /**< \brief (UDPHS_EPTCFG) 512 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_SIZE_1024 (0x7u << 0) /**< \brief (UDPHS_EPTCFG) 1024 bytes */
|
||||
#define UDPHS_EPTCFG_EPT_DIR (0x1u << 3) /**< \brief (UDPHS_EPTCFG) Endpoint Direction */
|
||||
#define UDPHS_EPTCFG_EPT_TYPE_Pos 4
|
||||
#define UDPHS_EPTCFG_EPT_TYPE_Msk (0x3u << UDPHS_EPTCFG_EPT_TYPE_Pos) /**< \brief (UDPHS_EPTCFG) Endpoint Type */
|
||||
#define UDPHS_EPTCFG_EPT_TYPE_CTRL8 (0x0u << 4) /**< \brief (UDPHS_EPTCFG) Control endpoint */
|
||||
#define UDPHS_EPTCFG_EPT_TYPE_ISO (0x1u << 4) /**< \brief (UDPHS_EPTCFG) Isochronous endpoint */
|
||||
#define UDPHS_EPTCFG_EPT_TYPE_BULK (0x2u << 4) /**< \brief (UDPHS_EPTCFG) Bulk endpoint */
|
||||
#define UDPHS_EPTCFG_EPT_TYPE_INT (0x3u << 4) /**< \brief (UDPHS_EPTCFG) Interrupt endpoint */
|
||||
#define UDPHS_EPTCFG_BK_NUMBER_Pos 6
|
||||
#define UDPHS_EPTCFG_BK_NUMBER_Msk (0x3u << UDPHS_EPTCFG_BK_NUMBER_Pos) /**< \brief (UDPHS_EPTCFG) Number of Banks */
|
||||
#define UDPHS_EPTCFG_BK_NUMBER_0 (0x0u << 6) /**< \brief (UDPHS_EPTCFG) Zero bank, the endpoint is not mapped in memory */
|
||||
#define UDPHS_EPTCFG_BK_NUMBER_1 (0x1u << 6) /**< \brief (UDPHS_EPTCFG) One bank (bank 0) */
|
||||
#define UDPHS_EPTCFG_BK_NUMBER_2 (0x2u << 6) /**< \brief (UDPHS_EPTCFG) Double bank (Ping-Pong: bank0/bank1) */
|
||||
#define UDPHS_EPTCFG_BK_NUMBER_3 (0x3u << 6) /**< \brief (UDPHS_EPTCFG) Triple bank (bank0/bank1/bank2) */
|
||||
#define UDPHS_EPTCFG_NB_TRANS_Pos 8
|
||||
#define UDPHS_EPTCFG_NB_TRANS_Msk (0x3u << UDPHS_EPTCFG_NB_TRANS_Pos) /**< \brief (UDPHS_EPTCFG) Number Of Transaction per Microframe */
|
||||
#define UDPHS_EPTCFG_NB_TRANS(value) ((UDPHS_EPTCFG_NB_TRANS_Msk & ((value) << UDPHS_EPTCFG_NB_TRANS_Pos)))
|
||||
#define UDPHS_EPTCFG_EPT_MAPD (0x1u << 31) /**< \brief (UDPHS_EPTCFG) Endpoint Mapped */
|
||||
/* -------- UDPHS_EPTCTLENB : (UDPHS Offset: N/A) UDPHS Endpoint Control Enable Register -------- */
|
||||
#define UDPHS_EPTCTLENB_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLENB) Endpoint Enable */
|
||||
#define UDPHS_EPTCTLENB_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLENB) Packet Auto-Valid Enable */
|
||||
#define UDPHS_EPTCTLENB_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLENB) Interrupts Disable DMA */
|
||||
#define UDPHS_EPTCTLENB_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLENB) NYET Disable (Only for High Speed Bulk OUT endpoints) */
|
||||
#define UDPHS_EPTCTLENB_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLENB) DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
|
||||
#define UDPHS_EPTCTLENB_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLENB) MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) */
|
||||
#define UDPHS_EPTCTLENB_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLENB) Overflow Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLENB) Received OUT Data Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLENB) Transmitted IN Data Complete Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLENB) TX Packet Ready/Transaction Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLENB) Received SETUP/Error Flow Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLENB) Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLENB) NAKIN/Bank Flush Error Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLENB) NAKOUT Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLENB) Busy Bank Interrupt Enable */
|
||||
#define UDPHS_EPTCTLENB_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLENB) Short Packet Send/Short Packet Interrupt Enable */
|
||||
/* -------- UDPHS_EPTCTLDIS : (UDPHS Offset: N/A) UDPHS Endpoint Control Disable Register -------- */
|
||||
#define UDPHS_EPTCTLDIS_EPT_DISABL (0x1u << 0) /**< \brief (UDPHS_EPTCTLDIS) Endpoint Disable */
|
||||
#define UDPHS_EPTCTLDIS_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTLDIS) Packet Auto-Valid Disable */
|
||||
#define UDPHS_EPTCTLDIS_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTLDIS) Interrupts Disable DMA */
|
||||
#define UDPHS_EPTCTLDIS_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTLDIS) NYET Enable (Only for High Speed Bulk OUT endpoints) */
|
||||
#define UDPHS_EPTCTLDIS_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTLDIS) DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
|
||||
#define UDPHS_EPTCTLDIS_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTLDIS) MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) */
|
||||
#define UDPHS_EPTCTLDIS_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTLDIS) Overflow Error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTLDIS) Received OUT Data Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTLDIS) Transmitted IN Data Complete Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTLDIS) TX Packet Ready/Transaction Error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTLDIS) Received SETUP/Error Flow Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTLDIS) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTLDIS) NAKIN/bank flush error Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTLDIS) NAKOUT Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTLDIS) Busy Bank Interrupt Disable */
|
||||
#define UDPHS_EPTCTLDIS_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTLDIS) Short Packet Interrupt Disable */
|
||||
/* -------- UDPHS_EPTCTL : (UDPHS Offset: N/A) UDPHS Endpoint Control Register -------- */
|
||||
#define UDPHS_EPTCTL_EPT_ENABL (0x1u << 0) /**< \brief (UDPHS_EPTCTL) Endpoint Enable */
|
||||
#define UDPHS_EPTCTL_AUTO_VALID (0x1u << 1) /**< \brief (UDPHS_EPTCTL) Packet Auto-Valid Enabled (Not for CONTROL Endpoints) */
|
||||
#define UDPHS_EPTCTL_INTDIS_DMA (0x1u << 3) /**< \brief (UDPHS_EPTCTL) Interrupt Disables DMA */
|
||||
#define UDPHS_EPTCTL_NYET_DIS (0x1u << 4) /**< \brief (UDPHS_EPTCTL) NYET Disable (Only for High Speed Bulk OUT endpoints) */
|
||||
#define UDPHS_EPTCTL_DATAX_RX (0x1u << 6) /**< \brief (UDPHS_EPTCTL) DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
|
||||
#define UDPHS_EPTCTL_MDATA_RX (0x1u << 7) /**< \brief (UDPHS_EPTCTL) MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) */
|
||||
#define UDPHS_EPTCTL_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTCTL) Overflow Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCTL) Received OUT Data Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCTL) Transmitted IN Data Complete Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTCTL) TX Packet Ready/Transaction Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCTL) Received SETUP/Error Flow Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCTL) Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCTL) NAKIN/Bank Flush Error Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCTL) NAKOUT Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_BUSY_BANK (0x1u << 18) /**< \brief (UDPHS_EPTCTL) Busy Bank Interrupt Enabled */
|
||||
#define UDPHS_EPTCTL_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTCTL) Short Packet Interrupt Enabled */
|
||||
/* -------- UDPHS_EPTSETSTA : (UDPHS Offset: N/A) UDPHS Endpoint Set Status Register -------- */
|
||||
#define UDPHS_EPTSETSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSETSTA) Stall Handshake Request Set */
|
||||
#define UDPHS_EPTSETSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSETSTA) KILL Bank Set (for IN Endpoint) */
|
||||
#define UDPHS_EPTSETSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSETSTA) TX Packet Ready Set */
|
||||
/* -------- UDPHS_EPTCLRSTA : (UDPHS Offset: N/A) UDPHS Endpoint Clear Status Register -------- */
|
||||
#define UDPHS_EPTCLRSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTCLRSTA) Stall Handshake Request Clear */
|
||||
#define UDPHS_EPTCLRSTA_TOGGLESQ (0x1u << 6) /**< \brief (UDPHS_EPTCLRSTA) Data Toggle Clear */
|
||||
#define UDPHS_EPTCLRSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTCLRSTA) Received OUT Data Clear */
|
||||
#define UDPHS_EPTCLRSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTCLRSTA) Transmitted IN Data Complete Clear */
|
||||
#define UDPHS_EPTCLRSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
|
||||
#define UDPHS_EPTCLRSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTCLRSTA) Received SETUP/Error Flow Clear */
|
||||
#define UDPHS_EPTCLRSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
|
||||
#define UDPHS_EPTCLRSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTCLRSTA) Stall Sent/Number of Transaction Error Clear */
|
||||
#define UDPHS_EPTCLRSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
|
||||
#define UDPHS_EPTCLRSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTCLRSTA) NAKIN/Bank Flush Error Clear */
|
||||
#define UDPHS_EPTCLRSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTCLRSTA) NAKOUT Clear */
|
||||
/* -------- UDPHS_EPTSTA : (UDPHS Offset: N/A) UDPHS Endpoint Status Register -------- */
|
||||
#define UDPHS_EPTSTA_FRCESTALL (0x1u << 5) /**< \brief (UDPHS_EPTSTA) Stall Handshake Request */
|
||||
#define UDPHS_EPTSTA_TOGGLESQ_STA_Pos 6
|
||||
#define UDPHS_EPTSTA_TOGGLESQ_STA_Msk (0x3u << UDPHS_EPTSTA_TOGGLESQ_STA_Pos) /**< \brief (UDPHS_EPTSTA) Toggle Sequencing */
|
||||
#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA0 (0x0u << 6) /**< \brief (UDPHS_EPTSTA) DATA0 */
|
||||
#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA1 (0x1u << 6) /**< \brief (UDPHS_EPTSTA) DATA1 */
|
||||
#define UDPHS_EPTSTA_TOGGLESQ_STA_DATA2 (0x2u << 6) /**< \brief (UDPHS_EPTSTA) Data2 (only for High Bandwidth Isochronous Endpoint) */
|
||||
#define UDPHS_EPTSTA_TOGGLESQ_STA_MDATA (0x3u << 6) /**< \brief (UDPHS_EPTSTA) MData (only for High Bandwidth Isochronous Endpoint) */
|
||||
#define UDPHS_EPTSTA_ERR_OVFLW (0x1u << 8) /**< \brief (UDPHS_EPTSTA) Overflow Error */
|
||||
#define UDPHS_EPTSTA_RX_BK_RDY (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
|
||||
#define UDPHS_EPTSTA_KILL_BANK (0x1u << 9) /**< \brief (UDPHS_EPTSTA) Received OUT Data/KILL Bank */
|
||||
#define UDPHS_EPTSTA_TX_COMPLT (0x1u << 10) /**< \brief (UDPHS_EPTSTA) Transmitted IN Data Complete */
|
||||
#define UDPHS_EPTSTA_TX_PK_RDY (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
|
||||
#define UDPHS_EPTSTA_ERR_TRANS (0x1u << 11) /**< \brief (UDPHS_EPTSTA) TX Packet Ready/Transaction Error */
|
||||
#define UDPHS_EPTSTA_RX_SETUP (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
|
||||
#define UDPHS_EPTSTA_ERR_FL_ISO (0x1u << 12) /**< \brief (UDPHS_EPTSTA) Received SETUP/Error Flow */
|
||||
#define UDPHS_EPTSTA_STALL_SNT (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
|
||||
#define UDPHS_EPTSTA_ERR_CRISO (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
|
||||
#define UDPHS_EPTSTA_ERR_NBTRA (0x1u << 13) /**< \brief (UDPHS_EPTSTA) Stall Sent/CRC ISO Error/Number of Transaction Error */
|
||||
#define UDPHS_EPTSTA_NAK_IN (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
|
||||
#define UDPHS_EPTSTA_ERR_FLUSH (0x1u << 14) /**< \brief (UDPHS_EPTSTA) NAK IN/Bank Flush Error */
|
||||
#define UDPHS_EPTSTA_NAK_OUT (0x1u << 15) /**< \brief (UDPHS_EPTSTA) NAK OUT */
|
||||
#define UDPHS_EPTSTA_CURRENT_BANK_Pos 16
|
||||
#define UDPHS_EPTSTA_CURRENT_BANK_Msk (0x3u << UDPHS_EPTSTA_CURRENT_BANK_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
|
||||
#define UDPHS_EPTSTA_CONTROL_DIR_Pos 16
|
||||
#define UDPHS_EPTSTA_CONTROL_DIR_Msk (0x3u << UDPHS_EPTSTA_CONTROL_DIR_Pos) /**< \brief (UDPHS_EPTSTA) Current Bank/Control Direction */
|
||||
#define UDPHS_EPTSTA_BUSY_BANK_STA_Pos 18
|
||||
#define UDPHS_EPTSTA_BUSY_BANK_STA_Msk (0x3u << UDPHS_EPTSTA_BUSY_BANK_STA_Pos) /**< \brief (UDPHS_EPTSTA) Busy Bank Number */
|
||||
#define UDPHS_EPTSTA_BUSY_BANK_STA_1BUSYBANK (0x0u << 18) /**< \brief (UDPHS_EPTSTA) 1 busy bank */
|
||||
#define UDPHS_EPTSTA_BUSY_BANK_STA_2BUSYBANKS (0x1u << 18) /**< \brief (UDPHS_EPTSTA) 2 busy banks */
|
||||
#define UDPHS_EPTSTA_BUSY_BANK_STA_3BUSYBANKS (0x2u << 18) /**< \brief (UDPHS_EPTSTA) 3 busy banks */
|
||||
#define UDPHS_EPTSTA_BYTE_COUNT_Pos 20
|
||||
#define UDPHS_EPTSTA_BYTE_COUNT_Msk (0x7ffu << UDPHS_EPTSTA_BYTE_COUNT_Pos) /**< \brief (UDPHS_EPTSTA) UDPHS Byte Count */
|
||||
#define UDPHS_EPTSTA_SHRT_PCKT (0x1u << 31) /**< \brief (UDPHS_EPTSTA) Short Packet */
|
||||
/* -------- UDPHS_DMANXTDSC : (UDPHS Offset: N/A) UDPHS DMA Next Descriptor Address Register -------- */
|
||||
#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos 0
|
||||
#define UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UDPHS_DMANXTDSC) */
|
||||
#define UDPHS_DMANXTDSC_NXT_DSC_ADD(value) ((UDPHS_DMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UDPHS_DMANXTDSC_NXT_DSC_ADD_Pos)))
|
||||
/* -------- UDPHS_DMAADDRESS : (UDPHS Offset: N/A) UDPHS DMA Channel Address Register -------- */
|
||||
#define UDPHS_DMAADDRESS_BUFF_ADD_Pos 0
|
||||
#define UDPHS_DMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UDPHS_DMAADDRESS_BUFF_ADD_Pos) /**< \brief (UDPHS_DMAADDRESS) */
|
||||
#define UDPHS_DMAADDRESS_BUFF_ADD(value) ((UDPHS_DMAADDRESS_BUFF_ADD_Msk & ((value) << UDPHS_DMAADDRESS_BUFF_ADD_Pos)))
|
||||
/* -------- UDPHS_DMACONTROL : (UDPHS Offset: N/A) UDPHS DMA Channel Control Register -------- */
|
||||
#define UDPHS_DMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMACONTROL) */
|
||||
#define UDPHS_DMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UDPHS_DMACONTROL) Load Next Channel Transfer Descriptor Enable (Command) */
|
||||
#define UDPHS_DMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UDPHS_DMACONTROL) End of Transfer Enable (Control) */
|
||||
#define UDPHS_DMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UDPHS_DMACONTROL) End of Buffer Enable (Control) */
|
||||
#define UDPHS_DMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UDPHS_DMACONTROL) End of Transfer Interrupt Enable */
|
||||
#define UDPHS_DMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UDPHS_DMACONTROL) End of Buffer Interrupt Enable */
|
||||
#define UDPHS_DMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UDPHS_DMACONTROL) Descriptor Loaded Interrupt Enable */
|
||||
#define UDPHS_DMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UDPHS_DMACONTROL) Burst Lock Enable */
|
||||
#define UDPHS_DMACONTROL_BUFF_LENGTH_Pos 16
|
||||
#define UDPHS_DMACONTROL_BUFF_LENGTH_Msk (0xffffu << UDPHS_DMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UDPHS_DMACONTROL) Buffer Byte Length (Write-only) */
|
||||
#define UDPHS_DMACONTROL_BUFF_LENGTH(value) ((UDPHS_DMACONTROL_BUFF_LENGTH_Msk & ((value) << UDPHS_DMACONTROL_BUFF_LENGTH_Pos)))
|
||||
/* -------- UDPHS_DMASTATUS : (UDPHS Offset: N/A) UDPHS DMA Channel Status Register -------- */
|
||||
#define UDPHS_DMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UDPHS_DMASTATUS) Channel Enable Status */
|
||||
#define UDPHS_DMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UDPHS_DMASTATUS) Channel Active Status */
|
||||
#define UDPHS_DMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UDPHS_DMASTATUS) End of Channel Transfer Status */
|
||||
#define UDPHS_DMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UDPHS_DMASTATUS) End of Channel Buffer Status */
|
||||
#define UDPHS_DMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UDPHS_DMASTATUS) Descriptor Loaded Status */
|
||||
#define UDPHS_DMASTATUS_BUFF_COUNT_Pos 16
|
||||
#define UDPHS_DMASTATUS_BUFF_COUNT_Msk (0xffffu << UDPHS_DMASTATUS_BUFF_COUNT_Pos) /**< \brief (UDPHS_DMASTATUS) Buffer Byte Count */
|
||||
#define UDPHS_DMASTATUS_BUFF_COUNT(value) ((UDPHS_DMASTATUS_BUFF_COUNT_Msk & ((value) << UDPHS_DMASTATUS_BUFF_COUNT_Pos)))
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_UDPHS_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_USART_COMPONENT_
|
||||
#define _SAM3U_USART_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_USART Universal Synchronous Asynchronous Receiver Transmitter */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Usart hardware registers */
|
||||
typedef struct {
|
||||
WoReg US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */
|
||||
RwReg US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */
|
||||
WoReg US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */
|
||||
WoReg US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */
|
||||
RoReg US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */
|
||||
RoReg US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */
|
||||
RoReg US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */
|
||||
WoReg US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */
|
||||
RwReg US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */
|
||||
RwReg US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */
|
||||
RwReg US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */
|
||||
RoReg Reserved1[5];
|
||||
RwReg US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */
|
||||
RoReg US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */
|
||||
RoReg Reserved2[1];
|
||||
RwReg US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */
|
||||
RwReg US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */
|
||||
RoReg Reserved3[36];
|
||||
RwReg US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */
|
||||
RoReg US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */
|
||||
RoReg Reserved4[5];
|
||||
RwReg US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */
|
||||
RwReg US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */
|
||||
RwReg US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */
|
||||
RwReg US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */
|
||||
RwReg US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */
|
||||
RwReg US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */
|
||||
RwReg US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */
|
||||
RwReg US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */
|
||||
WoReg US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */
|
||||
RoReg US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */
|
||||
} Usart;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */
|
||||
#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */
|
||||
#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */
|
||||
#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */
|
||||
#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */
|
||||
#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */
|
||||
#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */
|
||||
#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */
|
||||
#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */
|
||||
#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */
|
||||
#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */
|
||||
#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */
|
||||
#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */
|
||||
#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */
|
||||
#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */
|
||||
#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */
|
||||
#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */
|
||||
#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */
|
||||
#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */
|
||||
#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */
|
||||
#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */
|
||||
/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */
|
||||
#define US_MR_USART_MODE_Pos 0
|
||||
#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) */
|
||||
#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */
|
||||
#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */
|
||||
#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */
|
||||
#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */
|
||||
#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */
|
||||
#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */
|
||||
#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */
|
||||
#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */
|
||||
#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */
|
||||
#define US_MR_USCLKS_Pos 4
|
||||
#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */
|
||||
#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */
|
||||
#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */
|
||||
#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */
|
||||
#define US_MR_CHRL_Pos 6
|
||||
#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */
|
||||
#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */
|
||||
#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */
|
||||
#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */
|
||||
#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */
|
||||
#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */
|
||||
#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */
|
||||
#define US_MR_PAR_Pos 9
|
||||
#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */
|
||||
#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */
|
||||
#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */
|
||||
#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */
|
||||
#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */
|
||||
#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */
|
||||
#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */
|
||||
#define US_MR_NBSTOP_Pos 12
|
||||
#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */
|
||||
#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */
|
||||
#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */
|
||||
#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */
|
||||
#define US_MR_CHMODE_Pos 14
|
||||
#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */
|
||||
#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */
|
||||
#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */
|
||||
#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */
|
||||
#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */
|
||||
#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */
|
||||
#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */
|
||||
#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */
|
||||
#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */
|
||||
#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */
|
||||
#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */
|
||||
#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */
|
||||
#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */
|
||||
#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */
|
||||
#define US_MR_MAX_ITERATION_Pos 24
|
||||
#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) */
|
||||
#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos)))
|
||||
#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */
|
||||
#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */
|
||||
#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */
|
||||
#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */
|
||||
/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */
|
||||
#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */
|
||||
#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */
|
||||
#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */
|
||||
#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable */
|
||||
#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable */
|
||||
#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */
|
||||
#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */
|
||||
#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */
|
||||
#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */
|
||||
#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */
|
||||
#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached */
|
||||
#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error */
|
||||
#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable */
|
||||
#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable */
|
||||
#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */
|
||||
#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */
|
||||
#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */
|
||||
#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */
|
||||
#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */
|
||||
#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */
|
||||
/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */
|
||||
#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */
|
||||
#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */
|
||||
#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */
|
||||
#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable */
|
||||
#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable */
|
||||
#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Disable */
|
||||
#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */
|
||||
#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */
|
||||
#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */
|
||||
#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */
|
||||
#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Disable */
|
||||
#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Disable */
|
||||
#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable */
|
||||
#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable */
|
||||
#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */
|
||||
#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */
|
||||
#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */
|
||||
#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */
|
||||
#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */
|
||||
#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */
|
||||
/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */
|
||||
#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */
|
||||
#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */
|
||||
#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */
|
||||
#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask */
|
||||
#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask */
|
||||
#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */
|
||||
#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */
|
||||
#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */
|
||||
#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */
|
||||
#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */
|
||||
#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Mask */
|
||||
#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Mask */
|
||||
#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask */
|
||||
#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask */
|
||||
#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */
|
||||
#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */
|
||||
#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */
|
||||
#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */
|
||||
#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */
|
||||
#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */
|
||||
/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */
|
||||
#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */
|
||||
#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */
|
||||
#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */
|
||||
#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */
|
||||
#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */
|
||||
#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */
|
||||
#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */
|
||||
#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */
|
||||
#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */
|
||||
#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */
|
||||
#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */
|
||||
#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) SPI Underrun Error */
|
||||
#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */
|
||||
#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */
|
||||
#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */
|
||||
#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */
|
||||
#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */
|
||||
#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */
|
||||
#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */
|
||||
#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */
|
||||
#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */
|
||||
#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */
|
||||
#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */
|
||||
#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */
|
||||
/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */
|
||||
#define US_RHR_RXCHR_Pos 0
|
||||
#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */
|
||||
#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */
|
||||
/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */
|
||||
#define US_THR_TXCHR_Pos 0
|
||||
#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */
|
||||
#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos)))
|
||||
#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */
|
||||
/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */
|
||||
#define US_BRGR_CD_Pos 0
|
||||
#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */
|
||||
#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos)))
|
||||
#define US_BRGR_FP_Pos 16
|
||||
#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */
|
||||
#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos)))
|
||||
/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */
|
||||
#define US_RTOR_TO_Pos 0
|
||||
#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */
|
||||
#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos)))
|
||||
/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */
|
||||
#define US_TTGR_TG_Pos 0
|
||||
#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */
|
||||
#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos)))
|
||||
/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */
|
||||
#define US_FIDI_FI_DI_RATIO_Pos 0
|
||||
#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */
|
||||
#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos)))
|
||||
/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */
|
||||
#define US_NER_NB_ERRORS_Pos 0
|
||||
#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */
|
||||
/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */
|
||||
#define US_IF_IRDA_FILTER_Pos 0
|
||||
#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */
|
||||
#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos)))
|
||||
/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */
|
||||
#define US_MAN_TX_PL_Pos 0
|
||||
#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */
|
||||
#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos)))
|
||||
#define US_MAN_TX_PP_Pos 8
|
||||
#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */
|
||||
#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */
|
||||
#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */
|
||||
#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */
|
||||
#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */
|
||||
#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */
|
||||
#define US_MAN_RX_PL_Pos 16
|
||||
#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */
|
||||
#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos)))
|
||||
#define US_MAN_RX_PP_Pos 24
|
||||
#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */
|
||||
#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */
|
||||
#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */
|
||||
#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */
|
||||
#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */
|
||||
#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */
|
||||
#define US_MAN_STUCKTO1 (0x1u << 29) /**< \brief (US_MAN) */
|
||||
#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */
|
||||
/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */
|
||||
#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */
|
||||
#define US_WPMR_WPKEY_Pos 8
|
||||
#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */
|
||||
#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos)))
|
||||
/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */
|
||||
#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */
|
||||
#define US_WPSR_WPVSRC_Pos 8
|
||||
#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */
|
||||
/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */
|
||||
#define US_RPR_RXPTR_Pos 0
|
||||
#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */
|
||||
#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos)))
|
||||
/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */
|
||||
#define US_RCR_RXCTR_Pos 0
|
||||
#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */
|
||||
#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos)))
|
||||
/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */
|
||||
#define US_TPR_TXPTR_Pos 0
|
||||
#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */
|
||||
#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos)))
|
||||
/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */
|
||||
#define US_TCR_TXCTR_Pos 0
|
||||
#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */
|
||||
#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos)))
|
||||
/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */
|
||||
#define US_RNPR_RXNPTR_Pos 0
|
||||
#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */
|
||||
#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos)))
|
||||
/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */
|
||||
#define US_RNCR_RXNCTR_Pos 0
|
||||
#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */
|
||||
#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos)))
|
||||
/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */
|
||||
#define US_TNPR_TXNPTR_Pos 0
|
||||
#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */
|
||||
#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos)))
|
||||
/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */
|
||||
#define US_TNCR_TXNCTR_Pos 0
|
||||
#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */
|
||||
#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos)))
|
||||
/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */
|
||||
#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */
|
||||
#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */
|
||||
#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */
|
||||
#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */
|
||||
/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */
|
||||
#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */
|
||||
#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_USART_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_WDT_COMPONENT_
|
||||
#define _SAM3U_WDT_COMPONENT_
|
||||
|
||||
/* ============================================================================= */
|
||||
/** SOFTWARE API DEFINITION FOR Watchdog Timer */
|
||||
/* ============================================================================= */
|
||||
/** \addtogroup SAM3U_WDT Watchdog Timer */
|
||||
/*@{*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/** \brief Wdt hardware registers */
|
||||
typedef struct {
|
||||
WoReg WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */
|
||||
RwReg WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */
|
||||
RoReg WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */
|
||||
} Wdt;
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */
|
||||
#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */
|
||||
#define WDT_CR_KEY_Pos 24
|
||||
#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */
|
||||
#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)))
|
||||
/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */
|
||||
#define WDT_MR_WDV_Pos 0
|
||||
#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */
|
||||
#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)))
|
||||
#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */
|
||||
#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */
|
||||
#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */
|
||||
#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */
|
||||
#define WDT_MR_WDD_Pos 16
|
||||
#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */
|
||||
#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)))
|
||||
#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */
|
||||
#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */
|
||||
/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */
|
||||
#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */
|
||||
#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */
|
||||
|
||||
/*@}*/
|
||||
|
||||
|
||||
#endif /* _SAM3U_WDT_COMPONENT_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_ADC_INSTANCE_
|
||||
#define _SAM3U_ADC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC peripheral ========== */
|
||||
#define REG_ADC_CR REG_ACCESS(WoReg, 0x400AC000U) /**< \brief (ADC) Control Register */
|
||||
#define REG_ADC_MR REG_ACCESS(RwReg, 0x400AC004U) /**< \brief (ADC) Mode Register */
|
||||
#define REG_ADC_CHER REG_ACCESS(WoReg, 0x400AC010U) /**< \brief (ADC) Channel Enable Register */
|
||||
#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x400AC014U) /**< \brief (ADC) Channel Disable Register */
|
||||
#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x400AC018U) /**< \brief (ADC) Channel Status Register */
|
||||
#define REG_ADC_SR REG_ACCESS(RoReg, 0x400AC01CU) /**< \brief (ADC) Status Register */
|
||||
#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x400AC020U) /**< \brief (ADC) Last Converted Data Register */
|
||||
#define REG_ADC_IER REG_ACCESS(WoReg, 0x400AC024U) /**< \brief (ADC) Interrupt Enable Register */
|
||||
#define REG_ADC_IDR REG_ACCESS(WoReg, 0x400AC028U) /**< \brief (ADC) Interrupt Disable Register */
|
||||
#define REG_ADC_IMR REG_ACCESS(RoReg, 0x400AC02CU) /**< \brief (ADC) Interrupt Mask Register */
|
||||
#define REG_ADC_CDR REG_ACCESS(RoReg, 0x400AC030U) /**< \brief (ADC) Channel Data Register */
|
||||
#define REG_ADC_RPR REG_ACCESS(RwReg, 0x400AC100U) /**< \brief (ADC) Receive Pointer Register */
|
||||
#define REG_ADC_RCR REG_ACCESS(RwReg, 0x400AC104U) /**< \brief (ADC) Receive Counter Register */
|
||||
#define REG_ADC_TPR REG_ACCESS(RwReg, 0x400AC108U) /**< \brief (ADC) Transmit Pointer Register */
|
||||
#define REG_ADC_TCR REG_ACCESS(RwReg, 0x400AC10CU) /**< \brief (ADC) Transmit Counter Register */
|
||||
#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x400AC110U) /**< \brief (ADC) Receive Next Pointer Register */
|
||||
#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x400AC114U) /**< \brief (ADC) Receive Next Counter Register */
|
||||
#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x400AC118U) /**< \brief (ADC) Transmit Next Pointer Register */
|
||||
#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x400AC11CU) /**< \brief (ADC) Transmit Next Counter Register */
|
||||
#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x400AC120U) /**< \brief (ADC) Transfer Control Register */
|
||||
#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x400AC124U) /**< \brief (ADC) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_ADC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_ADC12B_INSTANCE_
|
||||
#define _SAM3U_ADC12B_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC12B peripheral ========== */
|
||||
#define REG_ADC12B_CR REG_ACCESS(WoReg, 0x400A8000U) /**< \brief (ADC12B) Control Register */
|
||||
#define REG_ADC12B_MR REG_ACCESS(RwReg, 0x400A8004U) /**< \brief (ADC12B) Mode Register */
|
||||
#define REG_ADC12B_CHER REG_ACCESS(WoReg, 0x400A8010U) /**< \brief (ADC12B) Channel Enable Register */
|
||||
#define REG_ADC12B_CHDR REG_ACCESS(WoReg, 0x400A8014U) /**< \brief (ADC12B) Channel Disable Register */
|
||||
#define REG_ADC12B_CHSR REG_ACCESS(RoReg, 0x400A8018U) /**< \brief (ADC12B) Channel Status Register */
|
||||
#define REG_ADC12B_SR REG_ACCESS(RoReg, 0x400A801CU) /**< \brief (ADC12B) Status Register */
|
||||
#define REG_ADC12B_LCDR REG_ACCESS(RoReg, 0x400A8020U) /**< \brief (ADC12B) Last Converted Data Register */
|
||||
#define REG_ADC12B_IER REG_ACCESS(WoReg, 0x400A8024U) /**< \brief (ADC12B) Interrupt Enable Register */
|
||||
#define REG_ADC12B_IDR REG_ACCESS(WoReg, 0x400A8028U) /**< \brief (ADC12B) Interrupt Disable Register */
|
||||
#define REG_ADC12B_IMR REG_ACCESS(RoReg, 0x400A802CU) /**< \brief (ADC12B) Interrupt Mask Register */
|
||||
#define REG_ADC12B_CDR REG_ACCESS(RoReg, 0x400A8030U) /**< \brief (ADC12B) Channel Data Register */
|
||||
#define REG_ADC12B_ACR REG_ACCESS(RwReg, 0x400A8064U) /**< \brief (ADC12B) Analog Control Register */
|
||||
#define REG_ADC12B_EMR REG_ACCESS(RwReg, 0x400A8068U) /**< \brief (ADC12B) Extended Mode Register */
|
||||
#define REG_ADC12B_RPR REG_ACCESS(RwReg, 0x400A8100U) /**< \brief (ADC12B) Receive Pointer Register */
|
||||
#define REG_ADC12B_RCR REG_ACCESS(RwReg, 0x400A8104U) /**< \brief (ADC12B) Receive Counter Register */
|
||||
#define REG_ADC12B_TPR REG_ACCESS(RwReg, 0x400A8108U) /**< \brief (ADC12B) Transmit Pointer Register */
|
||||
#define REG_ADC12B_TCR REG_ACCESS(RwReg, 0x400A810CU) /**< \brief (ADC12B) Transmit Counter Register */
|
||||
#define REG_ADC12B_RNPR REG_ACCESS(RwReg, 0x400A8110U) /**< \brief (ADC12B) Receive Next Pointer Register */
|
||||
#define REG_ADC12B_RNCR REG_ACCESS(RwReg, 0x400A8114U) /**< \brief (ADC12B) Receive Next Counter Register */
|
||||
#define REG_ADC12B_TNPR REG_ACCESS(RwReg, 0x400A8118U) /**< \brief (ADC12B) Transmit Next Pointer Register */
|
||||
#define REG_ADC12B_TNCR REG_ACCESS(RwReg, 0x400A811CU) /**< \brief (ADC12B) Transmit Next Counter Register */
|
||||
#define REG_ADC12B_PTCR REG_ACCESS(WoReg, 0x400A8120U) /**< \brief (ADC12B) Transfer Control Register */
|
||||
#define REG_ADC12B_PTSR REG_ACCESS(RoReg, 0x400A8124U) /**< \brief (ADC12B) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_ADC12B_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_CHIPID_INSTANCE_
|
||||
#define _SAM3U_CHIPID_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CHIPID peripheral ========== */
|
||||
#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
|
||||
|
||||
#endif /* _SAM3U_CHIPID_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_DMAC_INSTANCE_
|
||||
#define _SAM3U_DMAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DMAC peripheral ========== */
|
||||
#define REG_DMAC_GCFG REG_ACCESS(RwReg, 0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
|
||||
#define REG_DMAC_EN REG_ACCESS(RwReg, 0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
|
||||
#define REG_DMAC_SREQ REG_ACCESS(RwReg, 0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
|
||||
#define REG_DMAC_CREQ REG_ACCESS(RwReg, 0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
|
||||
#define REG_DMAC_LAST REG_ACCESS(RwReg, 0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
|
||||
#define REG_DMAC_SYNC REG_ACCESS(RwReg, 0x400B0014U) /**< \brief (DMAC) DMAC Request Synchronization Register */
|
||||
#define REG_DMAC_EBCIER REG_ACCESS(WoReg, 0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
|
||||
#define REG_DMAC_EBCIDR REG_ACCESS(WoReg, 0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
|
||||
#define REG_DMAC_EBCIMR REG_ACCESS(RoReg, 0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
|
||||
#define REG_DMAC_EBCISR REG_ACCESS(RoReg, 0x400B0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. */
|
||||
#define REG_DMAC_CHER REG_ACCESS(WoReg, 0x400B0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
|
||||
#define REG_DMAC_CHDR REG_ACCESS(WoReg, 0x400B002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
|
||||
#define REG_DMAC_CHSR REG_ACCESS(RoReg, 0x400B0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
|
||||
#define REG_DMAC_SADDR0 REG_ACCESS(RwReg, 0x400B003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
|
||||
#define REG_DMAC_DADDR0 REG_ACCESS(RwReg, 0x400B0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
|
||||
#define REG_DMAC_DSCR0 REG_ACCESS(RwReg, 0x400B0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
|
||||
#define REG_DMAC_CTRLA0 REG_ACCESS(RwReg, 0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
|
||||
#define REG_DMAC_CTRLB0 REG_ACCESS(RwReg, 0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
|
||||
#define REG_DMAC_CFG0 REG_ACCESS(RwReg, 0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
|
||||
#define REG_DMAC_SPIP0 REG_ACCESS(RwReg, 0x400B0054U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 0) */
|
||||
#define REG_DMAC_DPIP0 REG_ACCESS(RwReg, 0x400B0058U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 0) */
|
||||
#define REG_DMAC_SADDR1 REG_ACCESS(RwReg, 0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
|
||||
#define REG_DMAC_DADDR1 REG_ACCESS(RwReg, 0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
|
||||
#define REG_DMAC_DSCR1 REG_ACCESS(RwReg, 0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
|
||||
#define REG_DMAC_CTRLA1 REG_ACCESS(RwReg, 0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
|
||||
#define REG_DMAC_CTRLB1 REG_ACCESS(RwReg, 0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
|
||||
#define REG_DMAC_CFG1 REG_ACCESS(RwReg, 0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
|
||||
#define REG_DMAC_SPIP1 REG_ACCESS(RwReg, 0x400B007CU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 1) */
|
||||
#define REG_DMAC_DPIP1 REG_ACCESS(RwReg, 0x400B0080U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 1) */
|
||||
#define REG_DMAC_SADDR2 REG_ACCESS(RwReg, 0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
|
||||
#define REG_DMAC_DADDR2 REG_ACCESS(RwReg, 0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
|
||||
#define REG_DMAC_DSCR2 REG_ACCESS(RwReg, 0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
|
||||
#define REG_DMAC_CTRLA2 REG_ACCESS(RwReg, 0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
|
||||
#define REG_DMAC_CTRLB2 REG_ACCESS(RwReg, 0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
|
||||
#define REG_DMAC_CFG2 REG_ACCESS(RwReg, 0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
|
||||
#define REG_DMAC_SPIP2 REG_ACCESS(RwReg, 0x400B00A4U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 2) */
|
||||
#define REG_DMAC_DPIP2 REG_ACCESS(RwReg, 0x400B00A8U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 2) */
|
||||
#define REG_DMAC_SADDR3 REG_ACCESS(RwReg, 0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
|
||||
#define REG_DMAC_DADDR3 REG_ACCESS(RwReg, 0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
|
||||
#define REG_DMAC_DSCR3 REG_ACCESS(RwReg, 0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
|
||||
#define REG_DMAC_CTRLA3 REG_ACCESS(RwReg, 0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
|
||||
#define REG_DMAC_CTRLB3 REG_ACCESS(RwReg, 0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
|
||||
#define REG_DMAC_CFG3 REG_ACCESS(RwReg, 0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
|
||||
#define REG_DMAC_SPIP3 REG_ACCESS(RwReg, 0x400B00CCU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 3) */
|
||||
#define REG_DMAC_DPIP3 REG_ACCESS(RwReg, 0x400B00D0U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 3) */
|
||||
|
||||
#endif /* _SAM3U_DMAC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_EFC0_INSTANCE_
|
||||
#define _SAM3U_EFC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EFC0 peripheral ========== */
|
||||
#define REG_EFC0_FMR REG_ACCESS(RwReg, 0x400E0800U) /**< \brief (EFC0) EEFC Flash Mode Register */
|
||||
#define REG_EFC0_FCR REG_ACCESS(WoReg, 0x400E0804U) /**< \brief (EFC0) EEFC Flash Command Register */
|
||||
#define REG_EFC0_FSR REG_ACCESS(RoReg, 0x400E0808U) /**< \brief (EFC0) EEFC Flash Status Register */
|
||||
#define REG_EFC0_FRR REG_ACCESS(RoReg, 0x400E080CU) /**< \brief (EFC0) EEFC Flash Result Register */
|
||||
|
||||
#endif /* _SAM3U_EFC0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_EFC1_INSTANCE_
|
||||
#define _SAM3U_EFC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EFC1 peripheral ========== */
|
||||
#define REG_EFC1_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC1) EEFC Flash Mode Register */
|
||||
#define REG_EFC1_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC1) EEFC Flash Command Register */
|
||||
#define REG_EFC1_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC1) EEFC Flash Status Register */
|
||||
#define REG_EFC1_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC1) EEFC Flash Result Register */
|
||||
|
||||
#endif /* _SAM3U_EFC1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_GPBR_INSTANCE_
|
||||
#define _SAM3U_GPBR_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GPBR peripheral ========== */
|
||||
#define REG_GPBR_GPBR REG_ACCESS(RwReg, 0x400E1290U) /**< \brief (GPBR) General Purpose Backup Register */
|
||||
|
||||
#endif /* _SAM3U_GPBR_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_HSMCI_INSTANCE_
|
||||
#define _SAM3U_HSMCI_INSTANCE_
|
||||
|
||||
/* ========== Register definition for HSMCI peripheral ========== */
|
||||
#define REG_HSMCI_CR REG_ACCESS(WoReg, 0x40000000U) /**< \brief (HSMCI) Control Register */
|
||||
#define REG_HSMCI_MR REG_ACCESS(RwReg, 0x40000004U) /**< \brief (HSMCI) Mode Register */
|
||||
#define REG_HSMCI_DTOR REG_ACCESS(RwReg, 0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
|
||||
#define REG_HSMCI_SDCR REG_ACCESS(RwReg, 0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
|
||||
#define REG_HSMCI_ARGR REG_ACCESS(RwReg, 0x40000010U) /**< \brief (HSMCI) Argument Register */
|
||||
#define REG_HSMCI_CMDR REG_ACCESS(WoReg, 0x40000014U) /**< \brief (HSMCI) Command Register */
|
||||
#define REG_HSMCI_BLKR REG_ACCESS(RwReg, 0x40000018U) /**< \brief (HSMCI) Block Register */
|
||||
#define REG_HSMCI_CSTOR REG_ACCESS(RwReg, 0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
|
||||
#define REG_HSMCI_RSPR REG_ACCESS(RoReg, 0x40000020U) /**< \brief (HSMCI) Response Register */
|
||||
#define REG_HSMCI_RDR REG_ACCESS(RoReg, 0x40000030U) /**< \brief (HSMCI) Receive Data Register */
|
||||
#define REG_HSMCI_TDR REG_ACCESS(WoReg, 0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
|
||||
#define REG_HSMCI_SR REG_ACCESS(RoReg, 0x40000040U) /**< \brief (HSMCI) Status Register */
|
||||
#define REG_HSMCI_IER REG_ACCESS(WoReg, 0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
|
||||
#define REG_HSMCI_IDR REG_ACCESS(WoReg, 0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
|
||||
#define REG_HSMCI_IMR REG_ACCESS(RoReg, 0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
|
||||
#define REG_HSMCI_DMA REG_ACCESS(RwReg, 0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */
|
||||
#define REG_HSMCI_CFG REG_ACCESS(RwReg, 0x40000054U) /**< \brief (HSMCI) Configuration Register */
|
||||
#define REG_HSMCI_WPMR REG_ACCESS(RwReg, 0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
|
||||
#define REG_HSMCI_WPSR REG_ACCESS(RoReg, 0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
|
||||
#define REG_HSMCI_FIFO REG_ACCESS(RwReg, 0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
|
||||
|
||||
#endif /* _SAM3U_HSMCI_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_MATRIX_INSTANCE_
|
||||
#define _SAM3U_MATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MATRIX peripheral ========== */
|
||||
#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
|
||||
#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
|
||||
#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_MATRIX_PRAS4 REG_ACCESS(RwReg, 0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
|
||||
#define REG_MATRIX_PRAS5 REG_ACCESS(RwReg, 0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
|
||||
#define REG_MATRIX_PRAS6 REG_ACCESS(RwReg, 0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
|
||||
#define REG_MATRIX_PRAS7 REG_ACCESS(RwReg, 0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
|
||||
#define REG_MATRIX_PRAS8 REG_ACCESS(RwReg, 0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
|
||||
#define REG_MATRIX_PRAS9 REG_ACCESS(RwReg, 0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
|
||||
#define REG_MATRIX_MRCR REG_ACCESS(RwReg, 0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
|
||||
#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
|
||||
#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3U_MATRIX_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PIOA_INSTANCE_
|
||||
#define _SAM3U_PIOA_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOA peripheral ========== */
|
||||
#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0C00U) /**< \brief (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0C04U) /**< \brief (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0C08U) /**< \brief (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0C10U) /**< \brief (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0C14U) /**< \brief (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0C18U) /**< \brief (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0C20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0C24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0C28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0C30U) /**< \brief (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0C34U) /**< \brief (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0C38U) /**< \brief (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0C3CU) /**< \brief (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0C40U) /**< \brief (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0C44U) /**< \brief (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0C48U) /**< \brief (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0C4CU) /**< \brief (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0C50U) /**< \brief (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0C54U) /**< \brief (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0C58U) /**< \brief (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0C60U) /**< \brief (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0C64U) /**< \brief (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0C68U) /**< \brief (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABSR REG_ACCESS(RwReg, 0x400E0C70U) /**< \brief (PIOA) Peripheral AB Select Register */
|
||||
#define REG_PIOA_SCIFSR REG_ACCESS(WoReg, 0x400E0C80U) /**< \brief (PIOA) System Clock Glitch Input Filter Select Register */
|
||||
#define REG_PIOA_DIFSR REG_ACCESS(WoReg, 0x400E0C84U) /**< \brief (PIOA) Debouncing Input Filter Select Register */
|
||||
#define REG_PIOA_IFDGSR REG_ACCESS(RoReg, 0x400E0C88U) /**< \brief (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register */
|
||||
#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0C8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0CA0U) /**< \brief (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0CA4U) /**< \brief (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0CA8U) /**< \brief (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0CB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0CB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0CB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0CC0U) /**< \brief (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0CC4U) /**< \brief (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0CC8U) /**< \brief (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0CD0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0CD4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0CD8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0CE0U) /**< \brief (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0CE4U) /**< \brief (PIOA) Write Protect Mode Register */
|
||||
#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0CE8U) /**< \brief (PIOA) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3U_PIOA_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PIOB_INSTANCE_
|
||||
#define _SAM3U_PIOB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOB peripheral ========== */
|
||||
#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOB) Peripheral AB Select Register */
|
||||
#define REG_PIOB_SCIFSR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOB) System Clock Glitch Input Filter Select Register */
|
||||
#define REG_PIOB_DIFSR REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOB) Debouncing Input Filter Select Register */
|
||||
#define REG_PIOB_IFDGSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register */
|
||||
#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOB) Write Protect Mode Register */
|
||||
#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOB) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3U_PIOB_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PIOC_INSTANCE_
|
||||
#define _SAM3U_PIOC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOC peripheral ========== */
|
||||
#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
|
||||
#define REG_PIOC_SCIFSR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
|
||||
#define REG_PIOC_DIFSR REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
|
||||
#define REG_PIOC_IFDGSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
|
||||
#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
|
||||
#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3U_PIOC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PMC_INSTANCE_
|
||||
#define _SAM3U_PMC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PMC peripheral ========== */
|
||||
#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
|
||||
#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
|
||||
#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
|
||||
#define REG_CKGR_UCKR REG_ACCESS(RwReg, 0x400E041CU) /**< \brief (PMC) UTMI Clock Register */
|
||||
#define REG_CKGR_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLAR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLLA Register */
|
||||
#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
|
||||
#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
|
||||
#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
|
||||
#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
|
||||
#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3U_PMC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_PWM_INSTANCE_
|
||||
#define _SAM3U_PWM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PWM peripheral ========== */
|
||||
#define REG_PWM_CLK REG_ACCESS(RwReg, 0x4008C000U) /**< \brief (PWM) PWM Clock Register */
|
||||
#define REG_PWM_ENA REG_ACCESS(WoReg, 0x4008C004U) /**< \brief (PWM) PWM Enable Register */
|
||||
#define REG_PWM_DIS REG_ACCESS(WoReg, 0x4008C008U) /**< \brief (PWM) PWM Disable Register */
|
||||
#define REG_PWM_SR REG_ACCESS(RoReg, 0x4008C00CU) /**< \brief (PWM) PWM Status Register */
|
||||
#define REG_PWM_IER1 REG_ACCESS(WoReg, 0x4008C010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
|
||||
#define REG_PWM_IDR1 REG_ACCESS(WoReg, 0x4008C014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
|
||||
#define REG_PWM_IMR1 REG_ACCESS(RoReg, 0x4008C018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
|
||||
#define REG_PWM_ISR1 REG_ACCESS(RoReg, 0x4008C01CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
|
||||
#define REG_PWM_SCM REG_ACCESS(RwReg, 0x4008C020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
|
||||
#define REG_PWM_SCUC REG_ACCESS(RwReg, 0x4008C028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
|
||||
#define REG_PWM_SCUP REG_ACCESS(RwReg, 0x4008C02CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
|
||||
#define REG_PWM_SCUPUPD REG_ACCESS(WoReg, 0x4008C030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
|
||||
#define REG_PWM_IER2 REG_ACCESS(WoReg, 0x4008C034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
|
||||
#define REG_PWM_IDR2 REG_ACCESS(WoReg, 0x4008C038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
|
||||
#define REG_PWM_IMR2 REG_ACCESS(RoReg, 0x4008C03CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
|
||||
#define REG_PWM_ISR2 REG_ACCESS(RoReg, 0x4008C040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
|
||||
#define REG_PWM_OOV REG_ACCESS(RwReg, 0x4008C044U) /**< \brief (PWM) PWM Output Override Value Register */
|
||||
#define REG_PWM_OS REG_ACCESS(RwReg, 0x4008C048U) /**< \brief (PWM) PWM Output Selection Register */
|
||||
#define REG_PWM_OSS REG_ACCESS(WoReg, 0x4008C04CU) /**< \brief (PWM) PWM Output Selection Set Register */
|
||||
#define REG_PWM_OSC REG_ACCESS(WoReg, 0x4008C050U) /**< \brief (PWM) PWM Output Selection Clear Register */
|
||||
#define REG_PWM_OSSUPD REG_ACCESS(WoReg, 0x4008C054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
|
||||
#define REG_PWM_OSCUPD REG_ACCESS(WoReg, 0x4008C058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
|
||||
#define REG_PWM_FMR REG_ACCESS(RwReg, 0x4008C05CU) /**< \brief (PWM) PWM Fault Mode Register */
|
||||
#define REG_PWM_FSR REG_ACCESS(RoReg, 0x4008C060U) /**< \brief (PWM) PWM Fault Status Register */
|
||||
#define REG_PWM_FCR REG_ACCESS(WoReg, 0x4008C064U) /**< \brief (PWM) PWM Fault Clear Register */
|
||||
#define REG_PWM_FPV REG_ACCESS(RwReg, 0x4008C068U) /**< \brief (PWM) PWM Fault Protection Value Register */
|
||||
#define REG_PWM_FPE REG_ACCESS(RwReg, 0x4008C06CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
|
||||
#define REG_PWM_ELMR REG_ACCESS(RwReg, 0x4008C07CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
|
||||
#define REG_PWM_WPCR REG_ACCESS(WoReg, 0x4008C0E4U) /**< \brief (PWM) PWM Write Protect Control Register */
|
||||
#define REG_PWM_WPSR REG_ACCESS(RoReg, 0x4008C0E8U) /**< \brief (PWM) PWM Write Protect Status Register */
|
||||
#define REG_PWM_RPR REG_ACCESS(RwReg, 0x4008C100U) /**< \brief (PWM) Receive Pointer Register */
|
||||
#define REG_PWM_RCR REG_ACCESS(RwReg, 0x4008C104U) /**< \brief (PWM) Receive Counter Register */
|
||||
#define REG_PWM_TPR REG_ACCESS(RwReg, 0x4008C108U) /**< \brief (PWM) Transmit Pointer Register */
|
||||
#define REG_PWM_TCR REG_ACCESS(RwReg, 0x4008C10CU) /**< \brief (PWM) Transmit Counter Register */
|
||||
#define REG_PWM_RNPR REG_ACCESS(RwReg, 0x4008C110U) /**< \brief (PWM) Receive Next Pointer Register */
|
||||
#define REG_PWM_RNCR REG_ACCESS(RwReg, 0x4008C114U) /**< \brief (PWM) Receive Next Counter Register */
|
||||
#define REG_PWM_TNPR REG_ACCESS(RwReg, 0x4008C118U) /**< \brief (PWM) Transmit Next Pointer Register */
|
||||
#define REG_PWM_TNCR REG_ACCESS(RwReg, 0x4008C11CU) /**< \brief (PWM) Transmit Next Counter Register */
|
||||
#define REG_PWM_PTCR REG_ACCESS(WoReg, 0x4008C120U) /**< \brief (PWM) Transfer Control Register */
|
||||
#define REG_PWM_PTSR REG_ACCESS(RoReg, 0x4008C124U) /**< \brief (PWM) Transfer Status Register */
|
||||
#define REG_PWM_CMPV0 REG_ACCESS(RwReg, 0x4008C130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
|
||||
#define REG_PWM_CMPVUPD0 REG_ACCESS(WoReg, 0x4008C134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
|
||||
#define REG_PWM_CMPM0 REG_ACCESS(RwReg, 0x4008C138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
|
||||
#define REG_PWM_CMPMUPD0 REG_ACCESS(WoReg, 0x4008C13CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
|
||||
#define REG_PWM_CMPV1 REG_ACCESS(RwReg, 0x4008C140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
|
||||
#define REG_PWM_CMPVUPD1 REG_ACCESS(WoReg, 0x4008C144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
|
||||
#define REG_PWM_CMPM1 REG_ACCESS(RwReg, 0x4008C148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
|
||||
#define REG_PWM_CMPMUPD1 REG_ACCESS(WoReg, 0x4008C14CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
|
||||
#define REG_PWM_CMPV2 REG_ACCESS(RwReg, 0x4008C150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
|
||||
#define REG_PWM_CMPVUPD2 REG_ACCESS(WoReg, 0x4008C154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
|
||||
#define REG_PWM_CMPM2 REG_ACCESS(RwReg, 0x4008C158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
|
||||
#define REG_PWM_CMPMUPD2 REG_ACCESS(WoReg, 0x4008C15CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
|
||||
#define REG_PWM_CMPV3 REG_ACCESS(RwReg, 0x4008C160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
|
||||
#define REG_PWM_CMPVUPD3 REG_ACCESS(WoReg, 0x4008C164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
|
||||
#define REG_PWM_CMPM3 REG_ACCESS(RwReg, 0x4008C168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
|
||||
#define REG_PWM_CMPMUPD3 REG_ACCESS(WoReg, 0x4008C16CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
|
||||
#define REG_PWM_CMPV4 REG_ACCESS(RwReg, 0x4008C170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
|
||||
#define REG_PWM_CMPVUPD4 REG_ACCESS(WoReg, 0x4008C174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
|
||||
#define REG_PWM_CMPM4 REG_ACCESS(RwReg, 0x4008C178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
|
||||
#define REG_PWM_CMPMUPD4 REG_ACCESS(WoReg, 0x4008C17CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
|
||||
#define REG_PWM_CMPV5 REG_ACCESS(RwReg, 0x4008C180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
|
||||
#define REG_PWM_CMPVUPD5 REG_ACCESS(WoReg, 0x4008C184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
|
||||
#define REG_PWM_CMPM5 REG_ACCESS(RwReg, 0x4008C188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
|
||||
#define REG_PWM_CMPMUPD5 REG_ACCESS(WoReg, 0x4008C18CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
|
||||
#define REG_PWM_CMPV6 REG_ACCESS(RwReg, 0x4008C190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
|
||||
#define REG_PWM_CMPVUPD6 REG_ACCESS(WoReg, 0x4008C194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
|
||||
#define REG_PWM_CMPM6 REG_ACCESS(RwReg, 0x4008C198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
|
||||
#define REG_PWM_CMPMUPD6 REG_ACCESS(WoReg, 0x4008C19CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
|
||||
#define REG_PWM_CMPV7 REG_ACCESS(RwReg, 0x4008C1A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
|
||||
#define REG_PWM_CMPVUPD7 REG_ACCESS(WoReg, 0x4008C1A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
|
||||
#define REG_PWM_CMPM7 REG_ACCESS(RwReg, 0x4008C1A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
|
||||
#define REG_PWM_CMPMUPD7 REG_ACCESS(WoReg, 0x4008C1ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
|
||||
#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x4008C200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
|
||||
#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x4008C204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
|
||||
#define REG_PWM_CDTYUPD0 REG_ACCESS(WoReg, 0x4008C208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x4008C20CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
|
||||
#define REG_PWM_CPRDUPD0 REG_ACCESS(WoReg, 0x4008C210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4008C214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
|
||||
#define REG_PWM_DT0 REG_ACCESS(RwReg, 0x4008C218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
|
||||
#define REG_PWM_DTUPD0 REG_ACCESS(WoReg, 0x4008C21CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x4008C220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
|
||||
#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x4008C224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
|
||||
#define REG_PWM_CDTYUPD1 REG_ACCESS(WoReg, 0x4008C228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x4008C22CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
|
||||
#define REG_PWM_CPRDUPD1 REG_ACCESS(WoReg, 0x4008C230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4008C234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
|
||||
#define REG_PWM_DT1 REG_ACCESS(RwReg, 0x4008C238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
|
||||
#define REG_PWM_DTUPD1 REG_ACCESS(WoReg, 0x4008C23CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x4008C240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
|
||||
#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x4008C244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
|
||||
#define REG_PWM_CDTYUPD2 REG_ACCESS(WoReg, 0x4008C248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x4008C24CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
|
||||
#define REG_PWM_CPRDUPD2 REG_ACCESS(WoReg, 0x4008C250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4008C254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
|
||||
#define REG_PWM_DT2 REG_ACCESS(RwReg, 0x4008C258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
|
||||
#define REG_PWM_DTUPD2 REG_ACCESS(WoReg, 0x4008C25CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x4008C260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
|
||||
#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x4008C264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
|
||||
#define REG_PWM_CDTYUPD3 REG_ACCESS(WoReg, 0x4008C268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
|
||||
#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x4008C26CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
|
||||
#define REG_PWM_CPRDUPD3 REG_ACCESS(WoReg, 0x4008C270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
|
||||
#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4008C274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
|
||||
#define REG_PWM_DT3 REG_ACCESS(RwReg, 0x4008C278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
|
||||
#define REG_PWM_DTUPD3 REG_ACCESS(WoReg, 0x4008C27CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
|
||||
|
||||
#endif /* _SAM3U_PWM_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_RSTC_INSTANCE_
|
||||
#define _SAM3U_RSTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RSTC peripheral ========== */
|
||||
#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (RSTC) Control Register */
|
||||
#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1204U) /**< \brief (RSTC) Status Register */
|
||||
#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1208U) /**< \brief (RSTC) Mode Register */
|
||||
|
||||
#endif /* _SAM3U_RSTC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_RTC_INSTANCE_
|
||||
#define _SAM3U_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1260U) /**< \brief (RTC) Control Register */
|
||||
#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1264U) /**< \brief (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1268U) /**< \brief (RTC) Time Register */
|
||||
#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E126CU) /**< \brief (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1274U) /**< \brief (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1278U) /**< \brief (RTC) Status Register */
|
||||
#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E127CU) /**< \brief (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E128CU) /**< \brief (RTC) Valid Entry Register */
|
||||
#define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1344U) /**< \brief (RTC) Write Protect Mode Register */
|
||||
|
||||
#endif /* _SAM3U_RTC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_RTT_INSTANCE_
|
||||
#define _SAM3U_RTT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTT peripheral ========== */
|
||||
#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1230U) /**< \brief (RTT) Mode Register */
|
||||
#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1234U) /**< \brief (RTT) Alarm Register */
|
||||
#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1238U) /**< \brief (RTT) Value Register */
|
||||
#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (RTT) Status Register */
|
||||
|
||||
#endif /* _SAM3U_RTT_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SMC_INSTANCE_
|
||||
#define _SAM3U_SMC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SMC peripheral ========== */
|
||||
#define REG_SMC_CFG REG_ACCESS(RwReg, 0x400E0000U) /**< \brief (SMC) SMC NFC Configuration Register */
|
||||
#define REG_SMC_CTRL REG_ACCESS(WoReg, 0x400E0004U) /**< \brief (SMC) SMC NFC Control Register */
|
||||
#define REG_SMC_SR REG_ACCESS(RoReg, 0x400E0008U) /**< \brief (SMC) SMC NFC Status Register */
|
||||
#define REG_SMC_IER REG_ACCESS(WoReg, 0x400E000CU) /**< \brief (SMC) SMC NFC Interrupt Enable Register */
|
||||
#define REG_SMC_IDR REG_ACCESS(WoReg, 0x400E0010U) /**< \brief (SMC) SMC NFC Interrupt Disable Register */
|
||||
#define REG_SMC_IMR REG_ACCESS(RoReg, 0x400E0014U) /**< \brief (SMC) SMC NFC Interrupt Mask Register */
|
||||
#define REG_SMC_ADDR REG_ACCESS(RwReg, 0x400E0018U) /**< \brief (SMC) SMC NFC Address Cycle Zero Register */
|
||||
#define REG_SMC_BANK REG_ACCESS(RwReg, 0x400E001CU) /**< \brief (SMC) SMC Bank Address Register */
|
||||
#define REG_SMC_ECC_CTRL REG_ACCESS(WoReg, 0x400E0020U) /**< \brief (SMC) SMC ECC Control Register */
|
||||
#define REG_SMC_ECC_MD REG_ACCESS(RwReg, 0x400E0024U) /**< \brief (SMC) SMC ECC Mode Register */
|
||||
#define REG_SMC_ECC_SR1 REG_ACCESS(RoReg, 0x400E0028U) /**< \brief (SMC) SMC ECC Status 1 Register */
|
||||
#define REG_SMC_ECC_PR0 REG_ACCESS(RoReg, 0x400E002CU) /**< \brief (SMC) SMC ECC Parity 0 Register */
|
||||
#define REG_SMC_ECC_PR1 REG_ACCESS(RoReg, 0x400E0030U) /**< \brief (SMC) SMC ECC parity 1 Register */
|
||||
#define REG_SMC_ECC_SR2 REG_ACCESS(RoReg, 0x400E0034U) /**< \brief (SMC) SMC ECC status 2 Register */
|
||||
#define REG_SMC_ECC_PR2 REG_ACCESS(RoReg, 0x400E0038U) /**< \brief (SMC) SMC ECC parity 2 Register */
|
||||
#define REG_SMC_ECC_PR3 REG_ACCESS(RoReg, 0x400E003CU) /**< \brief (SMC) SMC ECC parity 3 Register */
|
||||
#define REG_SMC_ECC_PR4 REG_ACCESS(RoReg, 0x400E0040U) /**< \brief (SMC) SMC ECC parity 4 Register */
|
||||
#define REG_SMC_ECC_PR5 REG_ACCESS(RoReg, 0x400E0044U) /**< \brief (SMC) SMC ECC parity 5 Register */
|
||||
#define REG_SMC_ECC_PR6 REG_ACCESS(RoReg, 0x400E0048U) /**< \brief (SMC) SMC ECC parity 6 Register */
|
||||
#define REG_SMC_ECC_PR7 REG_ACCESS(RoReg, 0x400E004CU) /**< \brief (SMC) SMC ECC parity 7 Register */
|
||||
#define REG_SMC_ECC_PR8 REG_ACCESS(RoReg, 0x400E0050U) /**< \brief (SMC) SMC ECC parity 8 Register */
|
||||
#define REG_SMC_ECC_PR9 REG_ACCESS(RoReg, 0x400E0054U) /**< \brief (SMC) SMC ECC parity 9 Register */
|
||||
#define REG_SMC_ECC_PR10 REG_ACCESS(RoReg, 0x400E0058U) /**< \brief (SMC) SMC ECC parity 10 Register */
|
||||
#define REG_SMC_ECC_PR11 REG_ACCESS(RoReg, 0x400E005CU) /**< \brief (SMC) SMC ECC parity 11 Register */
|
||||
#define REG_SMC_ECC_PR12 REG_ACCESS(RoReg, 0x400E0060U) /**< \brief (SMC) SMC ECC parity 12 Register */
|
||||
#define REG_SMC_ECC_PR13 REG_ACCESS(RoReg, 0x400E0064U) /**< \brief (SMC) SMC ECC parity 13 Register */
|
||||
#define REG_SMC_ECC_PR14 REG_ACCESS(RoReg, 0x400E0068U) /**< \brief (SMC) SMC ECC parity 14 Register */
|
||||
#define REG_SMC_ECC_PR15 REG_ACCESS(RoReg, 0x400E006CU) /**< \brief (SMC) SMC ECC parity 15 Register */
|
||||
#define REG_SMC_SETUP0 REG_ACCESS(RwReg, 0x400E0070U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
|
||||
#define REG_SMC_PULSE0 REG_ACCESS(RwReg, 0x400E0074U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
|
||||
#define REG_SMC_CYCLE0 REG_ACCESS(RwReg, 0x400E0078U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
|
||||
#define REG_SMC_TIMINGS0 REG_ACCESS(RwReg, 0x400E007CU) /**< \brief (SMC) SMC Timings Register (CS_number = 0) */
|
||||
#define REG_SMC_MODE0 REG_ACCESS(RwReg, 0x400E0080U) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
|
||||
#define REG_SMC_SETUP1 REG_ACCESS(RwReg, 0x400E0084U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
|
||||
#define REG_SMC_PULSE1 REG_ACCESS(RwReg, 0x400E0088U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
|
||||
#define REG_SMC_CYCLE1 REG_ACCESS(RwReg, 0x400E008CU) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
|
||||
#define REG_SMC_TIMINGS1 REG_ACCESS(RwReg, 0x400E0090U) /**< \brief (SMC) SMC Timings Register (CS_number = 1) */
|
||||
#define REG_SMC_MODE1 REG_ACCESS(RwReg, 0x400E0094U) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
|
||||
#define REG_SMC_SETUP2 REG_ACCESS(RwReg, 0x400E0098U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
|
||||
#define REG_SMC_PULSE2 REG_ACCESS(RwReg, 0x400E009CU) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
|
||||
#define REG_SMC_CYCLE2 REG_ACCESS(RwReg, 0x400E00A0U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
|
||||
#define REG_SMC_TIMINGS2 REG_ACCESS(RwReg, 0x400E00A4U) /**< \brief (SMC) SMC Timings Register (CS_number = 2) */
|
||||
#define REG_SMC_MODE2 REG_ACCESS(RwReg, 0x400E00A8U) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
|
||||
#define REG_SMC_SETUP3 REG_ACCESS(RwReg, 0x400E00ACU) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
|
||||
#define REG_SMC_PULSE3 REG_ACCESS(RwReg, 0x400E00B0U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
|
||||
#define REG_SMC_CYCLE3 REG_ACCESS(RwReg, 0x400E00B4U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
|
||||
#define REG_SMC_TIMINGS3 REG_ACCESS(RwReg, 0x400E00B8U) /**< \brief (SMC) SMC Timings Register (CS_number = 3) */
|
||||
#define REG_SMC_MODE3 REG_ACCESS(RwReg, 0x400E00BCU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
|
||||
#define REG_SMC_OCMS REG_ACCESS(RwReg, 0x400E0110U) /**< \brief (SMC) SMC OCMS Register */
|
||||
#define REG_SMC_KEY1 REG_ACCESS(WoReg, 0x400E0114U) /**< \brief (SMC) SMC OCMS KEY1 Register */
|
||||
#define REG_SMC_KEY2 REG_ACCESS(WoReg, 0x400E0118U) /**< \brief (SMC) SMC OCMS KEY2 Register */
|
||||
#define REG_SMC_WPCR REG_ACCESS(WoReg, 0x400E01E4U) /**< \brief (SMC) Write Protection Control Register */
|
||||
#define REG_SMC_WPSR REG_ACCESS(RoReg, 0x400E01E8U) /**< \brief (SMC) Write Protection Status Register */
|
||||
|
||||
#endif /* _SAM3U_SMC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SPI_INSTANCE_
|
||||
#define _SAM3U_SPI_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SPI peripheral ========== */
|
||||
#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
|
||||
#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
|
||||
#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
|
||||
#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
|
||||
#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
|
||||
#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
|
||||
#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
|
||||
#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
|
||||
#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
|
||||
#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
|
||||
#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
|
||||
|
||||
#endif /* _SAM3U_SPI_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SSC_INSTANCE_
|
||||
#define _SAM3U_SSC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SSC peripheral ========== */
|
||||
#define REG_SSC_CR REG_ACCESS(WoReg, 0x40004000U) /**< \brief (SSC) Control Register */
|
||||
#define REG_SSC_CMR REG_ACCESS(RwReg, 0x40004004U) /**< \brief (SSC) Clock Mode Register */
|
||||
#define REG_SSC_RCMR REG_ACCESS(RwReg, 0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */
|
||||
#define REG_SSC_RFMR REG_ACCESS(RwReg, 0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */
|
||||
#define REG_SSC_TCMR REG_ACCESS(RwReg, 0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */
|
||||
#define REG_SSC_TFMR REG_ACCESS(RwReg, 0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */
|
||||
#define REG_SSC_RHR REG_ACCESS(RoReg, 0x40004020U) /**< \brief (SSC) Receive Holding Register */
|
||||
#define REG_SSC_THR REG_ACCESS(WoReg, 0x40004024U) /**< \brief (SSC) Transmit Holding Register */
|
||||
#define REG_SSC_RSHR REG_ACCESS(RoReg, 0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */
|
||||
#define REG_SSC_TSHR REG_ACCESS(RwReg, 0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */
|
||||
#define REG_SSC_RC0R REG_ACCESS(RwReg, 0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */
|
||||
#define REG_SSC_RC1R REG_ACCESS(RwReg, 0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */
|
||||
#define REG_SSC_SR REG_ACCESS(RoReg, 0x40004040U) /**< \brief (SSC) Status Register */
|
||||
#define REG_SSC_IER REG_ACCESS(WoReg, 0x40004044U) /**< \brief (SSC) Interrupt Enable Register */
|
||||
#define REG_SSC_IDR REG_ACCESS(WoReg, 0x40004048U) /**< \brief (SSC) Interrupt Disable Register */
|
||||
#define REG_SSC_IMR REG_ACCESS(RoReg, 0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */
|
||||
#define REG_SSC_WPMR REG_ACCESS(RwReg, 0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */
|
||||
#define REG_SSC_WPSR REG_ACCESS(RoReg, 0x400040E8U) /**< \brief (SSC) Write Protect Status Register */
|
||||
|
||||
#endif /* _SAM3U_SSC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_SUPC_INSTANCE_
|
||||
#define _SAM3U_SUPC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SUPC peripheral ========== */
|
||||
#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1214U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1218U) /**< \brief (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E121CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
|
||||
#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1220U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
|
||||
#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1224U) /**< \brief (SUPC) Supply Controller Status Register */
|
||||
|
||||
#endif /* _SAM3U_SUPC_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_TC0_INSTANCE_
|
||||
#define _SAM3U_TC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC0 peripheral ========== */
|
||||
#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
|
||||
#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
|
||||
#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
|
||||
#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
|
||||
#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
|
||||
#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
|
||||
#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
|
||||
#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
|
||||
#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
|
||||
#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
|
||||
#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
|
||||
#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
|
||||
#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
|
||||
#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
|
||||
#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
|
||||
#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
|
||||
#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
|
||||
#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
|
||||
#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400800C0U) /**< \brief (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400800C4U) /**< \brief (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
|
||||
|
||||
#endif /* _SAM3U_TC0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_TWI0_INSTANCE_
|
||||
#define _SAM3U_TWI0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TWI0 peripheral ========== */
|
||||
#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40084000U) /**< \brief (TWI0) Control Register */
|
||||
#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40084004U) /**< \brief (TWI0) Master Mode Register */
|
||||
#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40084008U) /**< \brief (TWI0) Slave Mode Register */
|
||||
#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4008400CU) /**< \brief (TWI0) Internal Address Register */
|
||||
#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40084010U) /**< \brief (TWI0) Clock Waveform Generator Register */
|
||||
#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40084020U) /**< \brief (TWI0) Status Register */
|
||||
#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40084024U) /**< \brief (TWI0) Interrupt Enable Register */
|
||||
#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40084028U) /**< \brief (TWI0) Interrupt Disable Register */
|
||||
#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4008402CU) /**< \brief (TWI0) Interrupt Mask Register */
|
||||
#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40084030U) /**< \brief (TWI0) Receive Holding Register */
|
||||
#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40084034U) /**< \brief (TWI0) Transmit Holding Register */
|
||||
#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40084100U) /**< \brief (TWI0) Receive Pointer Register */
|
||||
#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40084104U) /**< \brief (TWI0) Receive Counter Register */
|
||||
#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40084108U) /**< \brief (TWI0) Transmit Pointer Register */
|
||||
#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4008410CU) /**< \brief (TWI0) Transmit Counter Register */
|
||||
#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40084110U) /**< \brief (TWI0) Receive Next Pointer Register */
|
||||
#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40084114U) /**< \brief (TWI0) Receive Next Counter Register */
|
||||
#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40084118U) /**< \brief (TWI0) Transmit Next Pointer Register */
|
||||
#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4008411CU) /**< \brief (TWI0) Transmit Next Counter Register */
|
||||
#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40084120U) /**< \brief (TWI0) Transfer Control Register */
|
||||
#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40084124U) /**< \brief (TWI0) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_TWI0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_TWI1_INSTANCE_
|
||||
#define _SAM3U_TWI1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TWI1 peripheral ========== */
|
||||
#define REG_TWI1_CR REG_ACCESS(WoReg, 0x40088000U) /**< \brief (TWI1) Control Register */
|
||||
#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x40088004U) /**< \brief (TWI1) Master Mode Register */
|
||||
#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x40088008U) /**< \brief (TWI1) Slave Mode Register */
|
||||
#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4008800CU) /**< \brief (TWI1) Internal Address Register */
|
||||
#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x40088010U) /**< \brief (TWI1) Clock Waveform Generator Register */
|
||||
#define REG_TWI1_SR REG_ACCESS(RoReg, 0x40088020U) /**< \brief (TWI1) Status Register */
|
||||
#define REG_TWI1_IER REG_ACCESS(WoReg, 0x40088024U) /**< \brief (TWI1) Interrupt Enable Register */
|
||||
#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x40088028U) /**< \brief (TWI1) Interrupt Disable Register */
|
||||
#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4008802CU) /**< \brief (TWI1) Interrupt Mask Register */
|
||||
#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x40088030U) /**< \brief (TWI1) Receive Holding Register */
|
||||
#define REG_TWI1_THR REG_ACCESS(WoReg, 0x40088034U) /**< \brief (TWI1) Transmit Holding Register */
|
||||
#define REG_TWI1_RPR REG_ACCESS(RwReg, 0x40088100U) /**< \brief (TWI1) Receive Pointer Register */
|
||||
#define REG_TWI1_RCR REG_ACCESS(RwReg, 0x40088104U) /**< \brief (TWI1) Receive Counter Register */
|
||||
#define REG_TWI1_TPR REG_ACCESS(RwReg, 0x40088108U) /**< \brief (TWI1) Transmit Pointer Register */
|
||||
#define REG_TWI1_TCR REG_ACCESS(RwReg, 0x4008810CU) /**< \brief (TWI1) Transmit Counter Register */
|
||||
#define REG_TWI1_RNPR REG_ACCESS(RwReg, 0x40088110U) /**< \brief (TWI1) Receive Next Pointer Register */
|
||||
#define REG_TWI1_RNCR REG_ACCESS(RwReg, 0x40088114U) /**< \brief (TWI1) Receive Next Counter Register */
|
||||
#define REG_TWI1_TNPR REG_ACCESS(RwReg, 0x40088118U) /**< \brief (TWI1) Transmit Next Pointer Register */
|
||||
#define REG_TWI1_TNCR REG_ACCESS(RwReg, 0x4008811CU) /**< \brief (TWI1) Transmit Next Counter Register */
|
||||
#define REG_TWI1_PTCR REG_ACCESS(WoReg, 0x40088120U) /**< \brief (TWI1) Transfer Control Register */
|
||||
#define REG_TWI1_PTSR REG_ACCESS(RoReg, 0x40088124U) /**< \brief (TWI1) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_TWI1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_UART_INSTANCE_
|
||||
#define _SAM3U_UART_INSTANCE_
|
||||
|
||||
/* ========== Register definition for UART peripheral ========== */
|
||||
#define REG_UART_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART) Control Register */
|
||||
#define REG_UART_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART) Mode Register */
|
||||
#define REG_UART_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART) Interrupt Enable Register */
|
||||
#define REG_UART_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART) Interrupt Disable Register */
|
||||
#define REG_UART_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART) Interrupt Mask Register */
|
||||
#define REG_UART_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART) Status Register */
|
||||
#define REG_UART_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART) Receive Holding Register */
|
||||
#define REG_UART_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART) Transmit Holding Register */
|
||||
#define REG_UART_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART) Baud Rate Generator Register */
|
||||
#define REG_UART_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART) Receive Pointer Register */
|
||||
#define REG_UART_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART) Receive Counter Register */
|
||||
#define REG_UART_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART) Transmit Pointer Register */
|
||||
#define REG_UART_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART) Transmit Counter Register */
|
||||
#define REG_UART_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART) Receive Next Pointer Register */
|
||||
#define REG_UART_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART) Receive Next Counter Register */
|
||||
#define REG_UART_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART) Transmit Next Pointer Register */
|
||||
#define REG_UART_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART) Transmit Next Counter Register */
|
||||
#define REG_UART_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART) Transfer Control Register */
|
||||
#define REG_UART_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_UART_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_UDPHS_INSTANCE_
|
||||
#define _SAM3U_UDPHS_INSTANCE_
|
||||
|
||||
/* ========== Register definition for UDPHS peripheral ========== */
|
||||
#define REG_UDPHS_CTRL REG_ACCESS(RwReg, 0x400A4000U) /**< \brief (UDPHS) UDPHS Control Register */
|
||||
#define REG_UDPHS_FNUM REG_ACCESS(RoReg, 0x400A4004U) /**< \brief (UDPHS) UDPHS Frame Number Register */
|
||||
#define REG_UDPHS_IEN REG_ACCESS(RwReg, 0x400A4010U) /**< \brief (UDPHS) UDPHS Interrupt Enable Register */
|
||||
#define REG_UDPHS_INTSTA REG_ACCESS(RoReg, 0x400A4014U) /**< \brief (UDPHS) UDPHS Interrupt Status Register */
|
||||
#define REG_UDPHS_CLRINT REG_ACCESS(WoReg, 0x400A4018U) /**< \brief (UDPHS) UDPHS Clear Interrupt Register */
|
||||
#define REG_UDPHS_EPTRST REG_ACCESS(WoReg, 0x400A401CU) /**< \brief (UDPHS) UDPHS Endpoints Reset Register */
|
||||
#define REG_UDPHS_TST REG_ACCESS(RwReg, 0x400A40E0U) /**< \brief (UDPHS) UDPHS Test Register */
|
||||
#define REG_UDPHS_IPNAME1 REG_ACCESS(RoReg, 0x400A40F0U) /**< \brief (UDPHS) UDPHS Name1 Register */
|
||||
#define REG_UDPHS_IPNAME2 REG_ACCESS(RoReg, 0x400A40F4U) /**< \brief (UDPHS) UDPHS Name2 Register */
|
||||
#define REG_UDPHS_IPFEATURES REG_ACCESS(RoReg, 0x400A40F8U) /**< \brief (UDPHS) UDPHS Features Register */
|
||||
#define REG_UDPHS_EPTCFG0 REG_ACCESS(RwReg, 0x400A4100U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTCTLENB0 REG_ACCESS(WoReg, 0x400A4104U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTCTLDIS0 REG_ACCESS(WoReg, 0x400A4108U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTCTL0 REG_ACCESS(RoReg, 0x400A410CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTSETSTA0 REG_ACCESS(WoReg, 0x400A4114U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTCLRSTA0 REG_ACCESS(WoReg, 0x400A4118U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTSTA0 REG_ACCESS(RoReg, 0x400A411CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 0) */
|
||||
#define REG_UDPHS_EPTCFG1 REG_ACCESS(RwReg, 0x400A4120U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTCTLENB1 REG_ACCESS(WoReg, 0x400A4124U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTCTLDIS1 REG_ACCESS(WoReg, 0x400A4128U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTCTL1 REG_ACCESS(RoReg, 0x400A412CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTSETSTA1 REG_ACCESS(WoReg, 0x400A4134U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTCLRSTA1 REG_ACCESS(WoReg, 0x400A4138U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTSTA1 REG_ACCESS(RoReg, 0x400A413CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 1) */
|
||||
#define REG_UDPHS_EPTCFG2 REG_ACCESS(RwReg, 0x400A4140U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTCTLENB2 REG_ACCESS(WoReg, 0x400A4144U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTCTLDIS2 REG_ACCESS(WoReg, 0x400A4148U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTCTL2 REG_ACCESS(RoReg, 0x400A414CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTSETSTA2 REG_ACCESS(WoReg, 0x400A4154U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTCLRSTA2 REG_ACCESS(WoReg, 0x400A4158U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTSTA2 REG_ACCESS(RoReg, 0x400A415CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 2) */
|
||||
#define REG_UDPHS_EPTCFG3 REG_ACCESS(RwReg, 0x400A4160U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTCTLENB3 REG_ACCESS(WoReg, 0x400A4164U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTCTLDIS3 REG_ACCESS(WoReg, 0x400A4168U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTCTL3 REG_ACCESS(RoReg, 0x400A416CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTSETSTA3 REG_ACCESS(WoReg, 0x400A4174U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTCLRSTA3 REG_ACCESS(WoReg, 0x400A4178U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTSTA3 REG_ACCESS(RoReg, 0x400A417CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 3) */
|
||||
#define REG_UDPHS_EPTCFG4 REG_ACCESS(RwReg, 0x400A4180U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTCTLENB4 REG_ACCESS(WoReg, 0x400A4184U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTCTLDIS4 REG_ACCESS(WoReg, 0x400A4188U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTCTL4 REG_ACCESS(RoReg, 0x400A418CU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTSETSTA4 REG_ACCESS(WoReg, 0x400A4194U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTCLRSTA4 REG_ACCESS(WoReg, 0x400A4198U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTSTA4 REG_ACCESS(RoReg, 0x400A419CU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 4) */
|
||||
#define REG_UDPHS_EPTCFG5 REG_ACCESS(RwReg, 0x400A41A0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTCTLENB5 REG_ACCESS(WoReg, 0x400A41A4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTCTLDIS5 REG_ACCESS(WoReg, 0x400A41A8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTCTL5 REG_ACCESS(RoReg, 0x400A41ACU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTSETSTA5 REG_ACCESS(WoReg, 0x400A41B4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTCLRSTA5 REG_ACCESS(WoReg, 0x400A41B8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTSTA5 REG_ACCESS(RoReg, 0x400A41BCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 5) */
|
||||
#define REG_UDPHS_EPTCFG6 REG_ACCESS(RwReg, 0x400A41C0U) /**< \brief (UDPHS) UDPHS Endpoint Configuration Register (endpoint = 6) */
|
||||
#define REG_UDPHS_EPTCTLENB6 REG_ACCESS(WoReg, 0x400A41C4U) /**< \brief (UDPHS) UDPHS Endpoint Control Enable Register (endpoint = 6) */
|
||||
#define REG_UDPHS_EPTCTLDIS6 REG_ACCESS(WoReg, 0x400A41C8U) /**< \brief (UDPHS) UDPHS Endpoint Control Disable Register (endpoint = 6) */
|
||||
#define REG_UDPHS_EPTCTL6 REG_ACCESS(RoReg, 0x400A41CCU) /**< \brief (UDPHS) UDPHS Endpoint Control Register (endpoint = 6) */
|
||||
#define REG_UDPHS_EPTSETSTA6 REG_ACCESS(WoReg, 0x400A41D4U) /**< \brief (UDPHS) UDPHS Endpoint Set Status Register (endpoint = 6) */
|
||||
#define REG_UDPHS_EPTCLRSTA6 REG_ACCESS(WoReg, 0x400A41D8U) /**< \brief (UDPHS) UDPHS Endpoint Clear Status Register (endpoint = 6) */
|
||||
#define REG_UDPHS_EPTSTA6 REG_ACCESS(RoReg, 0x400A41DCU) /**< \brief (UDPHS) UDPHS Endpoint Status Register (endpoint = 6) */
|
||||
#define REG_UDPHS_DMANXTDSC0 REG_ACCESS(RwReg, 0x400A4300U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 0) */
|
||||
#define REG_UDPHS_DMAADDRESS0 REG_ACCESS(RwReg, 0x400A4304U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 0) */
|
||||
#define REG_UDPHS_DMACONTROL0 REG_ACCESS(RwReg, 0x400A4308U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 0) */
|
||||
#define REG_UDPHS_DMASTATUS0 REG_ACCESS(RwReg, 0x400A430CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 0) */
|
||||
#define REG_UDPHS_DMANXTDSC1 REG_ACCESS(RwReg, 0x400A4310U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 1) */
|
||||
#define REG_UDPHS_DMAADDRESS1 REG_ACCESS(RwReg, 0x400A4314U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 1) */
|
||||
#define REG_UDPHS_DMACONTROL1 REG_ACCESS(RwReg, 0x400A4318U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 1) */
|
||||
#define REG_UDPHS_DMASTATUS1 REG_ACCESS(RwReg, 0x400A431CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 1) */
|
||||
#define REG_UDPHS_DMANXTDSC2 REG_ACCESS(RwReg, 0x400A4320U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 2) */
|
||||
#define REG_UDPHS_DMAADDRESS2 REG_ACCESS(RwReg, 0x400A4324U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 2) */
|
||||
#define REG_UDPHS_DMACONTROL2 REG_ACCESS(RwReg, 0x400A4328U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 2) */
|
||||
#define REG_UDPHS_DMASTATUS2 REG_ACCESS(RwReg, 0x400A432CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 2) */
|
||||
#define REG_UDPHS_DMANXTDSC3 REG_ACCESS(RwReg, 0x400A4330U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 3) */
|
||||
#define REG_UDPHS_DMAADDRESS3 REG_ACCESS(RwReg, 0x400A4334U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 3) */
|
||||
#define REG_UDPHS_DMACONTROL3 REG_ACCESS(RwReg, 0x400A4338U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 3) */
|
||||
#define REG_UDPHS_DMASTATUS3 REG_ACCESS(RwReg, 0x400A433CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 3) */
|
||||
#define REG_UDPHS_DMANXTDSC4 REG_ACCESS(RwReg, 0x400A4340U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 4) */
|
||||
#define REG_UDPHS_DMAADDRESS4 REG_ACCESS(RwReg, 0x400A4344U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 4) */
|
||||
#define REG_UDPHS_DMACONTROL4 REG_ACCESS(RwReg, 0x400A4348U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 4) */
|
||||
#define REG_UDPHS_DMASTATUS4 REG_ACCESS(RwReg, 0x400A434CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 4) */
|
||||
#define REG_UDPHS_DMANXTDSC5 REG_ACCESS(RwReg, 0x400A4350U) /**< \brief (UDPHS) UDPHS DMA Next Descriptor Address Register (channel = 5) */
|
||||
#define REG_UDPHS_DMAADDRESS5 REG_ACCESS(RwReg, 0x400A4354U) /**< \brief (UDPHS) UDPHS DMA Channel Address Register (channel = 5) */
|
||||
#define REG_UDPHS_DMACONTROL5 REG_ACCESS(RwReg, 0x400A4358U) /**< \brief (UDPHS) UDPHS DMA Channel Control Register (channel = 5) */
|
||||
#define REG_UDPHS_DMASTATUS5 REG_ACCESS(RwReg, 0x400A435CU) /**< \brief (UDPHS) UDPHS DMA Channel Status Register (channel = 5) */
|
||||
|
||||
#endif /* _SAM3U_UDPHS_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_USART0_INSTANCE_
|
||||
#define _SAM3U_USART0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART0 peripheral ========== */
|
||||
#define REG_USART0_CR REG_ACCESS(WoReg, 0x40090000U) /**< \brief (USART0) Control Register */
|
||||
#define REG_USART0_MR REG_ACCESS(RwReg, 0x40090004U) /**< \brief (USART0) Mode Register */
|
||||
#define REG_USART0_IER REG_ACCESS(WoReg, 0x40090008U) /**< \brief (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4009000CU) /**< \brief (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40090010U) /**< \brief (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40090014U) /**< \brief (USART0) Channel Status Register */
|
||||
#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40090018U) /**< \brief (USART0) Receiver Holding Register */
|
||||
#define REG_USART0_THR REG_ACCESS(WoReg, 0x4009001CU) /**< \brief (USART0) Transmitter Holding Register */
|
||||
#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40090020U) /**< \brief (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40090024U) /**< \brief (USART0) Receiver Time-out Register */
|
||||
#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40090028U) /**< \brief (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40090040U) /**< \brief (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_NER REG_ACCESS(RoReg, 0x40090044U) /**< \brief (USART0) Number of Errors Register */
|
||||
#define REG_USART0_IF REG_ACCESS(RwReg, 0x4009004CU) /**< \brief (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_MAN REG_ACCESS(RwReg, 0x40090050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
|
||||
#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400900E4U) /**< \brief (USART0) Write Protect Mode Register */
|
||||
#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400900E8U) /**< \brief (USART0) Write Protect Status Register */
|
||||
#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40090100U) /**< \brief (USART0) Receive Pointer Register */
|
||||
#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40090104U) /**< \brief (USART0) Receive Counter Register */
|
||||
#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40090108U) /**< \brief (USART0) Transmit Pointer Register */
|
||||
#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4009010CU) /**< \brief (USART0) Transmit Counter Register */
|
||||
#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40090110U) /**< \brief (USART0) Receive Next Pointer Register */
|
||||
#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40090114U) /**< \brief (USART0) Receive Next Counter Register */
|
||||
#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40090118U) /**< \brief (USART0) Transmit Next Pointer Register */
|
||||
#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4009011CU) /**< \brief (USART0) Transmit Next Counter Register */
|
||||
#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40090120U) /**< \brief (USART0) Transfer Control Register */
|
||||
#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40090124U) /**< \brief (USART0) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_USART0_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_USART1_INSTANCE_
|
||||
#define _SAM3U_USART1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART1 peripheral ========== */
|
||||
#define REG_USART1_CR REG_ACCESS(WoReg, 0x40094000U) /**< \brief (USART1) Control Register */
|
||||
#define REG_USART1_MR REG_ACCESS(RwReg, 0x40094004U) /**< \brief (USART1) Mode Register */
|
||||
#define REG_USART1_IER REG_ACCESS(WoReg, 0x40094008U) /**< \brief (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4009400CU) /**< \brief (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40094010U) /**< \brief (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40094014U) /**< \brief (USART1) Channel Status Register */
|
||||
#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40094018U) /**< \brief (USART1) Receiver Holding Register */
|
||||
#define REG_USART1_THR REG_ACCESS(WoReg, 0x4009401CU) /**< \brief (USART1) Transmitter Holding Register */
|
||||
#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40094020U) /**< \brief (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40094024U) /**< \brief (USART1) Receiver Time-out Register */
|
||||
#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40094028U) /**< \brief (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40094040U) /**< \brief (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_NER REG_ACCESS(RoReg, 0x40094044U) /**< \brief (USART1) Number of Errors Register */
|
||||
#define REG_USART1_IF REG_ACCESS(RwReg, 0x4009404CU) /**< \brief (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_MAN REG_ACCESS(RwReg, 0x40094050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
|
||||
#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400940E4U) /**< \brief (USART1) Write Protect Mode Register */
|
||||
#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400940E8U) /**< \brief (USART1) Write Protect Status Register */
|
||||
#define REG_USART1_RPR REG_ACCESS(RwReg, 0x40094100U) /**< \brief (USART1) Receive Pointer Register */
|
||||
#define REG_USART1_RCR REG_ACCESS(RwReg, 0x40094104U) /**< \brief (USART1) Receive Counter Register */
|
||||
#define REG_USART1_TPR REG_ACCESS(RwReg, 0x40094108U) /**< \brief (USART1) Transmit Pointer Register */
|
||||
#define REG_USART1_TCR REG_ACCESS(RwReg, 0x4009410CU) /**< \brief (USART1) Transmit Counter Register */
|
||||
#define REG_USART1_RNPR REG_ACCESS(RwReg, 0x40094110U) /**< \brief (USART1) Receive Next Pointer Register */
|
||||
#define REG_USART1_RNCR REG_ACCESS(RwReg, 0x40094114U) /**< \brief (USART1) Receive Next Counter Register */
|
||||
#define REG_USART1_TNPR REG_ACCESS(RwReg, 0x40094118U) /**< \brief (USART1) Transmit Next Pointer Register */
|
||||
#define REG_USART1_TNCR REG_ACCESS(RwReg, 0x4009411CU) /**< \brief (USART1) Transmit Next Counter Register */
|
||||
#define REG_USART1_PTCR REG_ACCESS(WoReg, 0x40094120U) /**< \brief (USART1) Transfer Control Register */
|
||||
#define REG_USART1_PTSR REG_ACCESS(RoReg, 0x40094124U) /**< \brief (USART1) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_USART1_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_USART2_INSTANCE_
|
||||
#define _SAM3U_USART2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART2 peripheral ========== */
|
||||
#define REG_USART2_CR REG_ACCESS(WoReg, 0x40098000U) /**< \brief (USART2) Control Register */
|
||||
#define REG_USART2_MR REG_ACCESS(RwReg, 0x40098004U) /**< \brief (USART2) Mode Register */
|
||||
#define REG_USART2_IER REG_ACCESS(WoReg, 0x40098008U) /**< \brief (USART2) Interrupt Enable Register */
|
||||
#define REG_USART2_IDR REG_ACCESS(WoReg, 0x4009800CU) /**< \brief (USART2) Interrupt Disable Register */
|
||||
#define REG_USART2_IMR REG_ACCESS(RoReg, 0x40098010U) /**< \brief (USART2) Interrupt Mask Register */
|
||||
#define REG_USART2_CSR REG_ACCESS(RoReg, 0x40098014U) /**< \brief (USART2) Channel Status Register */
|
||||
#define REG_USART2_RHR REG_ACCESS(RoReg, 0x40098018U) /**< \brief (USART2) Receiver Holding Register */
|
||||
#define REG_USART2_THR REG_ACCESS(WoReg, 0x4009801CU) /**< \brief (USART2) Transmitter Holding Register */
|
||||
#define REG_USART2_BRGR REG_ACCESS(RwReg, 0x40098020U) /**< \brief (USART2) Baud Rate Generator Register */
|
||||
#define REG_USART2_RTOR REG_ACCESS(RwReg, 0x40098024U) /**< \brief (USART2) Receiver Time-out Register */
|
||||
#define REG_USART2_TTGR REG_ACCESS(RwReg, 0x40098028U) /**< \brief (USART2) Transmitter Timeguard Register */
|
||||
#define REG_USART2_FIDI REG_ACCESS(RwReg, 0x40098040U) /**< \brief (USART2) FI DI Ratio Register */
|
||||
#define REG_USART2_NER REG_ACCESS(RoReg, 0x40098044U) /**< \brief (USART2) Number of Errors Register */
|
||||
#define REG_USART2_IF REG_ACCESS(RwReg, 0x4009804CU) /**< \brief (USART2) IrDA Filter Register */
|
||||
#define REG_USART2_MAN REG_ACCESS(RwReg, 0x40098050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
|
||||
#define REG_USART2_WPMR REG_ACCESS(RwReg, 0x400980E4U) /**< \brief (USART2) Write Protect Mode Register */
|
||||
#define REG_USART2_WPSR REG_ACCESS(RoReg, 0x400980E8U) /**< \brief (USART2) Write Protect Status Register */
|
||||
#define REG_USART2_RPR REG_ACCESS(RwReg, 0x40098100U) /**< \brief (USART2) Receive Pointer Register */
|
||||
#define REG_USART2_RCR REG_ACCESS(RwReg, 0x40098104U) /**< \brief (USART2) Receive Counter Register */
|
||||
#define REG_USART2_TPR REG_ACCESS(RwReg, 0x40098108U) /**< \brief (USART2) Transmit Pointer Register */
|
||||
#define REG_USART2_TCR REG_ACCESS(RwReg, 0x4009810CU) /**< \brief (USART2) Transmit Counter Register */
|
||||
#define REG_USART2_RNPR REG_ACCESS(RwReg, 0x40098110U) /**< \brief (USART2) Receive Next Pointer Register */
|
||||
#define REG_USART2_RNCR REG_ACCESS(RwReg, 0x40098114U) /**< \brief (USART2) Receive Next Counter Register */
|
||||
#define REG_USART2_TNPR REG_ACCESS(RwReg, 0x40098118U) /**< \brief (USART2) Transmit Next Pointer Register */
|
||||
#define REG_USART2_TNCR REG_ACCESS(RwReg, 0x4009811CU) /**< \brief (USART2) Transmit Next Counter Register */
|
||||
#define REG_USART2_PTCR REG_ACCESS(WoReg, 0x40098120U) /**< \brief (USART2) Transfer Control Register */
|
||||
#define REG_USART2_PTSR REG_ACCESS(RoReg, 0x40098124U) /**< \brief (USART2) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_USART2_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_USART3_INSTANCE_
|
||||
#define _SAM3U_USART3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART3 peripheral ========== */
|
||||
#define REG_USART3_CR REG_ACCESS(WoReg, 0x4009C000U) /**< \brief (USART3) Control Register */
|
||||
#define REG_USART3_MR REG_ACCESS(RwReg, 0x4009C004U) /**< \brief (USART3) Mode Register */
|
||||
#define REG_USART3_IER REG_ACCESS(WoReg, 0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
|
||||
#define REG_USART3_IDR REG_ACCESS(WoReg, 0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
|
||||
#define REG_USART3_IMR REG_ACCESS(RoReg, 0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
|
||||
#define REG_USART3_CSR REG_ACCESS(RoReg, 0x4009C014U) /**< \brief (USART3) Channel Status Register */
|
||||
#define REG_USART3_RHR REG_ACCESS(RoReg, 0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
|
||||
#define REG_USART3_THR REG_ACCESS(WoReg, 0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
|
||||
#define REG_USART3_BRGR REG_ACCESS(RwReg, 0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
|
||||
#define REG_USART3_RTOR REG_ACCESS(RwReg, 0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
|
||||
#define REG_USART3_TTGR REG_ACCESS(RwReg, 0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
|
||||
#define REG_USART3_FIDI REG_ACCESS(RwReg, 0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
|
||||
#define REG_USART3_NER REG_ACCESS(RoReg, 0x4009C044U) /**< \brief (USART3) Number of Errors Register */
|
||||
#define REG_USART3_IF REG_ACCESS(RwReg, 0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
|
||||
#define REG_USART3_MAN REG_ACCESS(RwReg, 0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
|
||||
#define REG_USART3_WPMR REG_ACCESS(RwReg, 0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
|
||||
#define REG_USART3_WPSR REG_ACCESS(RoReg, 0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
|
||||
#define REG_USART3_RPR REG_ACCESS(RwReg, 0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
|
||||
#define REG_USART3_RCR REG_ACCESS(RwReg, 0x4009C104U) /**< \brief (USART3) Receive Counter Register */
|
||||
#define REG_USART3_TPR REG_ACCESS(RwReg, 0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
|
||||
#define REG_USART3_TCR REG_ACCESS(RwReg, 0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
|
||||
#define REG_USART3_RNPR REG_ACCESS(RwReg, 0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
|
||||
#define REG_USART3_RNCR REG_ACCESS(RwReg, 0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
|
||||
#define REG_USART3_TNPR REG_ACCESS(RwReg, 0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
|
||||
#define REG_USART3_TNCR REG_ACCESS(RwReg, 0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
|
||||
#define REG_USART3_PTCR REG_ACCESS(WoReg, 0x4009C120U) /**< \brief (USART3) Transfer Control Register */
|
||||
#define REG_USART3_PTSR REG_ACCESS(RoReg, 0x4009C124U) /**< \brief (USART3) Transfer Status Register */
|
||||
|
||||
#endif /* _SAM3U_USART3_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_WDT_INSTANCE_
|
||||
#define _SAM3U_WDT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (WDT) Control Register */
|
||||
#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1254U) /**< \brief (WDT) Mode Register */
|
||||
#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (WDT) Status Register */
|
||||
|
||||
#endif /* _SAM3U_WDT_INSTANCE_ */
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U1C_PIO_
|
||||
#define _SAM3U1C_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
|
||||
#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
|
||||
#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
|
||||
#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
|
||||
#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
|
||||
#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
|
||||
#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
|
||||
#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
|
||||
#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
|
||||
#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */
|
||||
#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */
|
||||
#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */
|
||||
#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for ADC12B peripheral ========== */
|
||||
#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
|
||||
#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
|
||||
#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */
|
||||
#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */
|
||||
#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
|
||||
#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
|
||||
#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
|
||||
#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
|
||||
#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */
|
||||
/* ========== Pio definition for EBI peripheral ========== */
|
||||
#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */
|
||||
#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */
|
||||
#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */
|
||||
#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */
|
||||
#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */
|
||||
#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */
|
||||
#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */
|
||||
#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */
|
||||
#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */
|
||||
#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */
|
||||
#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */
|
||||
#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */
|
||||
#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */
|
||||
#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */
|
||||
#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */
|
||||
#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */
|
||||
#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */
|
||||
#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */
|
||||
#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */
|
||||
#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */
|
||||
#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */
|
||||
#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */
|
||||
#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */
|
||||
#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */
|
||||
#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */
|
||||
#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */
|
||||
#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */
|
||||
#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */
|
||||
#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */
|
||||
#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */
|
||||
#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */
|
||||
#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */
|
||||
#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
|
||||
#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */
|
||||
#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */
|
||||
#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */
|
||||
#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */
|
||||
#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */
|
||||
#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */
|
||||
#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
/* ========== Pio definition for HSMCI peripheral ========== */
|
||||
#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */
|
||||
#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */
|
||||
#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */
|
||||
#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */
|
||||
#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */
|
||||
#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */
|
||||
#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */
|
||||
#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */
|
||||
#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */
|
||||
#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */
|
||||
#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */
|
||||
#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */
|
||||
#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for SSC peripheral ========== */
|
||||
#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */
|
||||
#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */
|
||||
#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */
|
||||
#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */
|
||||
#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */
|
||||
#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART peripheral ========== */
|
||||
#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */
|
||||
#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */
|
||||
#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */
|
||||
#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */
|
||||
#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */
|
||||
#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio definition for USART2 peripheral ========== */
|
||||
#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */
|
||||
#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */
|
||||
#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */
|
||||
#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */
|
||||
#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PB15_IDX 47
|
||||
#define PIO_PB16_IDX 48
|
||||
#define PIO_PB17_IDX 49
|
||||
#define PIO_PB18_IDX 50
|
||||
#define PIO_PB19_IDX 51
|
||||
#define PIO_PB20_IDX 52
|
||||
#define PIO_PB21_IDX 53
|
||||
#define PIO_PB22_IDX 54
|
||||
#define PIO_PB23_IDX 55
|
||||
#define PIO_PB24_IDX 56
|
||||
|
||||
#endif /* _SAM3U1C_PIO_ */
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U1E_PIO_
|
||||
#define _SAM3U1E_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
|
||||
#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
|
||||
#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
|
||||
#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
|
||||
#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
|
||||
#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
|
||||
#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
|
||||
#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
|
||||
#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
|
||||
#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
|
||||
#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */
|
||||
#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */
|
||||
#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */
|
||||
#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */
|
||||
#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */
|
||||
#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */
|
||||
#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */
|
||||
#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
|
||||
#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
|
||||
#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
|
||||
#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
|
||||
#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
|
||||
#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
|
||||
#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
|
||||
#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
|
||||
#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
|
||||
#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
|
||||
#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
|
||||
#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
|
||||
#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
|
||||
#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
|
||||
#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
|
||||
#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
|
||||
#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
|
||||
#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
|
||||
#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
|
||||
#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
|
||||
#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
|
||||
#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
|
||||
#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
|
||||
#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
|
||||
#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
|
||||
#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
|
||||
#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
|
||||
#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
|
||||
#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
|
||||
#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
|
||||
#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
|
||||
#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */
|
||||
#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */
|
||||
#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */
|
||||
#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for ADC12B peripheral ========== */
|
||||
#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
|
||||
#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
|
||||
#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */
|
||||
#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */
|
||||
#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
|
||||
#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
|
||||
#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
|
||||
#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
|
||||
#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */
|
||||
/* ========== Pio definition for EBI peripheral ========== */
|
||||
#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */
|
||||
#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */
|
||||
#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */
|
||||
#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */
|
||||
#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */
|
||||
#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */
|
||||
#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */
|
||||
#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */
|
||||
#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */
|
||||
#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */
|
||||
#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */
|
||||
#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */
|
||||
#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */
|
||||
#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */
|
||||
#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */
|
||||
#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */
|
||||
#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */
|
||||
#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */
|
||||
#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */
|
||||
#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */
|
||||
#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */
|
||||
#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */
|
||||
#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */
|
||||
#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */
|
||||
#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */
|
||||
#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */
|
||||
#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */
|
||||
#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */
|
||||
#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */
|
||||
#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */
|
||||
#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */
|
||||
#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */
|
||||
#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
|
||||
#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */
|
||||
#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */
|
||||
#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */
|
||||
#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */
|
||||
#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */
|
||||
#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */
|
||||
#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
/* ========== Pio definition for HSMCI peripheral ========== */
|
||||
#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */
|
||||
#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */
|
||||
#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */
|
||||
#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */
|
||||
#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */
|
||||
#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */
|
||||
#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */
|
||||
#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */
|
||||
#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */
|
||||
#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */
|
||||
#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */
|
||||
#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */
|
||||
#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for SSC peripheral ========== */
|
||||
#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */
|
||||
#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */
|
||||
#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */
|
||||
#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */
|
||||
#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */
|
||||
#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART peripheral ========== */
|
||||
#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */
|
||||
#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */
|
||||
#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */
|
||||
#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */
|
||||
#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */
|
||||
#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio definition for USART2 peripheral ========== */
|
||||
#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */
|
||||
#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */
|
||||
#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */
|
||||
#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */
|
||||
#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */
|
||||
/* ========== Pio definition for USART3 peripheral ========== */
|
||||
#define PIO_PC10B_CTS3 (1u << 10) /**< \brief Usart3 signal: CTS3 */
|
||||
#define PIO_PC11B_RTS3 (1u << 11) /**< \brief Usart3 signal: RTS3 */
|
||||
#define PIO_PC13B_RXD3 (1u << 13) /**< \brief Usart3 signal: RXD3 */
|
||||
#define PIO_PC19A_SCK3 (1u << 19) /**< \brief Usart3 signal: SCK3 */
|
||||
#define PIO_PC12B_TXD3 (1u << 12) /**< \brief Usart3 signal: TXD3 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PB15_IDX 47
|
||||
#define PIO_PB16_IDX 48
|
||||
#define PIO_PB17_IDX 49
|
||||
#define PIO_PB18_IDX 50
|
||||
#define PIO_PB19_IDX 51
|
||||
#define PIO_PB20_IDX 52
|
||||
#define PIO_PB21_IDX 53
|
||||
#define PIO_PB22_IDX 54
|
||||
#define PIO_PB23_IDX 55
|
||||
#define PIO_PB24_IDX 56
|
||||
#define PIO_PB25_IDX 57
|
||||
#define PIO_PB26_IDX 58
|
||||
#define PIO_PB27_IDX 59
|
||||
#define PIO_PB28_IDX 60
|
||||
#define PIO_PB29_IDX 61
|
||||
#define PIO_PB30_IDX 62
|
||||
#define PIO_PB31_IDX 63
|
||||
#define PIO_PC0_IDX 64
|
||||
#define PIO_PC1_IDX 65
|
||||
#define PIO_PC2_IDX 66
|
||||
#define PIO_PC3_IDX 67
|
||||
#define PIO_PC4_IDX 68
|
||||
#define PIO_PC5_IDX 69
|
||||
#define PIO_PC6_IDX 70
|
||||
#define PIO_PC7_IDX 71
|
||||
#define PIO_PC8_IDX 72
|
||||
#define PIO_PC9_IDX 73
|
||||
#define PIO_PC10_IDX 74
|
||||
#define PIO_PC11_IDX 75
|
||||
#define PIO_PC12_IDX 76
|
||||
#define PIO_PC13_IDX 77
|
||||
#define PIO_PC14_IDX 78
|
||||
#define PIO_PC15_IDX 79
|
||||
#define PIO_PC16_IDX 80
|
||||
#define PIO_PC17_IDX 81
|
||||
#define PIO_PC18_IDX 82
|
||||
#define PIO_PC19_IDX 83
|
||||
#define PIO_PC20_IDX 84
|
||||
#define PIO_PC21_IDX 85
|
||||
#define PIO_PC22_IDX 86
|
||||
#define PIO_PC23_IDX 87
|
||||
#define PIO_PC24_IDX 88
|
||||
#define PIO_PC25_IDX 89
|
||||
#define PIO_PC26_IDX 90
|
||||
#define PIO_PC27_IDX 91
|
||||
#define PIO_PC28_IDX 92
|
||||
#define PIO_PC29_IDX 93
|
||||
#define PIO_PC30_IDX 94
|
||||
#define PIO_PC31_IDX 95
|
||||
|
||||
#endif /* _SAM3U1E_PIO_ */
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U2C_PIO_
|
||||
#define _SAM3U2C_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
|
||||
#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
|
||||
#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
|
||||
#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
|
||||
#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
|
||||
#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
|
||||
#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
|
||||
#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
|
||||
#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
|
||||
#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */
|
||||
#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */
|
||||
#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */
|
||||
#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for ADC12B peripheral ========== */
|
||||
#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
|
||||
#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
|
||||
#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */
|
||||
#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */
|
||||
#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
|
||||
#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
|
||||
#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
|
||||
#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
|
||||
#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */
|
||||
/* ========== Pio definition for EBI peripheral ========== */
|
||||
#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */
|
||||
#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */
|
||||
#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */
|
||||
#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */
|
||||
#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */
|
||||
#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */
|
||||
#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */
|
||||
#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */
|
||||
#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */
|
||||
#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */
|
||||
#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */
|
||||
#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */
|
||||
#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */
|
||||
#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */
|
||||
#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */
|
||||
#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */
|
||||
#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */
|
||||
#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */
|
||||
#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */
|
||||
#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */
|
||||
#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */
|
||||
#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */
|
||||
#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */
|
||||
#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */
|
||||
#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */
|
||||
#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */
|
||||
#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */
|
||||
#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */
|
||||
#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */
|
||||
#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */
|
||||
#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */
|
||||
#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */
|
||||
#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
|
||||
#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */
|
||||
#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */
|
||||
#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */
|
||||
#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */
|
||||
#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */
|
||||
#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */
|
||||
#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
/* ========== Pio definition for HSMCI peripheral ========== */
|
||||
#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */
|
||||
#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */
|
||||
#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */
|
||||
#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */
|
||||
#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */
|
||||
#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */
|
||||
#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */
|
||||
#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */
|
||||
#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */
|
||||
#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */
|
||||
#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */
|
||||
#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */
|
||||
#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for SSC peripheral ========== */
|
||||
#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */
|
||||
#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */
|
||||
#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */
|
||||
#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */
|
||||
#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */
|
||||
#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART peripheral ========== */
|
||||
#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */
|
||||
#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */
|
||||
#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */
|
||||
#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */
|
||||
#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */
|
||||
#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio definition for USART2 peripheral ========== */
|
||||
#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */
|
||||
#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */
|
||||
#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */
|
||||
#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */
|
||||
#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PB15_IDX 47
|
||||
#define PIO_PB16_IDX 48
|
||||
#define PIO_PB17_IDX 49
|
||||
#define PIO_PB18_IDX 50
|
||||
#define PIO_PB19_IDX 51
|
||||
#define PIO_PB20_IDX 52
|
||||
#define PIO_PB21_IDX 53
|
||||
#define PIO_PB22_IDX 54
|
||||
#define PIO_PB23_IDX 55
|
||||
#define PIO_PB24_IDX 56
|
||||
|
||||
#endif /* _SAM3U2C_PIO_ */
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U2E_PIO_
|
||||
#define _SAM3U2E_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
|
||||
#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
|
||||
#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
|
||||
#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
|
||||
#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
|
||||
#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
|
||||
#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
|
||||
#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
|
||||
#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
|
||||
#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
|
||||
#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */
|
||||
#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */
|
||||
#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */
|
||||
#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */
|
||||
#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */
|
||||
#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */
|
||||
#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */
|
||||
#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
|
||||
#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
|
||||
#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
|
||||
#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
|
||||
#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
|
||||
#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
|
||||
#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
|
||||
#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
|
||||
#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
|
||||
#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
|
||||
#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
|
||||
#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
|
||||
#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
|
||||
#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
|
||||
#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
|
||||
#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
|
||||
#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
|
||||
#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
|
||||
#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
|
||||
#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
|
||||
#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
|
||||
#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
|
||||
#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
|
||||
#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
|
||||
#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
|
||||
#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
|
||||
#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
|
||||
#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
|
||||
#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
|
||||
#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
|
||||
#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
|
||||
#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */
|
||||
#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */
|
||||
#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */
|
||||
#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for ADC12B peripheral ========== */
|
||||
#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
|
||||
#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
|
||||
#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */
|
||||
#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */
|
||||
#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
|
||||
#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
|
||||
#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
|
||||
#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
|
||||
#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */
|
||||
/* ========== Pio definition for EBI peripheral ========== */
|
||||
#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */
|
||||
#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */
|
||||
#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */
|
||||
#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */
|
||||
#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */
|
||||
#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */
|
||||
#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */
|
||||
#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */
|
||||
#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */
|
||||
#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */
|
||||
#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */
|
||||
#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */
|
||||
#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */
|
||||
#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */
|
||||
#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */
|
||||
#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */
|
||||
#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */
|
||||
#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */
|
||||
#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */
|
||||
#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */
|
||||
#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */
|
||||
#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */
|
||||
#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */
|
||||
#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */
|
||||
#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */
|
||||
#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */
|
||||
#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */
|
||||
#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */
|
||||
#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */
|
||||
#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */
|
||||
#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */
|
||||
#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */
|
||||
#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
|
||||
#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */
|
||||
#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */
|
||||
#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */
|
||||
#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */
|
||||
#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */
|
||||
#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */
|
||||
#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
/* ========== Pio definition for HSMCI peripheral ========== */
|
||||
#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */
|
||||
#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */
|
||||
#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */
|
||||
#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */
|
||||
#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */
|
||||
#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */
|
||||
#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */
|
||||
#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */
|
||||
#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */
|
||||
#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */
|
||||
#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */
|
||||
#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */
|
||||
#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for SSC peripheral ========== */
|
||||
#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */
|
||||
#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */
|
||||
#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */
|
||||
#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */
|
||||
#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */
|
||||
#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART peripheral ========== */
|
||||
#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */
|
||||
#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */
|
||||
#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */
|
||||
#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */
|
||||
#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */
|
||||
#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio definition for USART2 peripheral ========== */
|
||||
#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */
|
||||
#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */
|
||||
#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */
|
||||
#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */
|
||||
#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */
|
||||
/* ========== Pio definition for USART3 peripheral ========== */
|
||||
#define PIO_PC10B_CTS3 (1u << 10) /**< \brief Usart3 signal: CTS3 */
|
||||
#define PIO_PC11B_RTS3 (1u << 11) /**< \brief Usart3 signal: RTS3 */
|
||||
#define PIO_PC13B_RXD3 (1u << 13) /**< \brief Usart3 signal: RXD3 */
|
||||
#define PIO_PC19A_SCK3 (1u << 19) /**< \brief Usart3 signal: SCK3 */
|
||||
#define PIO_PC12B_TXD3 (1u << 12) /**< \brief Usart3 signal: TXD3 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PB15_IDX 47
|
||||
#define PIO_PB16_IDX 48
|
||||
#define PIO_PB17_IDX 49
|
||||
#define PIO_PB18_IDX 50
|
||||
#define PIO_PB19_IDX 51
|
||||
#define PIO_PB20_IDX 52
|
||||
#define PIO_PB21_IDX 53
|
||||
#define PIO_PB22_IDX 54
|
||||
#define PIO_PB23_IDX 55
|
||||
#define PIO_PB24_IDX 56
|
||||
#define PIO_PB25_IDX 57
|
||||
#define PIO_PB26_IDX 58
|
||||
#define PIO_PB27_IDX 59
|
||||
#define PIO_PB28_IDX 60
|
||||
#define PIO_PB29_IDX 61
|
||||
#define PIO_PB30_IDX 62
|
||||
#define PIO_PB31_IDX 63
|
||||
#define PIO_PC0_IDX 64
|
||||
#define PIO_PC1_IDX 65
|
||||
#define PIO_PC2_IDX 66
|
||||
#define PIO_PC3_IDX 67
|
||||
#define PIO_PC4_IDX 68
|
||||
#define PIO_PC5_IDX 69
|
||||
#define PIO_PC6_IDX 70
|
||||
#define PIO_PC7_IDX 71
|
||||
#define PIO_PC8_IDX 72
|
||||
#define PIO_PC9_IDX 73
|
||||
#define PIO_PC10_IDX 74
|
||||
#define PIO_PC11_IDX 75
|
||||
#define PIO_PC12_IDX 76
|
||||
#define PIO_PC13_IDX 77
|
||||
#define PIO_PC14_IDX 78
|
||||
#define PIO_PC15_IDX 79
|
||||
#define PIO_PC16_IDX 80
|
||||
#define PIO_PC17_IDX 81
|
||||
#define PIO_PC18_IDX 82
|
||||
#define PIO_PC19_IDX 83
|
||||
#define PIO_PC20_IDX 84
|
||||
#define PIO_PC21_IDX 85
|
||||
#define PIO_PC22_IDX 86
|
||||
#define PIO_PC23_IDX 87
|
||||
#define PIO_PC24_IDX 88
|
||||
#define PIO_PC25_IDX 89
|
||||
#define PIO_PC26_IDX 90
|
||||
#define PIO_PC27_IDX 91
|
||||
#define PIO_PC28_IDX 92
|
||||
#define PIO_PC29_IDX 93
|
||||
#define PIO_PC30_IDX 94
|
||||
#define PIO_PC31_IDX 95
|
||||
|
||||
#endif /* _SAM3U2E_PIO_ */
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U4C_PIO_
|
||||
#define _SAM3U4C_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
|
||||
#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
|
||||
#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
|
||||
#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
|
||||
#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
|
||||
#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
|
||||
#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
|
||||
#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
|
||||
#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
|
||||
#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */
|
||||
#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */
|
||||
#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */
|
||||
#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for ADC12B peripheral ========== */
|
||||
#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
|
||||
#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
|
||||
#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */
|
||||
#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */
|
||||
#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
|
||||
#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
|
||||
#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
|
||||
#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
|
||||
#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */
|
||||
/* ========== Pio definition for EBI peripheral ========== */
|
||||
#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */
|
||||
#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */
|
||||
#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */
|
||||
#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */
|
||||
#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */
|
||||
#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */
|
||||
#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */
|
||||
#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */
|
||||
#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */
|
||||
#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */
|
||||
#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */
|
||||
#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */
|
||||
#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */
|
||||
#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */
|
||||
#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */
|
||||
#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */
|
||||
#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */
|
||||
#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */
|
||||
#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */
|
||||
#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */
|
||||
#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */
|
||||
#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */
|
||||
#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */
|
||||
#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */
|
||||
#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */
|
||||
#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */
|
||||
#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */
|
||||
#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */
|
||||
#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */
|
||||
#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */
|
||||
#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */
|
||||
#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */
|
||||
#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
|
||||
#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */
|
||||
#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */
|
||||
#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */
|
||||
#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */
|
||||
#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */
|
||||
#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */
|
||||
#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
/* ========== Pio definition for HSMCI peripheral ========== */
|
||||
#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */
|
||||
#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */
|
||||
#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */
|
||||
#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */
|
||||
#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */
|
||||
#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */
|
||||
#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */
|
||||
#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */
|
||||
#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */
|
||||
#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */
|
||||
#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */
|
||||
#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */
|
||||
#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for SSC peripheral ========== */
|
||||
#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */
|
||||
#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */
|
||||
#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */
|
||||
#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */
|
||||
#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */
|
||||
#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART peripheral ========== */
|
||||
#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */
|
||||
#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */
|
||||
#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */
|
||||
#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */
|
||||
#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */
|
||||
#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio definition for USART2 peripheral ========== */
|
||||
#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */
|
||||
#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */
|
||||
#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */
|
||||
#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */
|
||||
#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PB15_IDX 47
|
||||
#define PIO_PB16_IDX 48
|
||||
#define PIO_PB17_IDX 49
|
||||
#define PIO_PB18_IDX 50
|
||||
#define PIO_PB19_IDX 51
|
||||
#define PIO_PB20_IDX 52
|
||||
#define PIO_PB21_IDX 53
|
||||
#define PIO_PB22_IDX 54
|
||||
#define PIO_PB23_IDX 55
|
||||
#define PIO_PB24_IDX 56
|
||||
|
||||
#endif /* _SAM3U4C_PIO_ */
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U4E_PIO_
|
||||
#define _SAM3U4E_PIO_
|
||||
|
||||
#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */
|
||||
#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */
|
||||
#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */
|
||||
#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */
|
||||
#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */
|
||||
#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */
|
||||
#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */
|
||||
#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */
|
||||
#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */
|
||||
#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */
|
||||
#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */
|
||||
#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */
|
||||
#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */
|
||||
#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */
|
||||
#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */
|
||||
#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */
|
||||
#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */
|
||||
#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */
|
||||
#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */
|
||||
#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */
|
||||
#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */
|
||||
#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */
|
||||
#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */
|
||||
#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */
|
||||
#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */
|
||||
#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */
|
||||
#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */
|
||||
#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */
|
||||
#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */
|
||||
#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */
|
||||
#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */
|
||||
#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */
|
||||
#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */
|
||||
#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */
|
||||
#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */
|
||||
#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */
|
||||
#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */
|
||||
#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */
|
||||
#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */
|
||||
#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */
|
||||
#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */
|
||||
#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */
|
||||
#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */
|
||||
#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */
|
||||
#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */
|
||||
#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */
|
||||
#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */
|
||||
#define PIO_PB15 (1u << 15) /**< \brief Pin Controlled by PB15 */
|
||||
#define PIO_PB16 (1u << 16) /**< \brief Pin Controlled by PB16 */
|
||||
#define PIO_PB17 (1u << 17) /**< \brief Pin Controlled by PB17 */
|
||||
#define PIO_PB18 (1u << 18) /**< \brief Pin Controlled by PB18 */
|
||||
#define PIO_PB19 (1u << 19) /**< \brief Pin Controlled by PB19 */
|
||||
#define PIO_PB20 (1u << 20) /**< \brief Pin Controlled by PB20 */
|
||||
#define PIO_PB21 (1u << 21) /**< \brief Pin Controlled by PB21 */
|
||||
#define PIO_PB22 (1u << 22) /**< \brief Pin Controlled by PB22 */
|
||||
#define PIO_PB23 (1u << 23) /**< \brief Pin Controlled by PB23 */
|
||||
#define PIO_PB24 (1u << 24) /**< \brief Pin Controlled by PB24 */
|
||||
#define PIO_PB25 (1u << 25) /**< \brief Pin Controlled by PB25 */
|
||||
#define PIO_PB26 (1u << 26) /**< \brief Pin Controlled by PB26 */
|
||||
#define PIO_PB27 (1u << 27) /**< \brief Pin Controlled by PB27 */
|
||||
#define PIO_PB28 (1u << 28) /**< \brief Pin Controlled by PB28 */
|
||||
#define PIO_PB29 (1u << 29) /**< \brief Pin Controlled by PB29 */
|
||||
#define PIO_PB30 (1u << 30) /**< \brief Pin Controlled by PB30 */
|
||||
#define PIO_PB31 (1u << 31) /**< \brief Pin Controlled by PB31 */
|
||||
#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */
|
||||
#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */
|
||||
#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */
|
||||
#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */
|
||||
#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */
|
||||
#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */
|
||||
#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */
|
||||
#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */
|
||||
#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */
|
||||
#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */
|
||||
#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */
|
||||
#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */
|
||||
#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */
|
||||
#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */
|
||||
#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */
|
||||
#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */
|
||||
#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */
|
||||
#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */
|
||||
#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */
|
||||
#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */
|
||||
#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */
|
||||
#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */
|
||||
#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */
|
||||
#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */
|
||||
#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */
|
||||
#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */
|
||||
#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */
|
||||
#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */
|
||||
#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */
|
||||
#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */
|
||||
#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */
|
||||
#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */
|
||||
/* ========== Pio definition for ADC peripheral ========== */
|
||||
#define PIO_PB5X1_AD0 (1u << 5) /**< \brief Adc signal: AD0 */
|
||||
#define PIO_PB6X1_AD1 (1u << 6) /**< \brief Adc signal: AD1 */
|
||||
#define PIO_PB7X1_AD2 (1u << 7) /**< \brief Adc signal: AD2 */
|
||||
#define PIO_PB8X1_AD3 (1u << 8) /**< \brief Adc signal: AD3 */
|
||||
#define PIO_PC28X1_AD4 (1u << 28) /**< \brief Adc signal: AD4 */
|
||||
#define PIO_PC29X1_AD5 (1u << 29) /**< \brief Adc signal: AD5 */
|
||||
#define PIO_PC30X1_AD6 (1u << 30) /**< \brief Adc signal: AD6 */
|
||||
#define PIO_PC31X1_AD7 (1u << 31) /**< \brief Adc signal: AD7 */
|
||||
#define PIO_PA17B_ADTRG (1u << 17) /**< \brief Adc signal: ADTRG */
|
||||
/* ========== Pio definition for ADC12B peripheral ========== */
|
||||
#define PIO_PA22X1_AD12B0 (1u << 22) /**< \brief Adc12b signal: AD12B0 */
|
||||
#define PIO_PA30X1_AD12B1 (1u << 30) /**< \brief Adc12b signal: AD12B1 */
|
||||
#define PIO_PB3X1_AD12B2 (1u << 3) /**< \brief Adc12b signal: AD12B2 */
|
||||
#define PIO_PB4X1_AD12B3 (1u << 4) /**< \brief Adc12b signal: AD12B3 */
|
||||
#define PIO_PC15X1_AD12B4 (1u << 15) /**< \brief Adc12b signal: AD12B4 */
|
||||
#define PIO_PC16X1_AD12B5 (1u << 16) /**< \brief Adc12b signal: AD12B5 */
|
||||
#define PIO_PC17X1_AD12B6 (1u << 17) /**< \brief Adc12b signal: AD12B6 */
|
||||
#define PIO_PC18X1_AD12B7 (1u << 18) /**< \brief Adc12b signal: AD12B7 */
|
||||
#define PIO_PA2B_AD12BTRG (1u << 2) /**< \brief Adc12b signal: AD12BTRG */
|
||||
/* ========== Pio definition for EBI peripheral ========== */
|
||||
#define PIO_PB7B_A0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB7B_NBS0 (1u << 7) /**< \brief Ebi signal: A0/NBS0 */
|
||||
#define PIO_PB8B_A1 (1u << 8) /**< \brief Ebi signal: A1 */
|
||||
#define PIO_PC8A_A10 (1u << 8) /**< \brief Ebi signal: A10 */
|
||||
#define PIO_PC9A_A11 (1u << 9) /**< \brief Ebi signal: A11 */
|
||||
#define PIO_PC10A_A12 (1u << 10) /**< \brief Ebi signal: A12 */
|
||||
#define PIO_PC11A_A13 (1u << 11) /**< \brief Ebi signal: A13 */
|
||||
#define PIO_PC20A_A14 (1u << 20) /**< \brief Ebi signal: A14 */
|
||||
#define PIO_PC21A_A15 (1u << 21) /**< \brief Ebi signal: A15 */
|
||||
#define PIO_PC22A_A16 (1u << 22) /**< \brief Ebi signal: A16 */
|
||||
#define PIO_PC23A_A17 (1u << 23) /**< \brief Ebi signal: A17 */
|
||||
#define PIO_PC24A_A18 (1u << 24) /**< \brief Ebi signal: A18 */
|
||||
#define PIO_PC25A_A19 (1u << 25) /**< \brief Ebi signal: A19 */
|
||||
#define PIO_PB0B_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC0A_A2 (1u << 0) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC13A_A2 (1u << 13) /**< \brief Ebi signal: A2 */
|
||||
#define PIO_PC26A_A20 (1u << 26) /**< \brief Ebi signal: A20 */
|
||||
#define PIO_PB21A_A21 (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB21A_NANDALE (1u << 21) /**< \brief Ebi signal: A21/NANDALE */
|
||||
#define PIO_PB22A_A22 (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PB22A_NANDCLE (1u << 22) /**< \brief Ebi signal: A22/NANDCLE */
|
||||
#define PIO_PC27A_A23 (1u << 27) /**< \brief Ebi signal: A23 */
|
||||
#define PIO_PB1B_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC1A_A3 (1u << 1) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PC14A_A3 (1u << 14) /**< \brief Ebi signal: A3 */
|
||||
#define PIO_PB2B_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PC2A_A4 (1u << 2) /**< \brief Ebi signal: A4 */
|
||||
#define PIO_PB3B_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PC3A_A5 (1u << 3) /**< \brief Ebi signal: A5 */
|
||||
#define PIO_PB4B_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PC4A_A6 (1u << 4) /**< \brief Ebi signal: A6 */
|
||||
#define PIO_PB5B_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC5A_A7 (1u << 5) /**< \brief Ebi signal: A7 */
|
||||
#define PIO_PC6A_A8 (1u << 6) /**< \brief Ebi signal: A8 */
|
||||
#define PIO_PC7A_A9 (1u << 7) /**< \brief Ebi signal: A9 */
|
||||
#define PIO_PB9A_D0 (1u << 9) /**< \brief Ebi signal: D0 */
|
||||
#define PIO_PB10A_D1 (1u << 10) /**< \brief Ebi signal: D1 */
|
||||
#define PIO_PB27A_D10 (1u << 27) /**< \brief Ebi signal: D10 */
|
||||
#define PIO_PB28A_D11 (1u << 28) /**< \brief Ebi signal: D11 */
|
||||
#define PIO_PB29A_D12 (1u << 29) /**< \brief Ebi signal: D12 */
|
||||
#define PIO_PB30A_D13 (1u << 30) /**< \brief Ebi signal: D13 */
|
||||
#define PIO_PB31A_D14 (1u << 31) /**< \brief Ebi signal: D14 */
|
||||
#define PIO_PB6B_D15 (1u << 6) /**< \brief Ebi signal: D15 */
|
||||
#define PIO_PB11A_D2 (1u << 11) /**< \brief Ebi signal: D2 */
|
||||
#define PIO_PB12A_D3 (1u << 12) /**< \brief Ebi signal: D3 */
|
||||
#define PIO_PB13A_D4 (1u << 13) /**< \brief Ebi signal: D4 */
|
||||
#define PIO_PB14A_D5 (1u << 14) /**< \brief Ebi signal: D5 */
|
||||
#define PIO_PB15A_D6 (1u << 15) /**< \brief Ebi signal: D6 */
|
||||
#define PIO_PB16A_D7 (1u << 16) /**< \brief Ebi signal: D7 */
|
||||
#define PIO_PB25A_D8 (1u << 25) /**< \brief Ebi signal: D8 */
|
||||
#define PIO_PB26A_D9 (1u << 26) /**< \brief Ebi signal: D9 */
|
||||
#define PIO_PB17A_NANDOE (1u << 17) /**< \brief Ebi signal: NANDOE */
|
||||
#define PIO_PB24A_NANDRDY (1u << 24) /**< \brief Ebi signal: NANDRDY */
|
||||
#define PIO_PB18A_NANDWE (1u << 18) /**< \brief Ebi signal: NANDWE */
|
||||
#define PIO_PB20A_NCS0 (1u << 20) /**< \brief Ebi signal: NCS0 */
|
||||
#define PIO_PA16B_NCS1 (1u << 16) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC12A_NCS1 (1u << 12) /**< \brief Ebi signal: NCS1 */
|
||||
#define PIO_PC16A_NCS2 (1u << 16) /**< \brief Ebi signal: NCS2 */
|
||||
#define PIO_PC17A_NCS3 (1u << 17) /**< \brief Ebi signal: NCS3 */
|
||||
#define PIO_PB19A_NRD (1u << 19) /**< \brief Ebi signal: NRD */
|
||||
#define PIO_PC18A_NWAIT (1u << 18) /**< \brief Ebi signal: NWAIT */
|
||||
#define PIO_PB23A_NWR0 (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PB23A_NWE (1u << 23) /**< \brief Ebi signal: NWR0/NWE */
|
||||
#define PIO_PC15A_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
#define PIO_PC15A_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */
|
||||
/* ========== Pio definition for HSMCI peripheral ========== */
|
||||
#define PIO_PA4A_MCCDA (1u << 4) /**< \brief Hsmci signal: MCCDA */
|
||||
#define PIO_PA3A_MCCK (1u << 3) /**< \brief Hsmci signal: MCCK */
|
||||
#define PIO_PA5A_MCDA0 (1u << 5) /**< \brief Hsmci signal: MCDA0 */
|
||||
#define PIO_PA6A_MCDA1 (1u << 6) /**< \brief Hsmci signal: MCDA1 */
|
||||
#define PIO_PA7A_MCDA2 (1u << 7) /**< \brief Hsmci signal: MCDA2 */
|
||||
#define PIO_PA8A_MCDA3 (1u << 8) /**< \brief Hsmci signal: MCDA3 */
|
||||
#define PIO_PC28B_MCDA4 (1u << 28) /**< \brief Hsmci signal: MCDA4 */
|
||||
#define PIO_PC29B_MCDA5 (1u << 29) /**< \brief Hsmci signal: MCDA5 */
|
||||
#define PIO_PC30B_MCDA6 (1u << 30) /**< \brief Hsmci signal: MCDA6 */
|
||||
#define PIO_PC31B_MCDA7 (1u << 31) /**< \brief Hsmci signal: MCDA7 */
|
||||
/* ========== Pio definition for PMC peripheral ========== */
|
||||
#define PIO_PA21B_PCK0 (1u << 21) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA27B_PCK0 (1u << 27) /**< \brief Pmc signal: PCK0 */
|
||||
#define PIO_PA3B_PCK1 (1u << 3) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB24B_PCK1 (1u << 24) /**< \brief Pmc signal: PCK1 */
|
||||
#define PIO_PB23B_PCK2 (1u << 23) /**< \brief Pmc signal: PCK2 */
|
||||
/* ========== Pio definition for PWM peripheral ========== */
|
||||
#define PIO_PA11B_PWMFI0 (1u << 11) /**< \brief Pwm signal: PWMFI0 */
|
||||
#define PIO_PA12B_PWMFI1 (1u << 12) /**< \brief Pwm signal: PWMFI1 */
|
||||
#define PIO_PA18B_PWMFI2 (1u << 18) /**< \brief Pwm signal: PWMFI2 */
|
||||
#define PIO_PA4B_PWMH0 (1u << 4) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA28B_PWMH0 (1u << 28) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PB13B_PWMH0 (1u << 13) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PC24B_PWMH0 (1u << 24) /**< \brief Pwm signal: PWMH0 */
|
||||
#define PIO_PA5B_PWMH1 (1u << 5) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA29B_PWMH1 (1u << 29) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PB14B_PWMH1 (1u << 14) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PC25B_PWMH1 (1u << 25) /**< \brief Pwm signal: PWMH1 */
|
||||
#define PIO_PA6B_PWMH2 (1u << 6) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PB15B_PWMH2 (1u << 15) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PC26B_PWMH2 (1u << 26) /**< \brief Pwm signal: PWMH2 */
|
||||
#define PIO_PA20B_PWMH3 (1u << 20) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB3A_PWMH3 (1u << 3) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PB16B_PWMH3 (1u << 16) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PC27B_PWMH3 (1u << 27) /**< \brief Pwm signal: PWMH3 */
|
||||
#define PIO_PA7B_PWML0 (1u << 7) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB17B_PWML0 (1u << 17) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PB25B_PWML0 (1u << 25) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC6B_PWML0 (1u << 6) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PC29A_PWML0 (1u << 29) /**< \brief Pwm signal: PWML0 */
|
||||
#define PIO_PA8B_PWML1 (1u << 8) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB18B_PWML1 (1u << 18) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PB26B_PWML1 (1u << 26) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC7B_PWML1 (1u << 7) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PC30A_PWML1 (1u << 30) /**< \brief Pwm signal: PWML1 */
|
||||
#define PIO_PA9B_PWML2 (1u << 9) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB19B_PWML2 (1u << 19) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PB27B_PWML2 (1u << 27) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC8B_PWML2 (1u << 8) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PC31A_PWML2 (1u << 31) /**< \brief Pwm signal: PWML2 */
|
||||
#define PIO_PA10B_PWML3 (1u << 10) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB20B_PWML3 (1u << 20) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PB28B_PWML3 (1u << 28) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC9B_PWML3 (1u << 9) /**< \brief Pwm signal: PWML3 */
|
||||
#define PIO_PC16B_PWML3 (1u << 16) /**< \brief Pwm signal: PWML3 */
|
||||
/* ========== Pio definition for SPI peripheral ========== */
|
||||
#define PIO_PA13A_MISO (1u << 13) /**< \brief Spi signal: MISO */
|
||||
#define PIO_PA14A_MOSI (1u << 14) /**< \brief Spi signal: MOSI */
|
||||
#define PIO_PA16A_NPCS0 (1u << 16) /**< \brief Spi signal: NPCS0 */
|
||||
#define PIO_PA0B_NPCS1 (1u << 0) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC3B_NPCS1 (1u << 3) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PC19B_NPCS1 (1u << 19) /**< \brief Spi signal: NPCS1 */
|
||||
#define PIO_PA1B_NPCS2 (1u << 1) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC4B_NPCS2 (1u << 4) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PC14B_NPCS2 (1u << 14) /**< \brief Spi signal: NPCS2 */
|
||||
#define PIO_PA19B_NPCS3 (1u << 19) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PC5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */
|
||||
#define PIO_PA15A_SPCK (1u << 15) /**< \brief Spi signal: SPCK */
|
||||
/* ========== Pio definition for SSC peripheral ========== */
|
||||
#define PIO_PA27A_RD (1u << 27) /**< \brief Ssc signal: RD */
|
||||
#define PIO_PA31A_RF (1u << 31) /**< \brief Ssc signal: RF */
|
||||
#define PIO_PA29A_RK (1u << 29) /**< \brief Ssc signal: RK */
|
||||
#define PIO_PA26A_TD (1u << 26) /**< \brief Ssc signal: TD */
|
||||
#define PIO_PA30A_TF (1u << 30) /**< \brief Ssc signal: TF */
|
||||
#define PIO_PA28A_TK (1u << 28) /**< \brief Ssc signal: TK */
|
||||
/* ========== Pio definition for TC0 peripheral ========== */
|
||||
#define PIO_PA2A_TCLK0 (1u << 2) /**< \brief Tc0 signal: TCLK0 */
|
||||
#define PIO_PB4A_TCLK1 (1u << 4) /**< \brief Tc0 signal: TCLK1 */
|
||||
#define PIO_PA26B_TCLK2 (1u << 26) /**< \brief Tc0 signal: TCLK2 */
|
||||
#define PIO_PA1A_TIOA0 (1u << 1) /**< \brief Tc0 signal: TIOA0 */
|
||||
#define PIO_PB5A_TIOA1 (1u << 5) /**< \brief Tc0 signal: TIOA1 */
|
||||
#define PIO_PA30B_TIOA2 (1u << 30) /**< \brief Tc0 signal: TIOA2 */
|
||||
#define PIO_PA0A_TIOB0 (1u << 0) /**< \brief Tc0 signal: TIOB0 */
|
||||
#define PIO_PB6A_TIOB1 (1u << 6) /**< \brief Tc0 signal: TIOB1 */
|
||||
#define PIO_PA31B_TIOB2 (1u << 31) /**< \brief Tc0 signal: TIOB2 */
|
||||
/* ========== Pio definition for TWI0 peripheral ========== */
|
||||
#define PIO_PA10A_TWCK0 (1u << 10) /**< \brief Twi0 signal: TWCK0 */
|
||||
#define PIO_PA9A_TWD0 (1u << 9) /**< \brief Twi0 signal: TWD0 */
|
||||
/* ========== Pio definition for TWI1 peripheral ========== */
|
||||
#define PIO_PA25A_TWCK1 (1u << 25) /**< \brief Twi1 signal: TWCK1 */
|
||||
#define PIO_PA24A_TWD1 (1u << 24) /**< \brief Twi1 signal: TWD1 */
|
||||
/* ========== Pio definition for UART peripheral ========== */
|
||||
#define PIO_PA11A_URXD (1u << 11) /**< \brief Uart signal: URXD */
|
||||
#define PIO_PA12A_UTXD (1u << 12) /**< \brief Uart signal: UTXD */
|
||||
/* ========== Pio definition for USART0 peripheral ========== */
|
||||
#define PIO_PB8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */
|
||||
#define PIO_PB11B_DCD0 (1u << 11) /**< \brief Usart0 signal: DCD0 */
|
||||
#define PIO_PB10B_DSR0 (1u << 10) /**< \brief Usart0 signal: DSR0 */
|
||||
#define PIO_PB9B_DTR0 (1u << 9) /**< \brief Usart0 signal: DTR0 */
|
||||
#define PIO_PB12B_RI0 (1u << 12) /**< \brief Usart0 signal: RI0 */
|
||||
#define PIO_PB7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */
|
||||
#define PIO_PA19A_RXD0 (1u << 19) /**< \brief Usart0 signal: RXD0 */
|
||||
#define PIO_PA17A_SCK0 (1u << 17) /**< \brief Usart0 signal: SCK0 */
|
||||
#define PIO_PA18A_TXD0 (1u << 18) /**< \brief Usart0 signal: TXD0 */
|
||||
/* ========== Pio definition for USART1 peripheral ========== */
|
||||
#define PIO_PA23B_CTS1 (1u << 23) /**< \brief Usart1 signal: CTS1 */
|
||||
#define PIO_PA22B_RTS1 (1u << 22) /**< \brief Usart1 signal: RTS1 */
|
||||
#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */
|
||||
#define PIO_PA24B_SCK1 (1u << 24) /**< \brief Usart1 signal: SCK1 */
|
||||
#define PIO_PA20A_TXD1 (1u << 20) /**< \brief Usart1 signal: TXD1 */
|
||||
/* ========== Pio definition for USART2 peripheral ========== */
|
||||
#define PIO_PB22B_CTS2 (1u << 22) /**< \brief Usart2 signal: CTS2 */
|
||||
#define PIO_PB21B_RTS2 (1u << 21) /**< \brief Usart2 signal: RTS2 */
|
||||
#define PIO_PA23A_RXD2 (1u << 23) /**< \brief Usart2 signal: RXD2 */
|
||||
#define PIO_PA25B_SCK2 (1u << 25) /**< \brief Usart2 signal: SCK2 */
|
||||
#define PIO_PA22A_TXD2 (1u << 22) /**< \brief Usart2 signal: TXD2 */
|
||||
/* ========== Pio definition for USART3 peripheral ========== */
|
||||
#define PIO_PC10B_CTS3 (1u << 10) /**< \brief Usart3 signal: CTS3 */
|
||||
#define PIO_PC11B_RTS3 (1u << 11) /**< \brief Usart3 signal: RTS3 */
|
||||
#define PIO_PC13B_RXD3 (1u << 13) /**< \brief Usart3 signal: RXD3 */
|
||||
#define PIO_PC19A_SCK3 (1u << 19) /**< \brief Usart3 signal: SCK3 */
|
||||
#define PIO_PC12B_TXD3 (1u << 12) /**< \brief Usart3 signal: TXD3 */
|
||||
/* ========== Pio indexes ========== */
|
||||
#define PIO_PA0_IDX 0
|
||||
#define PIO_PA1_IDX 1
|
||||
#define PIO_PA2_IDX 2
|
||||
#define PIO_PA3_IDX 3
|
||||
#define PIO_PA4_IDX 4
|
||||
#define PIO_PA5_IDX 5
|
||||
#define PIO_PA6_IDX 6
|
||||
#define PIO_PA7_IDX 7
|
||||
#define PIO_PA8_IDX 8
|
||||
#define PIO_PA9_IDX 9
|
||||
#define PIO_PA10_IDX 10
|
||||
#define PIO_PA11_IDX 11
|
||||
#define PIO_PA12_IDX 12
|
||||
#define PIO_PA13_IDX 13
|
||||
#define PIO_PA14_IDX 14
|
||||
#define PIO_PA15_IDX 15
|
||||
#define PIO_PA16_IDX 16
|
||||
#define PIO_PA17_IDX 17
|
||||
#define PIO_PA18_IDX 18
|
||||
#define PIO_PA19_IDX 19
|
||||
#define PIO_PA20_IDX 20
|
||||
#define PIO_PA21_IDX 21
|
||||
#define PIO_PA22_IDX 22
|
||||
#define PIO_PA23_IDX 23
|
||||
#define PIO_PA24_IDX 24
|
||||
#define PIO_PA25_IDX 25
|
||||
#define PIO_PA26_IDX 26
|
||||
#define PIO_PA27_IDX 27
|
||||
#define PIO_PA28_IDX 28
|
||||
#define PIO_PA29_IDX 29
|
||||
#define PIO_PA30_IDX 30
|
||||
#define PIO_PA31_IDX 31
|
||||
#define PIO_PB0_IDX 32
|
||||
#define PIO_PB1_IDX 33
|
||||
#define PIO_PB2_IDX 34
|
||||
#define PIO_PB3_IDX 35
|
||||
#define PIO_PB4_IDX 36
|
||||
#define PIO_PB5_IDX 37
|
||||
#define PIO_PB6_IDX 38
|
||||
#define PIO_PB7_IDX 39
|
||||
#define PIO_PB8_IDX 40
|
||||
#define PIO_PB9_IDX 41
|
||||
#define PIO_PB10_IDX 42
|
||||
#define PIO_PB11_IDX 43
|
||||
#define PIO_PB12_IDX 44
|
||||
#define PIO_PB13_IDX 45
|
||||
#define PIO_PB14_IDX 46
|
||||
#define PIO_PB15_IDX 47
|
||||
#define PIO_PB16_IDX 48
|
||||
#define PIO_PB17_IDX 49
|
||||
#define PIO_PB18_IDX 50
|
||||
#define PIO_PB19_IDX 51
|
||||
#define PIO_PB20_IDX 52
|
||||
#define PIO_PB21_IDX 53
|
||||
#define PIO_PB22_IDX 54
|
||||
#define PIO_PB23_IDX 55
|
||||
#define PIO_PB24_IDX 56
|
||||
#define PIO_PB25_IDX 57
|
||||
#define PIO_PB26_IDX 58
|
||||
#define PIO_PB27_IDX 59
|
||||
#define PIO_PB28_IDX 60
|
||||
#define PIO_PB29_IDX 61
|
||||
#define PIO_PB30_IDX 62
|
||||
#define PIO_PB31_IDX 63
|
||||
#define PIO_PC0_IDX 64
|
||||
#define PIO_PC1_IDX 65
|
||||
#define PIO_PC2_IDX 66
|
||||
#define PIO_PC3_IDX 67
|
||||
#define PIO_PC4_IDX 68
|
||||
#define PIO_PC5_IDX 69
|
||||
#define PIO_PC6_IDX 70
|
||||
#define PIO_PC7_IDX 71
|
||||
#define PIO_PC8_IDX 72
|
||||
#define PIO_PC9_IDX 73
|
||||
#define PIO_PC10_IDX 74
|
||||
#define PIO_PC11_IDX 75
|
||||
#define PIO_PC12_IDX 76
|
||||
#define PIO_PC13_IDX 77
|
||||
#define PIO_PC14_IDX 78
|
||||
#define PIO_PC15_IDX 79
|
||||
#define PIO_PC16_IDX 80
|
||||
#define PIO_PC17_IDX 81
|
||||
#define PIO_PC18_IDX 82
|
||||
#define PIO_PC19_IDX 83
|
||||
#define PIO_PC20_IDX 84
|
||||
#define PIO_PC21_IDX 85
|
||||
#define PIO_PC22_IDX 86
|
||||
#define PIO_PC23_IDX 87
|
||||
#define PIO_PC24_IDX 88
|
||||
#define PIO_PC25_IDX 89
|
||||
#define PIO_PC26_IDX 90
|
||||
#define PIO_PC27_IDX 91
|
||||
#define PIO_PC28_IDX 92
|
||||
#define PIO_PC29_IDX 93
|
||||
#define PIO_PC30_IDX 94
|
||||
#define PIO_PC31_IDX 95
|
||||
|
||||
#endif /* _SAM3U4E_PIO_ */
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U_
|
||||
#define _SAM3U_
|
||||
|
||||
#if defined sam3u1c
|
||||
#include "SAM3U1C.h"
|
||||
#elif defined sam3u1e
|
||||
#include "SAM3U1E.h"
|
||||
#elif defined sam3u2c
|
||||
#include "SAM3U2C.h"
|
||||
#elif defined sam3u2e
|
||||
#include "SAM3U2E.h"
|
||||
#elif defined sam3u4c
|
||||
#include "SAM3U4C.h"
|
||||
#elif defined sam3u4e
|
||||
#include "SAM3U4E.h"
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _SAM3U_ */
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U1C_
|
||||
#define _SAM3U1C_
|
||||
|
||||
/** \addtogroup SAM3U1C_definitions SAM3U1C definitions
|
||||
This file defines all structures and symbols for SAM3U1C:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1C_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3U1C specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3U1C Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3U1C Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3U1C Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3U1C Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3U1C Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3U1C Power Management Controller (PMC) */
|
||||
EFC0_IRQn = 6, /**< 6 SAM3U1C Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
EFC1_IRQn = 7, /**< 7 SAM3U1C Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
UART_IRQn = 8, /**< 8 SAM3U1C Universal Asynchronous Receiver Transmitter (UART) */
|
||||
SMC_IRQn = 9, /**< 9 SAM3U1C Static Memory Controller (SMC) */
|
||||
PIOA_IRQn = 10, /**< 10 SAM3U1C Parallel I/O Controller A, (PIOA) */
|
||||
PIOB_IRQn = 11, /**< 11 SAM3U1C Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 12, /**< 12 SAM3U1C Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 13, /**< 13 SAM3U1C USART 0 (USART0) */
|
||||
USART1_IRQn = 14, /**< 14 SAM3U1C USART 1 (USART1) */
|
||||
USART2_IRQn = 15, /**< 15 SAM3U1C USART 2 (USART2) */
|
||||
USART3_IRQn = 16, /**< 16 SAM3U1C USART 3 (USART3) */
|
||||
HSMCI_IRQn = 17, /**< 17 SAM3U1C High Speed Multimedia Card Interface (HSMCI) */
|
||||
TWI0_IRQn = 18, /**< 18 SAM3U1C Two-Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 19, /**< 19 SAM3U1C Two-Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 20, /**< 20 SAM3U1C Serial Peripheral Interface (SPI) */
|
||||
SSC_IRQn = 21, /**< 21 SAM3U1C Synchronous Serial Controller (SSC) */
|
||||
TC0_IRQn = 22, /**< 22 SAM3U1C Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 23, /**< 23 SAM3U1C Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 24, /**< 24 SAM3U1C Timer Counter 2 (TC2) */
|
||||
PWM_IRQn = 25, /**< 25 SAM3U1C Pulse Width Modulation Controller (PWM) */
|
||||
ADC12B_IRQn = 26, /**< 26 SAM3U1C 12-bit ADC Controller (ADC12B) */
|
||||
ADC_IRQn = 27, /**< 27 SAM3U1C 10-bit ADC Controller (ADC) */
|
||||
DMAC_IRQn = 28, /**< 28 SAM3U1C DMA Controller (DMAC) */
|
||||
UDPHS_IRQn = 29 /**< 29 SAM3U1C USB Device High Speed (UDPHS) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< SAM3U1C does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3U1C uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1C_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/ADC12B.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DMAC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/HSMCI.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SMC.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SSC.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/UDPHS.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1C_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/HSMCI.h"
|
||||
#include "instance/SSC.h"
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/USART2.h"
|
||||
#include "instance/UDPHS.h"
|
||||
#include "instance/ADC12B.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DMAC.h"
|
||||
#include "instance/SMC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/EFC0.h"
|
||||
#include "instance/EFC1.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1C_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
|
||||
#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
|
||||
#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
|
||||
#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
|
||||
#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
|
||||
#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
|
||||
#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
|
||||
#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
|
||||
#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
|
||||
#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
|
||||
#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
|
||||
#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
|
||||
#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
|
||||
#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
|
||||
#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1C_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
|
||||
#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
|
||||
#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
|
||||
#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
|
||||
#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
|
||||
#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
|
||||
#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
|
||||
#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
|
||||
#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
|
||||
#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
|
||||
#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
|
||||
#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
|
||||
#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1C_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3U1C.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3U1C */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x10000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH_NB_OF_PAGES 32
|
||||
#define IRAM_SIZE 0x5000
|
||||
|
||||
#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
|
||||
#if defined IFLASH0_SIZE
|
||||
#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
|
||||
#endif
|
||||
#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
|
||||
#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
|
||||
#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
|
||||
#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
|
||||
#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3U1C_ */
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U1E_
|
||||
#define _SAM3U1E_
|
||||
|
||||
/** \addtogroup SAM3U1E_definitions SAM3U1E definitions
|
||||
This file defines all structures and symbols for SAM3U1E:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1E_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3U1E specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3U1E Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3U1E Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3U1E Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3U1E Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3U1E Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3U1E Power Management Controller (PMC) */
|
||||
EFC0_IRQn = 6, /**< 6 SAM3U1E Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
EFC1_IRQn = 7, /**< 7 SAM3U1E Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
UART_IRQn = 8, /**< 8 SAM3U1E Universal Asynchronous Receiver Transmitter (UART) */
|
||||
SMC_IRQn = 9, /**< 9 SAM3U1E Static Memory Controller (SMC) */
|
||||
PIOA_IRQn = 10, /**< 10 SAM3U1E Parallel I/O Controller A, (PIOA) */
|
||||
PIOB_IRQn = 11, /**< 11 SAM3U1E Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 12, /**< 12 SAM3U1E Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 13, /**< 13 SAM3U1E USART 0 (USART0) */
|
||||
USART1_IRQn = 14, /**< 14 SAM3U1E USART 1 (USART1) */
|
||||
USART2_IRQn = 15, /**< 15 SAM3U1E USART 2 (USART2) */
|
||||
USART3_IRQn = 16, /**< 16 SAM3U1E USART 3 (USART3) */
|
||||
HSMCI_IRQn = 17, /**< 17 SAM3U1E High Speed Multimedia Card Interface (HSMCI) */
|
||||
TWI0_IRQn = 18, /**< 18 SAM3U1E Two-Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 19, /**< 19 SAM3U1E Two-Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 20, /**< 20 SAM3U1E Serial Peripheral Interface (SPI) */
|
||||
SSC_IRQn = 21, /**< 21 SAM3U1E Synchronous Serial Controller (SSC) */
|
||||
TC0_IRQn = 22, /**< 22 SAM3U1E Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 23, /**< 23 SAM3U1E Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 24, /**< 24 SAM3U1E Timer Counter 2 (TC2) */
|
||||
PWM_IRQn = 25, /**< 25 SAM3U1E Pulse Width Modulation Controller (PWM) */
|
||||
ADC12B_IRQn = 26, /**< 26 SAM3U1E 12-bit ADC Controller (ADC12B) */
|
||||
ADC_IRQn = 27, /**< 27 SAM3U1E 10-bit ADC Controller (ADC) */
|
||||
DMAC_IRQn = 28, /**< 28 SAM3U1E DMA Controller (DMAC) */
|
||||
UDPHS_IRQn = 29 /**< 29 SAM3U1E USB Device High Speed (UDPHS) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< SAM3U1E does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3U1E uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1E_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/ADC12B.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DMAC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/HSMCI.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SMC.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SSC.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/UDPHS.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1E_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/HSMCI.h"
|
||||
#include "instance/SSC.h"
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/USART2.h"
|
||||
#include "instance/USART3.h"
|
||||
#include "instance/UDPHS.h"
|
||||
#include "instance/ADC12B.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DMAC.h"
|
||||
#include "instance/SMC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/EFC0.h"
|
||||
#include "instance/EFC1.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/PIOC.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1E_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
|
||||
#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
|
||||
#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
|
||||
#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
|
||||
#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
|
||||
#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
|
||||
#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
|
||||
#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
|
||||
#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
|
||||
#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
|
||||
#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
|
||||
#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
|
||||
#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
|
||||
#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
|
||||
#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1E_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
|
||||
#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
|
||||
#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
|
||||
#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
|
||||
#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
|
||||
#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
|
||||
#define USART3 CAST(Usart , 0x4009C000U) /**< \brief (USART3 ) Base Address */
|
||||
#define PDC_USART3 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART3) Base Address */
|
||||
#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
|
||||
#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
|
||||
#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
|
||||
#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
|
||||
#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
|
||||
#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
|
||||
#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
|
||||
#define PIOC CAST(Pio , 0x400E1000U) /**< \brief (PIOC ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U1E_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3U1E.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3U1E */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x10000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH_NB_OF_PAGES 32
|
||||
#define IRAM_SIZE 0x5000
|
||||
|
||||
#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
|
||||
#if defined IFLASH0_SIZE
|
||||
#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
|
||||
#endif
|
||||
#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
|
||||
#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
|
||||
#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
|
||||
#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
|
||||
#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3U1E_ */
|
||||
|
|
@ -0,0 +1,292 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U2C_
|
||||
#define _SAM3U2C_
|
||||
|
||||
/** \addtogroup SAM3U2C_definitions SAM3U2C definitions
|
||||
This file defines all structures and symbols for SAM3U2C:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2C_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3U2C specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3U2C Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3U2C Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3U2C Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3U2C Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3U2C Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3U2C Power Management Controller (PMC) */
|
||||
EFC0_IRQn = 6, /**< 6 SAM3U2C Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
EFC1_IRQn = 7, /**< 7 SAM3U2C Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
UART_IRQn = 8, /**< 8 SAM3U2C Universal Asynchronous Receiver Transmitter (UART) */
|
||||
SMC_IRQn = 9, /**< 9 SAM3U2C Static Memory Controller (SMC) */
|
||||
PIOA_IRQn = 10, /**< 10 SAM3U2C Parallel I/O Controller A, (PIOA) */
|
||||
PIOB_IRQn = 11, /**< 11 SAM3U2C Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 12, /**< 12 SAM3U2C Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 13, /**< 13 SAM3U2C USART 0 (USART0) */
|
||||
USART1_IRQn = 14, /**< 14 SAM3U2C USART 1 (USART1) */
|
||||
USART2_IRQn = 15, /**< 15 SAM3U2C USART 2 (USART2) */
|
||||
USART3_IRQn = 16, /**< 16 SAM3U2C USART 3 (USART3) */
|
||||
HSMCI_IRQn = 17, /**< 17 SAM3U2C High Speed Multimedia Card Interface (HSMCI) */
|
||||
TWI0_IRQn = 18, /**< 18 SAM3U2C Two-Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 19, /**< 19 SAM3U2C Two-Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 20, /**< 20 SAM3U2C Serial Peripheral Interface (SPI) */
|
||||
SSC_IRQn = 21, /**< 21 SAM3U2C Synchronous Serial Controller (SSC) */
|
||||
TC0_IRQn = 22, /**< 22 SAM3U2C Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 23, /**< 23 SAM3U2C Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 24, /**< 24 SAM3U2C Timer Counter 2 (TC2) */
|
||||
PWM_IRQn = 25, /**< 25 SAM3U2C Pulse Width Modulation Controller (PWM) */
|
||||
ADC12B_IRQn = 26, /**< 26 SAM3U2C 12-bit ADC Controller (ADC12B) */
|
||||
ADC_IRQn = 27, /**< 27 SAM3U2C 10-bit ADC Controller (ADC) */
|
||||
DMAC_IRQn = 28, /**< 28 SAM3U2C DMA Controller (DMAC) */
|
||||
UDPHS_IRQn = 29 /**< 29 SAM3U2C USB Device High Speed (UDPHS) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< SAM3U2C does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3U2C uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2C_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/ADC12B.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DMAC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/HSMCI.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SMC.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SSC.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/UDPHS.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2C_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/HSMCI.h"
|
||||
#include "instance/SSC.h"
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/USART2.h"
|
||||
#include "instance/UDPHS.h"
|
||||
#include "instance/ADC12B.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DMAC.h"
|
||||
#include "instance/SMC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/EFC0.h"
|
||||
#include "instance/EFC1.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2C_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
|
||||
#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
|
||||
#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
|
||||
#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
|
||||
#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
|
||||
#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
|
||||
#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
|
||||
#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
|
||||
#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
|
||||
#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
|
||||
#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
|
||||
#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
|
||||
#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
|
||||
#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
|
||||
#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2C_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
|
||||
#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
|
||||
#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
|
||||
#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
|
||||
#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
|
||||
#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
|
||||
#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
|
||||
#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
|
||||
#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
|
||||
#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
|
||||
#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
|
||||
#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
|
||||
#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2C_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3U2C.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x20000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH_NB_OF_PAGES 64
|
||||
#define IRAM_SIZE 0x9000
|
||||
|
||||
#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
|
||||
#if defined IFLASH0_SIZE
|
||||
#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
|
||||
#endif
|
||||
#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
|
||||
#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
|
||||
#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
|
||||
#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
|
||||
#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3U2C_ */
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U2E_
|
||||
#define _SAM3U2E_
|
||||
|
||||
/** \addtogroup SAM3U2E_definitions SAM3U2E definitions
|
||||
This file defines all structures and symbols for SAM3U2E:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2E_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3U2E specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3U2E Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3U2E Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3U2E Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3U2E Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3U2E Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3U2E Power Management Controller (PMC) */
|
||||
EFC0_IRQn = 6, /**< 6 SAM3U2E Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
EFC1_IRQn = 7, /**< 7 SAM3U2E Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
UART_IRQn = 8, /**< 8 SAM3U2E Universal Asynchronous Receiver Transmitter (UART) */
|
||||
SMC_IRQn = 9, /**< 9 SAM3U2E Static Memory Controller (SMC) */
|
||||
PIOA_IRQn = 10, /**< 10 SAM3U2E Parallel I/O Controller A, (PIOA) */
|
||||
PIOB_IRQn = 11, /**< 11 SAM3U2E Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 12, /**< 12 SAM3U2E Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 13, /**< 13 SAM3U2E USART 0 (USART0) */
|
||||
USART1_IRQn = 14, /**< 14 SAM3U2E USART 1 (USART1) */
|
||||
USART2_IRQn = 15, /**< 15 SAM3U2E USART 2 (USART2) */
|
||||
USART3_IRQn = 16, /**< 16 SAM3U2E USART 3 (USART3) */
|
||||
HSMCI_IRQn = 17, /**< 17 SAM3U2E High Speed Multimedia Card Interface (HSMCI) */
|
||||
TWI0_IRQn = 18, /**< 18 SAM3U2E Two-Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 19, /**< 19 SAM3U2E Two-Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 20, /**< 20 SAM3U2E Serial Peripheral Interface (SPI) */
|
||||
SSC_IRQn = 21, /**< 21 SAM3U2E Synchronous Serial Controller (SSC) */
|
||||
TC0_IRQn = 22, /**< 22 SAM3U2E Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 23, /**< 23 SAM3U2E Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 24, /**< 24 SAM3U2E Timer Counter 2 (TC2) */
|
||||
PWM_IRQn = 25, /**< 25 SAM3U2E Pulse Width Modulation Controller (PWM) */
|
||||
ADC12B_IRQn = 26, /**< 26 SAM3U2E 12-bit ADC Controller (ADC12B) */
|
||||
ADC_IRQn = 27, /**< 27 SAM3U2E 10-bit ADC Controller (ADC) */
|
||||
DMAC_IRQn = 28, /**< 28 SAM3U2E DMA Controller (DMAC) */
|
||||
UDPHS_IRQn = 29 /**< 29 SAM3U2E USB Device High Speed (UDPHS) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< SAM3U2E does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3U2E uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2E_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/ADC12B.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DMAC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/HSMCI.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SMC.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SSC.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/UDPHS.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2E_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/HSMCI.h"
|
||||
#include "instance/SSC.h"
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/USART2.h"
|
||||
#include "instance/USART3.h"
|
||||
#include "instance/UDPHS.h"
|
||||
#include "instance/ADC12B.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DMAC.h"
|
||||
#include "instance/SMC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/EFC0.h"
|
||||
#include "instance/EFC1.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/PIOC.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2E_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
|
||||
#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
|
||||
#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
|
||||
#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
|
||||
#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
|
||||
#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
|
||||
#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
|
||||
#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
|
||||
#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
|
||||
#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
|
||||
#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
|
||||
#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
|
||||
#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
|
||||
#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
|
||||
#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2E_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
|
||||
#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
|
||||
#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
|
||||
#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
|
||||
#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
|
||||
#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
|
||||
#define USART3 CAST(Usart , 0x4009C000U) /**< \brief (USART3 ) Base Address */
|
||||
#define PDC_USART3 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART3) Base Address */
|
||||
#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
|
||||
#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
|
||||
#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
|
||||
#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
|
||||
#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
|
||||
#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
|
||||
#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
|
||||
#define PIOC CAST(Pio , 0x400E1000U) /**< \brief (PIOC ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U2E_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3U2E.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3U2E */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH_SIZE 0x20000
|
||||
#define IFLASH_PAGE_SIZE 256
|
||||
#define IFLASH_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH_NB_OF_PAGES 64
|
||||
#define IRAM_SIZE 0x9000
|
||||
|
||||
#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
|
||||
#if defined IFLASH0_SIZE
|
||||
#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
|
||||
#endif
|
||||
#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
|
||||
#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
|
||||
#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
|
||||
#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
|
||||
#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3U2E_ */
|
||||
|
|
@ -0,0 +1,297 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U4C_
|
||||
#define _SAM3U4C_
|
||||
|
||||
/** \addtogroup SAM3U4C_definitions SAM3U4C definitions
|
||||
This file defines all structures and symbols for SAM3U4C:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4C_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3U4C specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3U4C Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3U4C Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3U4C Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3U4C Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3U4C Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3U4C Power Management Controller (PMC) */
|
||||
EFC0_IRQn = 6, /**< 6 SAM3U4C Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
EFC1_IRQn = 7, /**< 7 SAM3U4C Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
UART_IRQn = 8, /**< 8 SAM3U4C Universal Asynchronous Receiver Transmitter (UART) */
|
||||
SMC_IRQn = 9, /**< 9 SAM3U4C Static Memory Controller (SMC) */
|
||||
PIOA_IRQn = 10, /**< 10 SAM3U4C Parallel I/O Controller A, (PIOA) */
|
||||
PIOB_IRQn = 11, /**< 11 SAM3U4C Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 12, /**< 12 SAM3U4C Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 13, /**< 13 SAM3U4C USART 0 (USART0) */
|
||||
USART1_IRQn = 14, /**< 14 SAM3U4C USART 1 (USART1) */
|
||||
USART2_IRQn = 15, /**< 15 SAM3U4C USART 2 (USART2) */
|
||||
USART3_IRQn = 16, /**< 16 SAM3U4C USART 3 (USART3) */
|
||||
HSMCI_IRQn = 17, /**< 17 SAM3U4C High Speed Multimedia Card Interface (HSMCI) */
|
||||
TWI0_IRQn = 18, /**< 18 SAM3U4C Two-Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 19, /**< 19 SAM3U4C Two-Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 20, /**< 20 SAM3U4C Serial Peripheral Interface (SPI) */
|
||||
SSC_IRQn = 21, /**< 21 SAM3U4C Synchronous Serial Controller (SSC) */
|
||||
TC0_IRQn = 22, /**< 22 SAM3U4C Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 23, /**< 23 SAM3U4C Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 24, /**< 24 SAM3U4C Timer Counter 2 (TC2) */
|
||||
PWM_IRQn = 25, /**< 25 SAM3U4C Pulse Width Modulation Controller (PWM) */
|
||||
ADC12B_IRQn = 26, /**< 26 SAM3U4C 12-bit ADC Controller (ADC12B) */
|
||||
ADC_IRQn = 27, /**< 27 SAM3U4C 10-bit ADC Controller (ADC) */
|
||||
DMAC_IRQn = 28, /**< 28 SAM3U4C DMA Controller (DMAC) */
|
||||
UDPHS_IRQn = 29 /**< 29 SAM3U4C USB Device High Speed (UDPHS) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< SAM3U4C does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3U4C uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4C_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/ADC12B.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DMAC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/HSMCI.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SMC.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SSC.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/UDPHS.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4C_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/HSMCI.h"
|
||||
#include "instance/SSC.h"
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/USART2.h"
|
||||
#include "instance/UDPHS.h"
|
||||
#include "instance/ADC12B.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DMAC.h"
|
||||
#include "instance/SMC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/EFC0.h"
|
||||
#include "instance/EFC1.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4C_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
|
||||
#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
|
||||
#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
|
||||
#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
|
||||
#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
|
||||
#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
|
||||
#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
|
||||
#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
|
||||
#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
|
||||
#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
|
||||
#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
|
||||
#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
|
||||
#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
|
||||
#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
|
||||
#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4C_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
|
||||
#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
|
||||
#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
|
||||
#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
|
||||
#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
|
||||
#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
|
||||
#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
|
||||
#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
|
||||
#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
|
||||
#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
|
||||
#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
|
||||
#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
|
||||
#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4C_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3U4C.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3U4C */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH0_SIZE 0x20000
|
||||
#define IFLASH0_PAGE_SIZE 256
|
||||
#define IFLASH0_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH0_NB_OF_PAGES 64
|
||||
#define IFLASH1_SIZE 0x20000
|
||||
#define IFLASH1_PAGE_SIZE 256
|
||||
#define IFLASH1_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH1_NB_OF_PAGES 64
|
||||
#define IRAM_SIZE 0xD000
|
||||
#define IFLASH_SIZE 0x40000
|
||||
|
||||
#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
|
||||
#if defined IFLASH0_SIZE
|
||||
#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
|
||||
#endif
|
||||
#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
|
||||
#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
|
||||
#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
|
||||
#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
|
||||
#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3U4C_ */
|
||||
|
|
@ -0,0 +1,302 @@
|
|||
/* %ATMEL_LICENCE% */
|
||||
|
||||
#ifndef _SAM3U4E_
|
||||
#define _SAM3U4E_
|
||||
|
||||
/** \addtogroup SAM3U4E_definitions SAM3U4E definitions
|
||||
This file defines all structures and symbols for SAM3U4E:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- PIO definitions
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <stdint.h>
|
||||
#ifndef __cplusplus
|
||||
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#else
|
||||
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
|
||||
#endif
|
||||
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
|
||||
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
|
||||
#define CAST(type, value) (((type)*)(value))
|
||||
#define REG_ACCESS(type, address) (*((type)*)(address)) /**< C code: Register value */
|
||||
#else
|
||||
#define CAST(type, value) (value)
|
||||
#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
|
||||
#endif
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* CMSIS DEFINITIONS FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4E_cmsis CMSIS Definitions */
|
||||
/*@{*/
|
||||
|
||||
/**< Interrupt Number Definition */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions Numbers ******************************/
|
||||
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */
|
||||
/****** SAM3U4E specific Interrupt Numbers *********************************/
|
||||
|
||||
SUPC_IRQn = 0, /**< 0 SAM3U4E Supply Controller (SUPC) */
|
||||
RSTC_IRQn = 1, /**< 1 SAM3U4E Reset Controller (RSTC) */
|
||||
RTC_IRQn = 2, /**< 2 SAM3U4E Real Time Clock (RTC) */
|
||||
RTT_IRQn = 3, /**< 3 SAM3U4E Real Time Timer (RTT) */
|
||||
WDT_IRQn = 4, /**< 4 SAM3U4E Watchdog Timer (WDT) */
|
||||
PMC_IRQn = 5, /**< 5 SAM3U4E Power Management Controller (PMC) */
|
||||
EFC0_IRQn = 6, /**< 6 SAM3U4E Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
EFC1_IRQn = 7, /**< 7 SAM3U4E Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
UART_IRQn = 8, /**< 8 SAM3U4E Universal Asynchronous Receiver Transmitter (UART) */
|
||||
SMC_IRQn = 9, /**< 9 SAM3U4E Static Memory Controller (SMC) */
|
||||
PIOA_IRQn = 10, /**< 10 SAM3U4E Parallel I/O Controller A, (PIOA) */
|
||||
PIOB_IRQn = 11, /**< 11 SAM3U4E Parallel I/O Controller B (PIOB) */
|
||||
PIOC_IRQn = 12, /**< 12 SAM3U4E Parallel I/O Controller C (PIOC) */
|
||||
USART0_IRQn = 13, /**< 13 SAM3U4E USART 0 (USART0) */
|
||||
USART1_IRQn = 14, /**< 14 SAM3U4E USART 1 (USART1) */
|
||||
USART2_IRQn = 15, /**< 15 SAM3U4E USART 2 (USART2) */
|
||||
USART3_IRQn = 16, /**< 16 SAM3U4E USART 3 (USART3) */
|
||||
HSMCI_IRQn = 17, /**< 17 SAM3U4E High Speed Multimedia Card Interface (HSMCI) */
|
||||
TWI0_IRQn = 18, /**< 18 SAM3U4E Two-Wire Interface 0 (TWI0) */
|
||||
TWI1_IRQn = 19, /**< 19 SAM3U4E Two-Wire Interface 1 (TWI1) */
|
||||
SPI_IRQn = 20, /**< 20 SAM3U4E Serial Peripheral Interface (SPI) */
|
||||
SSC_IRQn = 21, /**< 21 SAM3U4E Synchronous Serial Controller (SSC) */
|
||||
TC0_IRQn = 22, /**< 22 SAM3U4E Timer Counter 0 (TC0) */
|
||||
TC1_IRQn = 23, /**< 23 SAM3U4E Timer Counter 1 (TC1) */
|
||||
TC2_IRQn = 24, /**< 24 SAM3U4E Timer Counter 2 (TC2) */
|
||||
PWM_IRQn = 25, /**< 25 SAM3U4E Pulse Width Modulation Controller (PWM) */
|
||||
ADC12B_IRQn = 26, /**< 26 SAM3U4E 12-bit ADC Controller (ADC12B) */
|
||||
ADC_IRQn = 27, /**< 27 SAM3U4E 10-bit ADC Controller (ADC) */
|
||||
DMAC_IRQn = 28, /**< 28 SAM3U4E DMA Controller (DMAC) */
|
||||
UDPHS_IRQn = 29 /**< 29 SAM3U4E USB Device High Speed (UDPHS) */
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
|
||||
*/
|
||||
|
||||
#define __MPU_PRESENT 1 /**< SAM3U4E does provide a MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /**< SAM3U4E uses 4 Bits for the Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/*
|
||||
* \brief CMSIS includes
|
||||
*/
|
||||
|
||||
#include <core_cm3.h>
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4E_api Peripheral Software API */
|
||||
/*@{*/
|
||||
|
||||
#include "component/ADC.h"
|
||||
#include "component/ADC12B.h"
|
||||
#include "component/CHIPID.h"
|
||||
#include "component/DMAC.h"
|
||||
#include "component/EFC.h"
|
||||
#include "component/GPBR.h"
|
||||
#include "component/HSMCI.h"
|
||||
#include "component/MATRIX.h"
|
||||
#include "component/PDC.h"
|
||||
#include "component/PIO.h"
|
||||
#include "component/PMC.h"
|
||||
#include "component/PWM.h"
|
||||
#include "component/RSTC.h"
|
||||
#include "component/RTC.h"
|
||||
#include "component/RTT.h"
|
||||
#include "component/SMC.h"
|
||||
#include "component/SPI.h"
|
||||
#include "component/SSC.h"
|
||||
#include "component/SUPC.h"
|
||||
#include "component/TC.h"
|
||||
#include "component/TWI.h"
|
||||
#include "component/UART.h"
|
||||
#include "component/UDPHS.h"
|
||||
#include "component/USART.h"
|
||||
#include "component/WDT.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* REGISTER ACCESS DEFINITIONS FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4E_reg Registers Access Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "instance/HSMCI.h"
|
||||
#include "instance/SSC.h"
|
||||
#include "instance/SPI.h"
|
||||
#include "instance/TC0.h"
|
||||
#include "instance/TWI0.h"
|
||||
#include "instance/TWI1.h"
|
||||
#include "instance/PWM.h"
|
||||
#include "instance/USART0.h"
|
||||
#include "instance/USART1.h"
|
||||
#include "instance/USART2.h"
|
||||
#include "instance/USART3.h"
|
||||
#include "instance/UDPHS.h"
|
||||
#include "instance/ADC12B.h"
|
||||
#include "instance/ADC.h"
|
||||
#include "instance/DMAC.h"
|
||||
#include "instance/SMC.h"
|
||||
#include "instance/MATRIX.h"
|
||||
#include "instance/PMC.h"
|
||||
#include "instance/UART.h"
|
||||
#include "instance/CHIPID.h"
|
||||
#include "instance/EFC0.h"
|
||||
#include "instance/EFC1.h"
|
||||
#include "instance/PIOA.h"
|
||||
#include "instance/PIOB.h"
|
||||
#include "instance/PIOC.h"
|
||||
#include "instance/RSTC.h"
|
||||
#include "instance/SUPC.h"
|
||||
#include "instance/RTT.h"
|
||||
#include "instance/WDT.h"
|
||||
#include "instance/RTC.h"
|
||||
#include "instance/GPBR.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PERIPHERAL ID DEFINITIONS FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4E_id Peripheral Ids Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
|
||||
#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
|
||||
#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */
|
||||
#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */
|
||||
#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
|
||||
#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
|
||||
#define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */
|
||||
#define ID_EFC1 ( 7) /**< \brief Enhanced Embedded Flash Controller 1 (EFC1) */
|
||||
#define ID_UART ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART) */
|
||||
#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */
|
||||
#define ID_PIOA (10) /**< \brief Parallel I/O Controller A, (PIOA) */
|
||||
#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */
|
||||
#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */
|
||||
#define ID_USART0 (13) /**< \brief USART 0 (USART0) */
|
||||
#define ID_USART1 (14) /**< \brief USART 1 (USART1) */
|
||||
#define ID_USART2 (15) /**< \brief USART 2 (USART2) */
|
||||
#define ID_USART3 (16) /**< \brief USART 3 (USART3) */
|
||||
#define ID_HSMCI (17) /**< \brief High Speed Multimedia Card Interface (HSMCI) */
|
||||
#define ID_TWI0 (18) /**< \brief Two-Wire Interface 0 (TWI0) */
|
||||
#define ID_TWI1 (19) /**< \brief Two-Wire Interface 1 (TWI1) */
|
||||
#define ID_SPI (20) /**< \brief Serial Peripheral Interface (SPI) */
|
||||
#define ID_SSC (21) /**< \brief Synchronous Serial Controller (SSC) */
|
||||
#define ID_TC0 (22) /**< \brief Timer Counter 0 (TC0) */
|
||||
#define ID_TC1 (23) /**< \brief Timer Counter 1 (TC1) */
|
||||
#define ID_TC2 (24) /**< \brief Timer Counter 2 (TC2) */
|
||||
#define ID_PWM (25) /**< \brief Pulse Width Modulation Controller (PWM) */
|
||||
#define ID_ADC12B (26) /**< \brief 12-bit ADC Controller (ADC12B) */
|
||||
#define ID_ADC (27) /**< \brief 10-bit ADC Controller (ADC) */
|
||||
#define ID_DMAC (28) /**< \brief DMA Controller (DMAC) */
|
||||
#define ID_UDPHS (29) /**< \brief USB Device High Speed (UDPHS) */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* BASE ADDRESS DEFINITIONS FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4E_base Peripheral Base Address Definitions */
|
||||
/*@{*/
|
||||
|
||||
#define HSMCI CAST(Hsmci , 0x40000000U) /**< \brief (HSMCI ) Base Address */
|
||||
#define SSC CAST(Ssc , 0x40004000U) /**< \brief (SSC ) Base Address */
|
||||
#define SPI CAST(Spi , 0x40008000U) /**< \brief (SPI ) Base Address */
|
||||
#define TC0 CAST(Tc , 0x40080000U) /**< \brief (TC0 ) Base Address */
|
||||
#define TWI0 CAST(Twi , 0x40084000U) /**< \brief (TWI0 ) Base Address */
|
||||
#define PDC_TWI0 CAST(Pdc , 0x40084100U) /**< \brief (PDC_TWI0 ) Base Address */
|
||||
#define TWI1 CAST(Twi , 0x40088000U) /**< \brief (TWI1 ) Base Address */
|
||||
#define PDC_TWI1 CAST(Pdc , 0x40088100U) /**< \brief (PDC_TWI1 ) Base Address */
|
||||
#define PWM CAST(Pwm , 0x4008C000U) /**< \brief (PWM ) Base Address */
|
||||
#define PDC_PWM CAST(Pdc , 0x4008C100U) /**< \brief (PDC_PWM ) Base Address */
|
||||
#define USART0 CAST(Usart , 0x40090000U) /**< \brief (USART0 ) Base Address */
|
||||
#define PDC_USART0 CAST(Pdc , 0x40090100U) /**< \brief (PDC_USART0) Base Address */
|
||||
#define USART1 CAST(Usart , 0x40094000U) /**< \brief (USART1 ) Base Address */
|
||||
#define PDC_USART1 CAST(Pdc , 0x40094100U) /**< \brief (PDC_USART1) Base Address */
|
||||
#define USART2 CAST(Usart , 0x40098000U) /**< \brief (USART2 ) Base Address */
|
||||
#define PDC_USART2 CAST(Pdc , 0x40098100U) /**< \brief (PDC_USART2) Base Address */
|
||||
#define USART3 CAST(Usart , 0x4009C000U) /**< \brief (USART3 ) Base Address */
|
||||
#define PDC_USART3 CAST(Pdc , 0x4009C100U) /**< \brief (PDC_USART3) Base Address */
|
||||
#define UDPHS CAST(Udphs , 0x400A4000U) /**< \brief (UDPHS ) Base Address */
|
||||
#define ADC12B CAST(Adc12b , 0x400A8000U) /**< \brief (ADC12B ) Base Address */
|
||||
#define PDC_ADC12B CAST(Pdc , 0x400A8100U) /**< \brief (PDC_ADC12B) Base Address */
|
||||
#define ADC CAST(Adc , 0x400AC000U) /**< \brief (ADC ) Base Address */
|
||||
#define PDC_ADC CAST(Pdc , 0x400AC100U) /**< \brief (PDC_ADC ) Base Address */
|
||||
#define DMAC CAST(Dmac , 0x400B0000U) /**< \brief (DMAC ) Base Address */
|
||||
#define SMC CAST(Smc , 0x400E0000U) /**< \brief (SMC ) Base Address */
|
||||
#define MATRIX CAST(Matrix , 0x400E0200U) /**< \brief (MATRIX ) Base Address */
|
||||
#define PMC CAST(Pmc , 0x400E0400U) /**< \brief (PMC ) Base Address */
|
||||
#define UART CAST(Uart , 0x400E0600U) /**< \brief (UART ) Base Address */
|
||||
#define PDC_UART CAST(Pdc , 0x400E0700U) /**< \brief (PDC_UART ) Base Address */
|
||||
#define CHIPID CAST(Chipid , 0x400E0740U) /**< \brief (CHIPID ) Base Address */
|
||||
#define EFC0 CAST(Efc , 0x400E0800U) /**< \brief (EFC0 ) Base Address */
|
||||
#define EFC1 CAST(Efc , 0x400E0A00U) /**< \brief (EFC1 ) Base Address */
|
||||
#define PIOA CAST(Pio , 0x400E0C00U) /**< \brief (PIOA ) Base Address */
|
||||
#define PIOB CAST(Pio , 0x400E0E00U) /**< \brief (PIOB ) Base Address */
|
||||
#define PIOC CAST(Pio , 0x400E1000U) /**< \brief (PIOC ) Base Address */
|
||||
#define RSTC CAST(Rstc , 0x400E1200U) /**< \brief (RSTC ) Base Address */
|
||||
#define SUPC CAST(Supc , 0x400E1210U) /**< \brief (SUPC ) Base Address */
|
||||
#define RTT CAST(Rtt , 0x400E1230U) /**< \brief (RTT ) Base Address */
|
||||
#define WDT CAST(Wdt , 0x400E1250U) /**< \brief (WDT ) Base Address */
|
||||
#define RTC CAST(Rtc , 0x400E1260U) /**< \brief (RTC ) Base Address */
|
||||
#define GPBR CAST(Gpbr , 0x400E1290U) /**< \brief (GPBR ) Base Address */
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* PIO DEFINITIONS FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
/** \addtogroup SAM3U4E_pio Peripheral Pio Definitions */
|
||||
/*@{*/
|
||||
|
||||
#include "pio/SAM3U4E.h"
|
||||
/*@}*/
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* MEMORY MAPPING DEFINITIONS FOR SAM3U4E */
|
||||
/* ************************************************************************** */
|
||||
|
||||
#define IFLASH0_SIZE 0x20000
|
||||
#define IFLASH0_PAGE_SIZE 256
|
||||
#define IFLASH0_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH0_NB_OF_PAGES 64
|
||||
#define IFLASH1_SIZE 0x20000
|
||||
#define IFLASH1_PAGE_SIZE 256
|
||||
#define IFLASH1_LOCK_REGION_SIZE 8192
|
||||
#define IFLASH1_NB_OF_PAGES 64
|
||||
#define IRAM_SIZE 0xD000
|
||||
#define IFLASH_SIZE 0x40000
|
||||
|
||||
#define IFLASH0_ADDR (0x00080000u) /**< Internal Flash 0 base address */
|
||||
#if defined IFLASH0_SIZE
|
||||
#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
|
||||
#endif
|
||||
#define IROM_ADDR (0x00180000u) /**< Internal ROM base address */
|
||||
#define IRAM0_ADDR (0x20000000u) /**< Internal RAM 0 base address */
|
||||
#define IRAM1_ADDR (0x20080000u) /**< Internal RAM 1 base address */
|
||||
#define NFC_RAM_ADDR (0x20100000u) /**< NAND Flash Controller RAM base address */
|
||||
#define UDPHS_RAM_ADDR (0x20180000u) /**< USB High Speed Device Port RAM base address */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAM3U4E_ */
|
||||
Loading…
Reference in New Issue