diff --git a/hardware/sam/cores/sam/Arduino.h b/hardware/sam/cores/sam/Arduino.h
index b3d0d6ea7..78cecd7c1 100644
--- a/hardware/sam/cores/sam/Arduino.h
+++ b/hardware/sam/cores/sam/Arduino.h
@@ -98,6 +98,15 @@ typedef enum _EAnalogChannel
   DAC1
 } EAnalogChannel ;
 
+/**
+ * Pin Attributes to be OR-ed
+ */
+#define PIN_ATTR_COMBO         (1UL<<0)
+#define PIN_ATTR_ANALOG        (1UL<<1)
+#define PIN_ATTR_DIGITAL       (1UL<<2)
+#define PIN_ATTR_PWM           (1UL<<3)
+#define PIN_ATTR_TIMER         (1UL<<4)
+
 /* Types used for the tables below */
 typedef struct _PinDescription
 {
@@ -105,6 +114,7 @@ typedef struct _PinDescription
   uint32_t ulPin ;
   uint32_t ulPeripheralId ;
   EPioType ulPinType ;
+  uint32_t ulPinConfiguration ;
   uint32_t ulPinAttribute ;
   EAnalogChannel ulAnalogChannel ;
 } PinDescription ;
diff --git a/hardware/sam/cores/sam/wiring_digital.c b/hardware/sam/cores/sam/wiring_digital.c
index d060c129c..dc66e538a 100644
--- a/hardware/sam/cores/sam/wiring_digital.c
+++ b/hardware/sam/cores/sam/wiring_digital.c
@@ -27,7 +27,7 @@ extern void pinMode( uint32_t ulPin, uint32_t ulMode )
             {
                 PMC_DisablePeripheral( g_APinDescription[ulPin].ulPeripheralId ) ;
             }
-            PIO_Configure( g_APinDescription[ulPin].pPort, PIO_OUTPUT_1, g_APinDescription[ulPin].ulPin, g_APinDescription[ulPin].ulPinAttribute ) ;
+            PIO_Configure( g_APinDescription[ulPin].pPort, PIO_OUTPUT_1, g_APinDescription[ulPin].ulPin, g_APinDescription[ulPin].ulPinConfiguration ) ;
         break ;
 
         default:
diff --git a/hardware/sam/libraries/SPI/SPI.cpp b/hardware/sam/libraries/SPI/SPI.cpp
index 8216af5bb..10170ef8d 100644
--- a/hardware/sam/libraries/SPI/SPI.cpp
+++ b/hardware/sam/libraries/SPI/SPI.cpp
@@ -35,27 +35,48 @@ void SPIClass::begin()
   SPCR |= _BV(SPE);
 }
 
-void SPIClass::end() {
+void SPIClass::end()
+{
   SPCR &= ~_BV(SPE);
 }
 
-void SPIClass::setBitOrder(uint8_t bitOrder)
+void SPIClass::setBitOrder( uint8_t bitOrder )
 {
-  if(bitOrder == LSBFIRST) {
+  if(bitOrder == LSBFIRST)
+  {
     SPCR |= _BV(DORD);
-  } else {
+  }
+  else
+  {
     SPCR &= ~(_BV(DORD));
   }
 }
 
-void SPIClass::setDataMode(uint8_t mode)
+void SPIClass::setDataMode( uint8_t mode )
 {
   SPCR = (SPCR & ~SPI_MODE_MASK) | mode;
 }
 
-void SPIClass::setClockDivider(uint8_t rate)
+void SPIClass::setClockDivider( uint8_t rate )
 {
   SPCR = (SPCR & ~SPI_CLOCK_MASK) | (rate & SPI_CLOCK_MASK);
   SPSR = (SPSR & ~SPI_2XCLOCK_MASK) | ((rate >> 2) & SPI_2XCLOCK_MASK);
 }
 
+byte SPIClass::transfer( byte _data ) 
+{
+  SPDR = _data;
+  while (!(SPSR & _BV(SPIF)))
+    ;
+  return SPDR;
+}
+
+void SPIClass::attachInterrupt( void )
+{
+  SPCR |= _BV(SPIE) ;
+}
+
+void SPIClass::detachInterrupt( void )
+{
+  SPCR &= ~_BV(SPIE) ;
+}
diff --git a/hardware/sam/libraries/SPI/SPI.h b/hardware/sam/libraries/SPI/SPI.h
index d42cfb777..b643c1f1d 100644
--- a/hardware/sam/libraries/SPI/SPI.h
+++ b/hardware/sam/libraries/SPI/SPI.h
@@ -14,56 +14,43 @@
 #include "variant.h"
 #include <stdio.h>
 
-#define SPI_CLOCK_DIV4 0x00
-#define SPI_CLOCK_DIV16 0x01
-#define SPI_CLOCK_DIV64 0x02
+#define SPI_CLOCK_DIV4   0x00
+#define SPI_CLOCK_DIV16  0x01
+#define SPI_CLOCK_DIV64  0x02
 #define SPI_CLOCK_DIV128 0x03
-#define SPI_CLOCK_DIV2 0x04
-#define SPI_CLOCK_DIV8 0x05
-#define SPI_CLOCK_DIV32 0x06
-#define SPI_CLOCK_DIV64 0x07
+#define SPI_CLOCK_DIV2   0x04
+#define SPI_CLOCK_DIV8   0x05
+#define SPI_CLOCK_DIV32  0x06
+#define SPI_CLOCK_DIV64  0x07
 
 #define SPI_MODE0 0x00
-#define SPI_MODE1 0x04
-#define SPI_MODE2 0x08
-#define SPI_MODE3 0x0C
+#define SPI_MODE1 0x02
+#define SPI_MODE2 0x01
+#define SPI_MODE3 0x03
 
-#define SPI_MODE_MASK 0x0C  // CPOL = bit 3, CPHA = bit 2 on SPCR
-#define SPI_CLOCK_MASK 0x03  // SPR1 = bit 1, SPR0 = bit 0 on SPCR
+#define SPI_MODE_MASK 0x03     // CPOL = bit 3, CPHA = bit 2 on SPCR
+#define SPI_CLOCK_MASK 0x03    // SPR1 = bit 1, SPR0 = bit 0 on SPCR
 #define SPI_2XCLOCK_MASK 0x01  // SPI2X = bit 0 on SPSR
 
-class SPIClass {
-public:
-  inline static byte transfer(byte _data);
+class SPIClass
+{
+  public:
+    static byte transfer( byte _data ) ;
 
-  // SPI Configuration methods
+    // SPI Configuration methods
 
-  inline static void attachInterrupt();
-  inline static void detachInterrupt(); // Default
+    static void attachInterrupt( void ) ;
+    static void detachInterrupt( void ) ; // Default
 
-  static void begin(); // Default
-  static void end();
+    static void begin( void ) ; // Default
+    static void end( void ) ;
 
-  static void setBitOrder(uint8_t);
-  static void setDataMode(uint8_t);
-  static void setClockDivider(uint8_t);
-};
+    static void setBitOrder( uint8_t ) ;
+    static void setDataMode( uint8_t ) ;
+    static void setClockDivider( uint8_t ) ;
+} ;
 
 extern SPIClass SPI;
 
-byte SPIClass::transfer(byte _data) {
-  SPDR = _data;
-  while (!(SPSR & _BV(SPIF)))
-    ;
-  return SPDR;
-}
-
-void SPIClass::attachInterrupt() {
-  SPCR |= _BV(SPIE);
-}
-
-void SPIClass::detachInterrupt() {
-  SPCR &= ~_BV(SPIE);
-}
 
 #endif
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h
index c29de31b9..39acd5e51 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1a.h
@@ -74,9 +74,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N1A does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N1A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N1A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -253,12 +254,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N1A */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      256
-#define IFLASH_NB_OF_LOCK_BITS  4
-#define IRAM_SIZE               0x2000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h
index 9f81928c6..45d481027 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1b.h
@@ -75,9 +75,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N1B does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N1B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N1B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -258,12 +259,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N1B */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      256
-#define IFLASH_NB_OF_LOCK_BITS  4
-#define IRAM_SIZE               0x2000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h
index 1399e492d..7a6a36528 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n1c.h
@@ -79,9 +79,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N1C does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N1C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N1C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -272,12 +273,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N1C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      256
-#define IFLASH_NB_OF_LOCK_BITS  4
-#define IRAM_SIZE               0x2000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x2000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h
index c0896f92b..6938c0f76 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2a.h
@@ -74,9 +74,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N2A does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N2A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N2A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -253,12 +254,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N2A */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      512
-#define IFLASH_NB_OF_LOCK_BITS  8
-#define IRAM_SIZE               0x4000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h
index b0a256c25..04aa6b503 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2b.h
@@ -75,9 +75,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N2B does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N2B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N2B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -258,12 +259,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N2B */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      512
-#define IFLASH_NB_OF_LOCK_BITS  8
-#define IRAM_SIZE               0x4000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h
index c8403343c..07dc9b088 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n2c.h
@@ -79,9 +79,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N2C does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N2C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N2C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -272,12 +273,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N2C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      512
-#define IFLASH_NB_OF_LOCK_BITS  8
-#define IRAM_SIZE               0x4000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x4000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h
index 074fc322c..c97de7786 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4a.h
@@ -74,9 +74,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N4A does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N4A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N4A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4A does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -253,12 +254,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N4A */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x40000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      1024
-#define IFLASH_NB_OF_LOCK_BITS  16
-#define IRAM_SIZE               0x6000
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h
index f61a6f836..98047117a 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4b.h
@@ -75,9 +75,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N4B does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N4B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N4B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4B does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -258,12 +259,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N4B */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x40000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      1024
-#define IFLASH_NB_OF_LOCK_BITS  16
-#define IRAM_SIZE               0x6000
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h
index 450788746..b08f10e95 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/include/sam3n4c.h
@@ -79,9 +79,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          0 /**< SAM3N4C does not provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3N4C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3N4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          0      /**< SAM3N4C does not provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3N4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -272,12 +273,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3N4C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x40000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      1024
-#define IFLASH_NB_OF_LOCK_BITS  16
-#define IRAM_SIZE               0x6000
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0x6000u)
 
 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR   (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c
index 8ed0a3c89..56eb436e2 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.c
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \note
@@ -17,8 +19,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "exceptions.h"
 
 /* @cond 0 */
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h
index 7f8a0ec6e..1b0e34365 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/exceptions.h
@@ -2,6 +2,8 @@
  *
  * \brief This file contains the interface for default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -12,10 +14,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef _EXCEPTIONS_
-#define _EXCEPTIONS_
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -79,5 +79,5 @@ extern void PWM_IrqHandler( void ) ;
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* _EXCEPTIONS_ */
+#endif /* EXCEPTIONS_H_INCLUDED */
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c
index d302591a6..964711518 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/gcc/startup_sam3n.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3N.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           ARMGCC
@@ -10,20 +12,10 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3n.h"
 #include "system_sam3n.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
 /* Initialize segments */
 extern uint32_t _sfixed;
 extern uint32_t _efixed;
@@ -35,10 +27,6 @@ extern uint32_t _ezero;
 extern uint32_t _sstack;
 extern uint32_t _estack;
 
-/*----------------------------------------------------------------------------
- *        ProtoTypes
- *----------------------------------------------------------------------------*/
-
 /** \cond DOXYGEN_SHOULD_SKIP_THIS */
 extern int main(void);
 /** \endcond */
@@ -46,16 +34,13 @@ extern int main(void);
 void ResetException( void ) ;
 extern void __libc_init_array( void ) ;
 
-/*----------------------------------------------------------------------------
- *         Exception Table
- *----------------------------------------------------------------------------*/
-
+/* Exception Table */
 __attribute__((section(".vectors")))
 IntFunc exception_table[] = {
 
     /* Configure Initial Stack Pointer, using linker-generated symbols */
     (IntFunc)(&_estack),
-    ResetException,
+    Reset_Handler,
 
     NMI_Handler,
     HardFault_Handler,
@@ -113,7 +98,7 @@ IntFunc exception_table[] = {
  * \brief This is the code that gets called on processor reset.
  * To initialize the device, and call the main() routine.
  */
-void ResetException( void )
+void Reset_Handler( void )
 {
     uint32_t *pSrc, *pDest ;
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c
index c5e3f4365..50f1ba845 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/iar/startup_sam3n.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3N.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           IAR EWARM
@@ -10,35 +12,17 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*------------------------------------------------------------------------------
- *         Headers
- *------------------------------------------------------------------------------*/
-
 #include "exceptions.h"
-#include "board.h"
+#include "sam3n.h"
 #include "system_sam3n.h"
 
-/*----------------------------------------------------------------------------
- *        Definitions
- *----------------------------------------------------------------------------*/
-
-/*------------------------------------------------------------------------------
- *         Types
- *------------------------------------------------------------------------------*/
 typedef void( *intfunc )( void );
 typedef union { intfunc __fun; void * __ptr; } intvec_elem;
 
-/*------------------------------------------------------------------------------
- *         Prototypes
- *------------------------------------------------------------------------------*/
 extern void __iar_program_start( void ) ;
 extern int __low_level_init( void ) ;
 
-/*------------------------------------------------------------------------------
- *         Exception Table
- *------------------------------------------------------------------------------*/
+/* Exception Table */
 #pragma language=extended
 #pragma segment="CSTACK"
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c
index 2548f4c73..c7e3b17d9 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.c
@@ -3,6 +3,8 @@
  * \brief Provides the low-level initialization functions that called
  * on chip startup.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,8 +15,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "system_sam3n.h"
 #include "sam3n.h"
 
@@ -88,14 +88,17 @@ extern void SystemCoreClockUpdate( void )
 	/* Determine clock frequency according to clock register values */
 	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
 	case PMC_MCKR_CSS_SLOW_CLK:                             /* Slow clock */
-		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
 			SystemCoreClock = OSC32_CLK;
-		else
+        }
+		else {
 			SystemCoreClock = ERC_OSC;
+        }
 		break;
 	case PMC_MCKR_CSS_MAIN_CLK:                             /* Main clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -114,8 +117,9 @@ extern void SystemCoreClockUpdate( void )
 		}
 		break;
 	case PMC_MCKR_CSS_PLL_CLK:                             /* PLL clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -137,10 +141,12 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	}
 
-	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
 		SystemCoreClock /= 3;
-	else
+    }
+	else {
 		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+    }
 }
 
 /* @cond 0 */
@@ -150,3 +156,4 @@ extern void SystemCoreClockUpdate( void )
 #endif
 /**INDENT-ON**/
 /* @endcond */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h
index 2029bd926..bad5560b7 100644
--- a/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h
+++ b/hardware/sam/system/libsam/cmsis/sam3n/source/templates/system_sam3n.h
@@ -3,6 +3,8 @@
  * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
  *           for SAM3 devices.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,10 +15,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef __SYSTEM_SAM3N_
-#define __SYSTEM_SAM3N_
+#ifndef SYSTEM_SAM3N_H_INCLUDED
+#define SYSTEM_SAM3N_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -50,5 +50,5 @@ extern void SystemCoreClockUpdate(void);
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* __SYSTEM_SAM3N_ */
+#endif /* SYSTEM_SAM3N_H_INCLUDED */
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/component/crccu.h b/hardware/sam/system/libsam/cmsis/sam3s/include/component/crccu.h
index 813dbb777..69525983e 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/component/crccu.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/component/crccu.h
@@ -56,9 +56,9 @@ typedef struct {
 #define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
 #define CRCCU_MR_PTYPE_Pos 2
 #define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
-#define   CRCCU_MR_PTYPE_CCIT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
 #define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
-#define   CRCCU_MR_PTYPE_CCIT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
 #define CRCCU_MR_DIVIDER_Pos 4
 #define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
 #define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h
index 4eacade1f..ab6735675 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1a.h
@@ -77,9 +77,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S1A does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S1A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S1A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -279,12 +280,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S1A */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      256
-#define IFLASH_NB_OF_LOCK_BITS  4
-#define IRAM_SIZE               0x4000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h
index 77c90330e..85d114bb5 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1b.h
@@ -80,9 +80,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S1B does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S1B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S1B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -302,12 +303,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S1B */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      256
-#define IFLASH_NB_OF_LOCK_BITS  4
-#define IRAM_SIZE               0x4000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h
index efe76095b..f4a78e183 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s1c.h
@@ -85,9 +85,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S1C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S1C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S1C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -322,12 +323,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S1C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      256
-#define IFLASH_NB_OF_LOCK_BITS  4
-#define IRAM_SIZE               0x4000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (256u)
+#define IFLASH_NB_OF_LOCK_BITS  (4u)
+#define IRAM_SIZE               (0x4000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h
index f9c5ac4d1..c49c97897 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2a.h
@@ -77,9 +77,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S2A does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S2A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S2A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -279,12 +280,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S2A */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      512
-#define IFLASH_NB_OF_LOCK_BITS  8
-#define IRAM_SIZE               0x8000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h
index b7a5da366..8f4cb5f99 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2b.h
@@ -80,9 +80,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S2B does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S2B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S2B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -302,12 +303,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S2B */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      512
-#define IFLASH_NB_OF_LOCK_BITS  8
-#define IRAM_SIZE               0x8000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h
index 68c01af79..c5e8fa729 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s2c.h
@@ -85,9 +85,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S2C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S2C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -322,12 +323,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S2C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      512
-#define IFLASH_NB_OF_LOCK_BITS  8
-#define IRAM_SIZE               0x8000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (512u)
+#define IFLASH_NB_OF_LOCK_BITS  (8u)
+#define IRAM_SIZE               (0x8000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h
index e3bf9ed42..dc966e3f9 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4a.h
@@ -77,9 +77,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S4A does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S4A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S4A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -279,12 +280,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S4A */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x40000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      1024
-#define IFLASH_NB_OF_LOCK_BITS  16
-#define IRAM_SIZE               0xC000
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h
index 9d60c20f3..d3bbd640a 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4b.h
@@ -80,9 +80,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S4B does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S4B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S4B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -302,12 +303,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S4B */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x40000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      1024
-#define IFLASH_NB_OF_LOCK_BITS  16
-#define IRAM_SIZE               0xC000
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h
index 61ab7b585..061dacb82 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/include/sam3s4c.h
@@ -85,9 +85,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S4C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S4C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -322,12 +323,12 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3S4C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x40000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 16384
-#define IFLASH_NB_OF_PAGES      1024
-#define IFLASH_NB_OF_LOCK_BITS  16
-#define IRAM_SIZE               0xC000
+#define IFLASH_SIZE             (0x40000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (16384u)
+#define IFLASH_NB_OF_PAGES      (1024u)
+#define IFLASH_NB_OF_LOCK_BITS  (16u)
+#define IRAM_SIZE               (0xC000u)
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c
index ae895cc17..0c13cefdd 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.c
@@ -2,6 +2,8 @@
  *
  * \brief This file contains the default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -17,8 +19,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "exceptions.h"
 
 /* @cond 0 */
@@ -140,3 +140,4 @@ void Dummy_Handler( void )
 #endif
 /**INDENT-ON**/
 /* @endcond */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h
index 47e253821..dab91aa02 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/exceptions.h
@@ -2,6 +2,8 @@
  *
  * \brief This file contains the interface for default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -12,10 +14,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef _EXCEPTIONS_
-#define _EXCEPTIONS_
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -85,4 +85,5 @@ extern void WDT_IrqHandler( void ) ;
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* _EXCEPTIONS_ */
+#endif /* EXCEPTIONS_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c
index 424e371a3..123c0ce46 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/gcc/startup_sam3s.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3S.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           ARMGCC
@@ -10,20 +12,10 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3s.h"
 #include "system_sam3s.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
 /* Stack Configuration */
 #define STACK_SIZE       0x900     /** Stack size (in DWords) */
 __attribute__ ((aligned(8),section(".stack")))
@@ -38,20 +30,12 @@ extern uint32_t _erelocate;
 extern uint32_t _szero;
 extern uint32_t _ezero;
 
-
-/*----------------------------------------------------------------------------
- *        ProtoTypes
- *----------------------------------------------------------------------------*/
-
 /** \cond DOXYGEN_SHOULD_SKIP_THIS */
 extern int main( void ) ;
 /** \endcond */
 extern void __libc_init_array( void ) ;
 
-/*------------------------------------------------------------------------------
- *         Exception Table
- *------------------------------------------------------------------------------*/
-
+/* Exception Table */
 __attribute__((section(".vectors")))
 IntFunc exception_table[] = {
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c
index d34a5cbba..9c006bfcb 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/iar/startup_sam3s.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3S.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           IAR EWARM
@@ -10,38 +12,20 @@
  *
  ******************************************************************************/
 
-// $asf_license$
-
-/*------------------------------------------------------------------------------
- *         Headers
- *------------------------------------------------------------------------------*/
-
 #include "../exceptions.h"
 #include "sam3.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
 
-/*------------------------------------------------------------------------------
- *         Types
- *------------------------------------------------------------------------------*/
 typedef void( *intfunc )( void );
 typedef union { intfunc __fun; void * __ptr; } intvec_elem;
 
-/*------------------------------------------------------------------------------
- *         Prototypes
- *------------------------------------------------------------------------------*/
 extern void __iar_program_start( void ) ;
 extern int __low_level_init( void ) ;
 
-/*------------------------------------------------------------------------------
- *         Exception Table
- *------------------------------------------------------------------------------*/
+/* Exception Table */
 #pragma language=extended
 #pragma segment="CSTACK"
 
-
 /*  The name "__vector_table" has special meaning for C-SPY: */
 /*  it is where the SP start value is found, and the NVIC vector */
 /*  table register (VTOR) is initialized to this address if != 0. */
@@ -51,57 +35,57 @@ extern int __low_level_init( void ) ;
 const intvec_elem __vector_table[] =
 {
     { .__ptr = __sfe( "CSTACK" ) },
-    Reset_Handler,
+    {Reset_Handler},
 
-    NMI_Handler,
-    HardFault_Handler,
-    MemManage_Handler,
-    BusFault_Handler,
-    UsageFault_Handler,
-    0, 0, 0, 0,         /*  Reserved */
-    SVC_Handler,
-    DebugMon_Handler,
-    0,                  /*  Reserved */
-    PendSV_Handler,
-    SysTick_Handler,
+    {NMI_Handler},
+    {HardFault_Handler},
+    {MemManage_Handler},
+    {BusFault_Handler},
+    {UsageFault_Handler},
+    {0}, {0}, {0}, {0},         /*  Reserved */
+    {SVC_Handler},
+    {DebugMon_Handler},
+    {0},                  /*  Reserved */
+    {PendSV_Handler},
+    {SysTick_Handler},
 
     /* Configurable interrupts */
-    SUPC_IrqHandler,    /* 0  Supply Controller */
-    RSTC_IrqHandler,    /* 1  Reset Controller */
-    RTC_IrqHandler,     /* 2  Real Time Clock */
-    RTT_IrqHandler,     /* 3  Real Time Timer */
-    WDT_IrqHandler,     /* 4  Watchdog Timer */
-    PMC_IrqHandler,     /* 5  PMC */
-    EEFC_IrqHandler,    /* 6  EEFC */
-    Dummy_Handler,   	  /* 7  Reserved */
-    UART0_IrqHandler,   /* 8  UART0 */
-    UART1_IrqHandler,   /* 9  UART1 */
-    SMC_IrqHandler,     /* 10 SMC */
-    PIOA_IrqHandler,    /* 11 Parallel IO Controller A */
-    PIOB_IrqHandler,    /* 12 Parallel IO Controller B */
-    PIOC_IrqHandler,    /* 13 Parallel IO Controller C */
-    USART0_IrqHandler,  /* 14 USART 0 */
-    USART1_IrqHandler,  /* 15 USART 1 */
-    Dummy_Handler,  	  /* 16 Reserved */
-    Dummy_Handler,  	  /* 17 Reserved */
-    MCI_IrqHandler,     /* 18 MCI */
-    TWI0_IrqHandler,    /* 19 TWI 0 */
-    TWI1_IrqHandler,    /* 20 TWI 1 */
-    SPI_IrqHandler,     /* 21 SPI */
-    SSC_IrqHandler,     /* 22 SSC */
-    TC0_IrqHandler,     /* 23 Timer Counter 0 */
-    TC1_IrqHandler,     /* 24 Timer Counter 1 */
-    TC2_IrqHandler,     /* 25 Timer Counter 2 */
-    TC3_IrqHandler,     /* 26 Timer Counter 3 */
-    TC4_IrqHandler,     /* 27 Timer Counter 4 */
-    TC5_IrqHandler,     /* 28 Timer Counter 5 */
-    ADC_IrqHandler,     /* 29 ADC controller */
-    DAC_IrqHandler,     /* 30 DAC controller */
-    PWM_IrqHandler,     /* 31 PWM */
-    CRCCU_IrqHandler,   /* 32 CRC Calculation Unit */
-    ACC_IrqHandler,     /* 33 Analog Comparator */
-    USBD_IrqHandler,    /* 34 USB Device Port */
-    Dummy_Handler   	  /* 35 not used */
+    {SUPC_IrqHandler},    /* 0  Supply Controller */
+    {RSTC_IrqHandler},    /* 1  Reset Controller */
+    {RTC_IrqHandler},     /* 2  Real Time Clock */
+    {RTT_IrqHandler},     /* 3  Real Time Timer */
+    {WDT_IrqHandler},     /* 4  Watchdog Timer */
+    {PMC_IrqHandler},     /* 5  PMC */
+    {EEFC_IrqHandler},    /* 6  EEFC */
+    {Dummy_Handler},  	/* 7  Reserved */
+    {UART0_IrqHandler},   /* 8  UART0 */
+    {UART1_IrqHandler},   /* 9  UART1 */
+    {SMC_IrqHandler},     /* 10 SMC */
+    {PIOA_IrqHandler},    /* 11 Parallel IO Controller A */
+    {PIOB_IrqHandler},    /* 12 Parallel IO Controller B */
+    {PIOC_IrqHandler},    /* 13 Parallel IO Controller C */
+    {USART0_IrqHandler},  /* 14 USART 0 */
+    {USART1_IrqHandler},  /* 15 USART 1 */
+    {Dummy_Handler},  	/* 16 Reserved */
+    {Dummy_Handler},  	/* 17 Reserved */
+    {MCI_IrqHandler},     /* 18 MCI */
+    {TWI0_IrqHandler},    /* 19 TWI 0 */
+    {TWI1_IrqHandler},    /* 20 TWI 1 */
+    {SPI_IrqHandler},     /* 21 SPI */
+    {SSC_IrqHandler},     /* 22 SSC */
+    {TC0_IrqHandler},     /* 23 Timer Counter 0 */
+    {TC1_IrqHandler},     /* 24 Timer Counter 1 */
+    {TC2_IrqHandler},     /* 25 Timer Counter 2 */
+    {TC3_IrqHandler},     /* 26 Timer Counter 3 */
+    {TC4_IrqHandler},     /* 27 Timer Counter 4 */
+    {TC5_IrqHandler},     /* 28 Timer Counter 5 */
+    {ADC_IrqHandler},     /* 29 ADC controller */
+    {DAC_IrqHandler},     /* 30 DAC controller */
+    {PWM_IrqHandler},     /* 31 PWM */
+    {CRCCU_IrqHandler},   /* 32 CRC Calculation Unit */
+    {ACC_IrqHandler},     /* 33 Analog Comparator */
+    {USBD_IrqHandler},    /* 34 USB Device Port */
+    {Dummy_Handler}   	/* 35 not used */
 };
 
 /* TEMPORARY PATCH FOR SCB */
@@ -118,9 +102,9 @@ extern int __low_level_init( void )
 
     SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
 
-    if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
+    if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < (uint32_t)IRAM_ADDR+(uint32_t)IRAM_SIZE) )
     {
-	    SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
+	    SCB->VTOR |= (uint32_t)(1 << SCB_VTOR_TBLBASE_Pos) ;
     }
 
     return 1 ; /*  if return 0, the data sections will not be initialized. */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c
index 8edbcbeb2..afbff7d08 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.c
@@ -3,6 +3,8 @@
  * \brief Provides the low-level initialization functions that called
  * on chip startup.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,8 +15,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "sam3.h"
 
 /* @cond 0 */
@@ -51,33 +51,33 @@ uint32_t SystemCoreClock = EFRC_OSC;
 extern void SystemInit( void )
 {
     /* Set 3 FWS for Embedded Flash Access */
-    EFC->EEFC_FMR = EEFC_FMR_FWS(3);
+    EFC->EEFC_FMR = EEFC_FMR_FWS(3U);
 
     /* Initialize main oscillator */
     if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
     {
-        PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
-        while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
+        PMC->CKGR_MOR = CKGR_MOR_KEY(0x37U) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+        while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {}
     }
 
     /* Switch to 3-20MHz Xtal oscillator */
-    PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+    PMC->CKGR_MOR = CKGR_MOR_KEY(0x37U) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
 
-    while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
+    while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {}
     PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
-    while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+    while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
 
     /* Initialize PLLA */
     PMC->CKGR_PLLAR = BOARD_PLLAR;
-    while (!(PMC->PMC_SR & PMC_SR_LOCKA));
+    while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {}
 
     /* Switch to main clock */
     PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
-    while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+    while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
 
     /* Switch to PLLA */
     PMC->PMC_MCKR = BOARD_MCKR ;
-    while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
+    while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {}
 
 	SystemCoreClock = MCK_HZ;
 }
@@ -85,16 +85,19 @@ extern void SystemInit( void )
 extern void SystemCoreClockUpdate( void )
 {
 	/* Determine clock frequency according to clock register values */
-	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
+	switch (PMC->PMC_MCKR & (uint32_t)PMC_MCKR_CSS_Msk) {
 	case PMC_MCKR_CSS_SLOW_CLK:                             /* Slow clock */
-		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
+	  if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
 			SystemCoreClock = OSC32_CLK;
-		else
+	  }
+	  else {
 			SystemCoreClock = ERC_OSC;
+	  }
 		break;
 	case PMC_MCKR_CSS_MAIN_CLK:                             /* Main clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+	  if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+	  }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -102,20 +105,21 @@ extern void SystemCoreClockUpdate( void )
 			case CKGR_MOR_MOSCRCF_4MHz:
 				break;
 			case CKGR_MOR_MOSCRCF_8MHz:
-				SystemCoreClock *= 2;
+				SystemCoreClock *= 2U;
 				break;
 			case CKGR_MOR_MOSCRCF_12MHz:
-				SystemCoreClock *= 3;
+				SystemCoreClock *= 3U;
 				break;
-			case 3:
+			default:
 				break;
 			}
 		}
 		break;
 	case PMC_MCKR_CSS_PLLA_CLK:                             /* PLLA clock */
 	case PMC_MCKR_CSS_PLLB_CLK:                             /* PLLB clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+		}
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -123,30 +127,34 @@ extern void SystemCoreClockUpdate( void )
 			case CKGR_MOR_MOSCRCF_4MHz:
 				break;
 			case CKGR_MOR_MOSCRCF_8MHz:
-				SystemCoreClock *= 2;
+				SystemCoreClock *= 2U;
 				break;
 			case CKGR_MOR_MOSCRCF_12MHz:
-				SystemCoreClock *= 3;
+				SystemCoreClock *= 3U;
 				break;
-			case 3:
+			default:
 				break;
 			}
 		}
-		if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
-			SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FF) + 1);
-			SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FF));
+		if ((uint32_t)(PMC->PMC_MCKR & (uint32_t)PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
+			SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FFU) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FFU));
 		}
 		else {
-			SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_MULB_Pos) & 0x7FF) + 1);
-			SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_DIVB_Pos) & 0x0FF));
+			SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_MULB_Pos) & 0x7FFU) + 1U);
+			SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_DIVB_Pos) & 0x0FFU));
 		}
 		break;
+	default:
+		break;
 	}
 
-	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
-		SystemCoreClock /= 3;
-	else
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
+		SystemCoreClock /= 3U;
+	}
+	else {
 		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+	}
 }
 
 /* @cond 0 */
@@ -157,4 +165,3 @@ extern void SystemCoreClockUpdate( void )
 /**INDENT-ON**/
 /* @endcond */
 
-
diff --git a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h
index 35440b3be..0eebb12d9 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s/source/templates/system_sam3s.h
@@ -3,6 +3,8 @@
  * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
  *           for SAM3 devices.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,10 +15,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef __SYSTEM_SAM3S_
-#define __SYSTEM_SAM3S_
+#ifndef SYSTEM_SAM3S_H_INCLUDED
+#define SYSTEM_SAM3S_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -50,4 +50,5 @@ extern void SystemCoreClockUpdate(void);
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* __SYSTEM_SAM3S_ */
+#endif /* SYSTEM_SAM3S_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/component/crccu.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/component/crccu.h
index c0fd441df..3b2f021d7 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/component/crccu.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/component/crccu.h
@@ -56,9 +56,9 @@ typedef struct {
 #define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */
 #define CRCCU_MR_PTYPE_Pos 2
 #define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */
-#define   CRCCU_MR_PTYPE_CCIT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
+#define   CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */
 #define   CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */
-#define   CRCCU_MR_PTYPE_CCIT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
+#define   CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */
 #define CRCCU_MR_DIVIDER_Pos 4
 #define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */
 #define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos)))
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/component/rtt.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/component/rtt.h
index e6200766b..d8c8f5d21 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/component/rtt.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/component/rtt.h
@@ -25,6 +25,8 @@ typedef struct {
 #define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */
 #define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */
 #define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */
+#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */
+#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */
 /* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */
 #define RTT_AR_ALMV_Pos 0
 #define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8a.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8a.h
index fb1ffb1be..515b038ea 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8a.h
@@ -78,9 +78,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S8A does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S8A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S8A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -289,17 +290,17 @@ typedef enum IRQn
 
 #define IFLASH_SIZE             0x80000
 #define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 32768
+#define IFLASH_LOCK_REGION_SIZE 16384
 #define IFLASH_NB_OF_PAGES      2048
 #define IFLASH_NB_OF_LOCK_BITS  16
 #define IRAM_SIZE               0x10000
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #if defined IFLASH0_SIZE
 #define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
 #endif
-#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8b.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8b.h
index b93ef955b..bd230fc49 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8b.h
@@ -80,9 +80,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S8B does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S8B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -304,17 +305,17 @@ typedef enum IRQn
 
 #define IFLASH_SIZE             0x80000
 #define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 32768
+#define IFLASH_LOCK_REGION_SIZE 16384
 #define IFLASH_NB_OF_PAGES      2048
 #define IFLASH_NB_OF_LOCK_BITS  16
 #define IRAM_SIZE               0x10000
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #if defined IFLASH0_SIZE
 #define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
 #endif
-#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8c.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8c.h
index 6ec174d1c..623942f59 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3s8c.h
@@ -86,9 +86,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3S8C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3S8C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3S8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3S8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3S8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -331,17 +332,17 @@ typedef enum IRQn
 
 #define IFLASH_SIZE             0x80000
 #define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 32768
+#define IFLASH_LOCK_REGION_SIZE 16384
 #define IFLASH_NB_OF_PAGES      2048
 #define IFLASH_NB_OF_LOCK_BITS  16
 #define IRAM_SIZE               0x10000
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #if defined IFLASH0_SIZE
 #define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
 #endif
-#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8a.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8a.h
index a239c211e..937e96056 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8a.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8a.h
@@ -78,9 +78,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3SD8A does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3SD8A uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3SD8A core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8A does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8A uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -289,12 +290,12 @@ typedef enum IRQn
 
 #define IFLASH0_SIZE             0x40000
 #define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 32768
+#define IFLASH0_LOCK_REGION_SIZE 16384
 #define IFLASH0_NB_OF_PAGES      1024
 #define IFLASH0_NB_OF_LOCK_BITS  16
 #define IFLASH1_SIZE             0x40000
 #define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 32768
+#define IFLASH1_LOCK_REGION_SIZE 16384
 #define IFLASH1_NB_OF_PAGES      1024
 #define IFLASH1_NB_OF_LOCK_BITS  16
 #define IRAM_SIZE                0x10000
@@ -302,10 +303,10 @@ typedef enum IRQn
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #if defined IFLASH0_SIZE
 #define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
 #endif
-#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8b.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8b.h
index 1d543a33b..9d6fd08a2 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8b.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8b.h
@@ -80,9 +80,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3SD8B does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3SD8B uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3SD8B core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8B does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8B uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -304,12 +305,12 @@ typedef enum IRQn
 
 #define IFLASH0_SIZE             0x40000
 #define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 32768
+#define IFLASH0_LOCK_REGION_SIZE 16384
 #define IFLASH0_NB_OF_PAGES      1024
 #define IFLASH0_NB_OF_LOCK_BITS  16
 #define IFLASH1_SIZE             0x40000
 #define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 32768
+#define IFLASH1_LOCK_REGION_SIZE 16384
 #define IFLASH1_NB_OF_PAGES      1024
 #define IFLASH1_NB_OF_LOCK_BITS  16
 #define IRAM_SIZE                0x10000
@@ -317,10 +318,10 @@ typedef enum IRQn
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #if defined IFLASH0_SIZE
 #define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
 #endif
-#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8c.h b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8c.h
index 8864df3db..aa976f99a 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/include/sam3sd8c.h
@@ -86,9 +86,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3SD8C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3SD8C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3SD8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3SD8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3SD8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -331,12 +332,12 @@ typedef enum IRQn
 
 #define IFLASH0_SIZE             0x40000
 #define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 32768
+#define IFLASH0_LOCK_REGION_SIZE 16384
 #define IFLASH0_NB_OF_PAGES      1024
 #define IFLASH0_NB_OF_LOCK_BITS  16
 #define IFLASH1_SIZE             0x40000
 #define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 32768
+#define IFLASH1_LOCK_REGION_SIZE 16384
 #define IFLASH1_NB_OF_PAGES      1024
 #define IFLASH1_NB_OF_LOCK_BITS  16
 #define IRAM_SIZE                0x10000
@@ -344,10 +345,10 @@ typedef enum IRQn
 
 #define IFLASH_ADDR  (0x00400000u) /**< Internal Flash base address */
 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */
+#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #if defined IFLASH0_SIZE
 #define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */
 #endif
-#define IROM_ADDR    (0x00800000u) /**< Internal ROM base address */
 #define IRAM_ADDR    (0x20000000u) /**< Internal RAM base address */
 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */
 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.c
index 61c21ce95..3443984fd 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.c
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \note
@@ -17,8 +19,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "exceptions.h"
 
 /* @cond 0 */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.h
index f08330341..dab91aa02 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.h
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the interface for default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \author               Atmel Corporation: http://www.atmel.com \n
@@ -12,10 +14,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef _EXCEPTIONS_
-#define _EXCEPTIONS_
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -85,4 +85,5 @@ extern void WDT_IrqHandler( void ) ;
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* _EXCEPTIONS_ */
+#endif /* EXCEPTIONS_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c
index c28c45c1c..cf361e40a 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3S8/SAM3SD.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           ARMGCC
@@ -10,20 +12,10 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3s8.h"
 #include "system_sam3sd8.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
 /* Stack Configuration */
 #define STACK_SIZE       0x900     /** Stack size (in DWords) */
 __attribute__ ((aligned(8),section(".stack")))
@@ -38,27 +30,18 @@ extern uint32_t _erelocate;
 extern uint32_t _szero;
 extern uint32_t _ezero;
 
-
-/*----------------------------------------------------------------------------
- *        ProtoTypes
- *----------------------------------------------------------------------------*/
-
 /** \cond DOXYGEN_SHOULD_SKIP_THIS */
 extern int main( void ) ;
 /** \endcond */
-void ResetException( void ) ;
 extern void __libc_init_array( void ) ;
 
-/*----------------------------------------------------------------------------
- *         Exception Table
- *----------------------------------------------------------------------------*/
-
+/* Exception Table */
 __attribute__((section(".vectors")))
 IntFunc exception_table[] = {
 
     /* Configure Initial Stack Pointer, using linker-generated symbols */
     (IntFunc)(&pdwStack[STACK_SIZE-1]),
-    ResetException,
+    Reset_Handler,
 
     NMI_Handler,
     HardFault_Handler,
@@ -119,7 +102,7 @@ IntFunc exception_table[] = {
  * \brief This is the code that gets called on processor reset.
  * To initialize the device, and call the main() routine.
  */
-void ResetException( void )
+void Reset_Handler( void )
 {
     uint32_t *pSrc, *pDest ;
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/iar/startup_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/iar/startup_sam3sd8.c
index cbcaae7f7..c2ba4eb54 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/iar/startup_sam3sd8.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/iar/startup_sam3sd8.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3S8/SAM3SD.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           IAR EWARM
@@ -10,39 +12,20 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3s8.h"
 #include "system_sam3sd8.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
-/*------------------------------------------------------------------------------
- *         Types
- *------------------------------------------------------------------------------*/
 typedef void( *intfunc )( void );
 typedef union { intfunc __fun; void * __ptr; } intvec_elem;
 
-/*------------------------------------------------------------------------------
- *         Prototypes
- *------------------------------------------------------------------------------*/
 extern void __iar_program_start( void ) ;
 extern int __low_level_init( void ) ;
 
-/*------------------------------------------------------------------------------
- *         Exception Table
- *------------------------------------------------------------------------------*/
+/* Exception Table */
 #pragma language=extended
 #pragma segment="CSTACK"
 
-
 /*  The name "__vector_table" has special meaning for C-SPY: */
 /*  it is where the SP start value is found, and the NVIC vector */
 /*  table register (VTOR) is initialized to this address if != 0. */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.c b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.c
index 5c8b31bcc..bf25ee6c5 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.c
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.c
@@ -3,6 +3,8 @@
  * \brief Provides the low-level initialization functions that called
  * on chip startup.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,11 +15,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "system_sam3sd8.h"
 #include "sam3s8.h"
-#include "sam3s_ek2.h"
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -89,14 +88,17 @@ extern void SystemCoreClockUpdate( void )
 	/* Determine clock frequency according to clock register values */
 	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
 	case PMC_MCKR_CSS_SLOW_CLK:                             /* Slow clock */
-		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
 			SystemCoreClock = OSC32_CLK;
-		else
+        }
+		else {
 			SystemCoreClock = ERC_OSC;
+        }
 		break;
 	case PMC_MCKR_CSS_MAIN_CLK:                             /* Main clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -116,8 +118,9 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	case PMC_MCKR_CSS_PLLA_CLK:                             /* PLLA clock */
 	case PMC_MCKR_CSS_PLLB_CLK:                             /* PLLB clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -145,10 +148,12 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	}
 
-	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
 		SystemCoreClock /= 3;
-	else
+    }
+	else {
 		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+    }
 }
 
 /* @cond 0 */
diff --git a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.h b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.h
index b7746d401..5c0b00ceb 100644
--- a/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.h
+++ b/hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.h
@@ -3,6 +3,8 @@
  * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
  *           for SAM3 devices.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,10 +15,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef __SYSTEM_SAM3SD8_
-#define __SYSTEM_SAM3SD8_
+#ifndef SYSTEM_SAM3SD8_H_INCLUDED
+#define SYSTEM_SAM3SD8_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -50,4 +50,5 @@ extern void SystemCoreClockUpdate(void);
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* __SYSTEM_SAM3SD8_ */
+#endif /* SYSTEM_SAM3SD8_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/component/dmac.h b/hardware/sam/system/libsam/cmsis/sam3u/include/component/dmac.h
index 1a363d340..1ed2db83c 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/component/dmac.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/component/dmac.h
@@ -18,9 +18,7 @@ typedef struct {
   RwReg       DMAC_CTRLA;     /**< \brief (DmacCh_num Offset: 0xC) DMAC Channel Control A Register */
   RwReg       DMAC_CTRLB;     /**< \brief (DmacCh_num Offset: 0x10) DMAC Channel Control B Register */
   RwReg       DMAC_CFG;       /**< \brief (DmacCh_num Offset: 0x14) DMAC Channel Configuration Register */
-  RwReg       DMAC_SPIP;      /**< \brief (DmacCh_num Offset: 0x18) DMAC Channel Source Picture in Picture Configuration Register */
-  RwReg       DMAC_DPIP;      /**< \brief (DmacCh_num Offset: 0x1C) DMAC Channel Destination Picture in Picture Configuration Register */
-  RoReg       Reserved1[2];
+  RoReg       Reserved1[4];
 } DmacCh_num;
 /** \brief Dmac hardware registers */
 #define DMACCH_NUM_NUMBER 4
@@ -30,7 +28,7 @@ typedef struct {
   RwReg       DMAC_SREQ;      /**< \brief (Dmac Offset: 0x008) DMAC Software Single Request Register */
   RwReg       DMAC_CREQ;      /**< \brief (Dmac Offset: 0x00C) DMAC Software Chunk Transfer Request Register */
   RwReg       DMAC_LAST;      /**< \brief (Dmac Offset: 0x010) DMAC Software Last Transfer Flag Register */
-  RwReg       DMAC_SYNC;      /**< \brief (Dmac Offset: 0x014) DMAC Request Synchronization Register */
+  RoReg       Reserved1[1];
   WoReg       DMAC_EBCIER;    /**< \brief (Dmac Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
   WoReg       DMAC_EBCIDR;    /**< \brief (Dmac Offset: 0x01C) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
   RoReg       DMAC_EBCIMR;    /**< \brief (Dmac Offset: 0x020) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
@@ -38,12 +36,11 @@ typedef struct {
   WoReg       DMAC_CHER;      /**< \brief (Dmac Offset: 0x028) DMAC Channel Handler Enable Register */
   WoReg       DMAC_CHDR;      /**< \brief (Dmac Offset: 0x02C) DMAC Channel Handler Disable Register */
   RoReg       DMAC_CHSR;      /**< \brief (Dmac Offset: 0x030) DMAC Channel Handler Status Register */
-  RoReg       Reserved1[2];
+  RoReg       Reserved2[2];
   DmacCh_num  DMAC_CH_NUM[DMACCH_NUM_NUMBER]; /**< \brief (Dmac Offset: 0x3C) ch_num = 0 .. 3 */
 } Dmac;
 #endif /* __ASSEMBLY__ */
 /* -------- DMAC_GCFG : (DMAC Offset: 0x000) DMAC Global Configuration Register -------- */
-#define DMAC_GCFG_IF0_BIGEND (0x1u << 0) /**< \brief (DMAC_GCFG)  */
 #define DMAC_GCFG_ARB_CFG (0x1u << 4) /**< \brief (DMAC_GCFG)  */
 /* -------- DMAC_EN : (DMAC Offset: 0x004) DMAC Enable Register -------- */
 #define DMAC_EN_ENABLE (0x1u << 0) /**< \brief (DMAC_EN)  */
@@ -52,8 +49,6 @@ typedef struct {
 #define DMAC_SREQ_DSREQ0 (0x1u << 1) /**< \brief (DMAC_SREQ)  */
 #define DMAC_SREQ_SSREQ1 (0x1u << 2) /**< \brief (DMAC_SREQ)  */
 #define DMAC_SREQ_DSREQ1 (0x1u << 3) /**< \brief (DMAC_SREQ)  */
-#define DMAC_SREQ_SSREQ2 (0x1u << 4) /**< \brief (DMAC_SREQ)  */
-#define DMAC_SREQ_DSREQ2 (0x1u << 5) /**< \brief (DMAC_SREQ)  */
 #define DMAC_SREQ_SSREQ3 (0x1u << 6) /**< \brief (DMAC_SREQ)  */
 #define DMAC_SREQ_DSREQ3 (0x1u << 7) /**< \brief (DMAC_SREQ)  */
 /* -------- DMAC_CREQ : (DMAC Offset: 0x00C) DMAC Software Chunk Transfer Request Register -------- */
@@ -61,8 +56,6 @@ typedef struct {
 #define DMAC_CREQ_DCREQ0 (0x1u << 1) /**< \brief (DMAC_CREQ)  */
 #define DMAC_CREQ_SCREQ1 (0x1u << 2) /**< \brief (DMAC_CREQ)  */
 #define DMAC_CREQ_DCREQ1 (0x1u << 3) /**< \brief (DMAC_CREQ)  */
-#define DMAC_CREQ_SCREQ2 (0x1u << 4) /**< \brief (DMAC_CREQ)  */
-#define DMAC_CREQ_DCREQ2 (0x1u << 5) /**< \brief (DMAC_CREQ)  */
 #define DMAC_CREQ_SCREQ3 (0x1u << 6) /**< \brief (DMAC_CREQ)  */
 #define DMAC_CREQ_DCREQ3 (0x1u << 7) /**< \brief (DMAC_CREQ)  */
 /* -------- DMAC_LAST : (DMAC Offset: 0x010) DMAC Software Last Transfer Flag Register -------- */
@@ -74,15 +67,6 @@ typedef struct {
 #define DMAC_LAST_DLAST2 (0x1u << 5) /**< \brief (DMAC_LAST)  */
 #define DMAC_LAST_SLAST3 (0x1u << 6) /**< \brief (DMAC_LAST)  */
 #define DMAC_LAST_DLAST3 (0x1u << 7) /**< \brief (DMAC_LAST)  */
-/* -------- DMAC_SYNC : (DMAC Offset: 0x014) DMAC Request Synchronization Register -------- */
-#define DMAC_SYNC_SYR0 (0x1u << 0) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR1 (0x1u << 1) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR2 (0x1u << 2) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR3 (0x1u << 3) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR4 (0x1u << 4) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR5 (0x1u << 5) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR6 (0x1u << 6) /**< \brief (DMAC_SYNC)  */
-#define DMAC_SYNC_SYR7 (0x1u << 7) /**< \brief (DMAC_SYNC)  */
 /* -------- DMAC_EBCIER : (DMAC Offset: 0x018) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. -------- */
 #define DMAC_EBCIER_BTC0 (0x1u << 0) /**< \brief (DMAC_EBCIER)  */
 #define DMAC_EBCIER_BTC1 (0x1u << 1) /**< \brief (DMAC_EBCIER)  */
@@ -183,22 +167,15 @@ typedef struct {
 #define DMAC_DADDR_DADDRx_Msk (0xffffffffu << DMAC_DADDR_DADDRx_Pos) /**< \brief (DMAC_DADDR)  */
 #define DMAC_DADDR_DADDRx(value) ((DMAC_DADDR_DADDRx_Msk & ((value) << DMAC_DADDR_DADDRx_Pos)))
 /* -------- DMAC_DSCR : (DMAC Offset: N/A) DMAC Channel Descriptor Address Register -------- */
-#define DMAC_DSCR_DSCRx_IF_Pos 0
-#define DMAC_DSCR_DSCRx_IF_Msk (0x3u << DMAC_DSCR_DSCRx_IF_Pos) /**< \brief (DMAC_DSCR)  */
-#define DMAC_DSCR_DSCRx_IF(value) ((DMAC_DSCR_DSCRx_IF_Msk & ((value) << DMAC_DSCR_DSCRx_IF_Pos)))
 #define DMAC_DSCR_DSCRx_Pos 2
 #define DMAC_DSCR_DSCRx_Msk (0x3fffffffu << DMAC_DSCR_DSCRx_Pos) /**< \brief (DMAC_DSCR)  */
 #define DMAC_DSCR_DSCRx(value) ((DMAC_DSCR_DSCRx_Msk & ((value) << DMAC_DSCR_DSCRx_Pos)))
 /* -------- DMAC_CTRLA : (DMAC Offset: N/A) DMAC Channel Control A Register -------- */
 #define DMAC_CTRLA_BTSIZE_Pos 0
-#define DMAC_CTRLA_BTSIZE_Msk (0xffffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_BTSIZE_Msk (0xfffu << DMAC_CTRLA_BTSIZE_Pos) /**< \brief (DMAC_CTRLA)  */
 #define DMAC_CTRLA_BTSIZE(value) ((DMAC_CTRLA_BTSIZE_Msk & ((value) << DMAC_CTRLA_BTSIZE_Pos)))
-#define DMAC_CTRLA_SCSIZE_Pos 16
-#define DMAC_CTRLA_SCSIZE_Msk (0x7u << DMAC_CTRLA_SCSIZE_Pos) /**< \brief (DMAC_CTRLA)  */
-#define DMAC_CTRLA_SCSIZE(value) ((DMAC_CTRLA_SCSIZE_Msk & ((value) << DMAC_CTRLA_SCSIZE_Pos)))
-#define DMAC_CTRLA_DCSIZE_Pos 20
-#define DMAC_CTRLA_DCSIZE_Msk (0x7u << DMAC_CTRLA_DCSIZE_Pos) /**< \brief (DMAC_CTRLA)  */
-#define DMAC_CTRLA_DCSIZE(value) ((DMAC_CTRLA_DCSIZE_Msk & ((value) << DMAC_CTRLA_DCSIZE_Pos)))
+#define DMAC_CTRLA_SCSIZE (0x1u << 16) /**< \brief (DMAC_CTRLA)  */
+#define DMAC_CTRLA_DCSIZE (0x1u << 20) /**< \brief (DMAC_CTRLA)  */
 #define DMAC_CTRLA_SRC_WIDTH_Pos 24
 #define DMAC_CTRLA_SRC_WIDTH_Msk (0x3u << DMAC_CTRLA_SRC_WIDTH_Pos) /**< \brief (DMAC_CTRLA)  */
 #define DMAC_CTRLA_SRC_WIDTH(value) ((DMAC_CTRLA_SRC_WIDTH_Msk & ((value) << DMAC_CTRLA_SRC_WIDTH_Pos)))
@@ -207,18 +184,10 @@ typedef struct {
 #define DMAC_CTRLA_DST_WIDTH(value) ((DMAC_CTRLA_DST_WIDTH_Msk & ((value) << DMAC_CTRLA_DST_WIDTH_Pos)))
 #define DMAC_CTRLA_DONE (0x1u << 31) /**< \brief (DMAC_CTRLA)  */
 /* -------- DMAC_CTRLB : (DMAC Offset: N/A) DMAC Channel Control B Register -------- */
-#define DMAC_CTRLB_SIF_Pos 0
-#define DMAC_CTRLB_SIF_Msk (0x3u << DMAC_CTRLB_SIF_Pos) /**< \brief (DMAC_CTRLB) Source Interface Selection Field */
-#define DMAC_CTRLB_SIF(value) ((DMAC_CTRLB_SIF_Msk & ((value) << DMAC_CTRLB_SIF_Pos)))
-#define DMAC_CTRLB_DIF_Pos 4
-#define DMAC_CTRLB_DIF_Msk (0x3u << DMAC_CTRLB_DIF_Pos) /**< \brief (DMAC_CTRLB) Destination Interface Selection Field */
-#define DMAC_CTRLB_DIF(value) ((DMAC_CTRLB_DIF_Msk & ((value) << DMAC_CTRLB_DIF_Pos)))
-#define DMAC_CTRLB_SRC_PIP (0x1u << 8) /**< \brief (DMAC_CTRLB)  */
-#define DMAC_CTRLB_DST_PIP (0x1u << 12) /**< \brief (DMAC_CTRLB)  */
 #define DMAC_CTRLB_SRC_DSCR (0x1u << 16) /**< \brief (DMAC_CTRLB)  */
 #define DMAC_CTRLB_DST_DSCR (0x1u << 20) /**< \brief (DMAC_CTRLB)  */
 #define DMAC_CTRLB_FC_Pos 21
-#define DMAC_CTRLB_FC_Msk (0x7u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB)  */
+#define DMAC_CTRLB_FC_Msk (0x3u << DMAC_CTRLB_FC_Pos) /**< \brief (DMAC_CTRLB)  */
 #define DMAC_CTRLB_FC(value) ((DMAC_CTRLB_FC_Msk & ((value) << DMAC_CTRLB_FC_Pos)))
 #define DMAC_CTRLB_SRC_INCR_Pos 24
 #define DMAC_CTRLB_SRC_INCR_Msk (0x3u << DMAC_CTRLB_SRC_INCR_Pos) /**< \brief (DMAC_CTRLB)  */
@@ -227,7 +196,6 @@ typedef struct {
 #define DMAC_CTRLB_DST_INCR_Msk (0x3u << DMAC_CTRLB_DST_INCR_Pos) /**< \brief (DMAC_CTRLB)  */
 #define DMAC_CTRLB_DST_INCR(value) ((DMAC_CTRLB_DST_INCR_Msk & ((value) << DMAC_CTRLB_DST_INCR_Pos)))
 #define DMAC_CTRLB_IEN (0x1u << 30) /**< \brief (DMAC_CTRLB)  */
-#define DMAC_CTRLB_AUTO (0x1u << 31) /**< \brief (DMAC_CTRLB)  */
 /* -------- DMAC_CFG : (DMAC Offset: N/A) DMAC Channel Configuration Register -------- */
 #define DMAC_CFG_SRC_PER_Pos 0
 #define DMAC_CFG_SRC_PER_Msk (0xfu << DMAC_CFG_SRC_PER_Pos) /**< \brief (DMAC_CFG)  */
@@ -235,9 +203,7 @@ typedef struct {
 #define DMAC_CFG_DST_PER_Pos 4
 #define DMAC_CFG_DST_PER_Msk (0xfu << DMAC_CFG_DST_PER_Pos) /**< \brief (DMAC_CFG)  */
 #define DMAC_CFG_DST_PER(value) ((DMAC_CFG_DST_PER_Msk & ((value) << DMAC_CFG_DST_PER_Pos)))
-#define DMAC_CFG_SRC_REP (0x1u << 8) /**< \brief (DMAC_CFG)  */
 #define DMAC_CFG_SRC_H2SEL (0x1u << 9) /**< \brief (DMAC_CFG)  */
-#define DMAC_CFG_DST_REP (0x1u << 12) /**< \brief (DMAC_CFG)  */
 #define DMAC_CFG_DST_H2SEL (0x1u << 13) /**< \brief (DMAC_CFG)  */
 #define DMAC_CFG_SOD (0x1u << 16) /**< \brief (DMAC_CFG)  */
 #define DMAC_CFG_LOCK_IF (0x1u << 20) /**< \brief (DMAC_CFG)  */
@@ -249,20 +215,6 @@ typedef struct {
 #define DMAC_CFG_FIFOCFG_Pos 28
 #define DMAC_CFG_FIFOCFG_Msk (0x3u << DMAC_CFG_FIFOCFG_Pos) /**< \brief (DMAC_CFG)  */
 #define DMAC_CFG_FIFOCFG(value) ((DMAC_CFG_FIFOCFG_Msk & ((value) << DMAC_CFG_FIFOCFG_Pos)))
-/* -------- DMAC_SPIP : (DMAC Offset: N/A) DMAC Channel Source Picture in Picture Configuration Register -------- */
-#define DMAC_SPIP_SPIP_HOLE_Pos 0
-#define DMAC_SPIP_SPIP_HOLE_Msk (0xffffu << DMAC_SPIP_SPIP_HOLE_Pos) /**< \brief (DMAC_SPIP)  */
-#define DMAC_SPIP_SPIP_HOLE(value) ((DMAC_SPIP_SPIP_HOLE_Msk & ((value) << DMAC_SPIP_SPIP_HOLE_Pos)))
-#define DMAC_SPIP_SPIP_BOUNDARY_Pos 16
-#define DMAC_SPIP_SPIP_BOUNDARY_Msk (0x3ffu << DMAC_SPIP_SPIP_BOUNDARY_Pos) /**< \brief (DMAC_SPIP)  */
-#define DMAC_SPIP_SPIP_BOUNDARY(value) ((DMAC_SPIP_SPIP_BOUNDARY_Msk & ((value) << DMAC_SPIP_SPIP_BOUNDARY_Pos)))
-/* -------- DMAC_DPIP : (DMAC Offset: N/A) DMAC Channel Destination Picture in Picture Configuration Register -------- */
-#define DMAC_DPIP_DPIP_HOLE_Pos 0
-#define DMAC_DPIP_DPIP_HOLE_Msk (0xffffu << DMAC_DPIP_DPIP_HOLE_Pos) /**< \brief (DMAC_DPIP)  */
-#define DMAC_DPIP_DPIP_HOLE(value) ((DMAC_DPIP_DPIP_HOLE_Msk & ((value) << DMAC_DPIP_DPIP_HOLE_Pos)))
-#define DMAC_DPIP_DPIP_BOUNDARY_Pos 16
-#define DMAC_DPIP_DPIP_BOUNDARY_Msk (0x3ffu << DMAC_DPIP_DPIP_BOUNDARY_Pos) /**< \brief (DMAC_DPIP)  */
-#define DMAC_DPIP_DPIP_BOUNDARY(value) ((DMAC_DPIP_DPIP_BOUNDARY_Msk & ((value) << DMAC_DPIP_DPIP_BOUNDARY_Pos)))
 
 /*@}*/
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/dmac.h b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/dmac.h
index b912bdef2..02ec7921c 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/instance/dmac.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/instance/dmac.h
@@ -10,7 +10,6 @@
 #define REG_DMAC_SREQ            (0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
 #define REG_DMAC_CREQ            (0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
 #define REG_DMAC_LAST            (0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
-#define REG_DMAC_SYNC            (0x400B0014U) /**< \brief (DMAC) DMAC Request Synchronization Register */
 #define REG_DMAC_EBCIER          (0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
 #define REG_DMAC_EBCIDR          (0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
 #define REG_DMAC_EBCIMR          (0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
@@ -24,39 +23,30 @@
 #define REG_DMAC_CTRLA0          (0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
 #define REG_DMAC_CTRLB0          (0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
 #define REG_DMAC_CFG0            (0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
-#define REG_DMAC_SPIP0           (0x400B0054U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 0) */
-#define REG_DMAC_DPIP0           (0x400B0058U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 0) */
 #define REG_DMAC_SADDR1          (0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
 #define REG_DMAC_DADDR1          (0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
 #define REG_DMAC_DSCR1           (0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
 #define REG_DMAC_CTRLA1          (0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
 #define REG_DMAC_CTRLB1          (0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
 #define REG_DMAC_CFG1            (0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
-#define REG_DMAC_SPIP1           (0x400B007CU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 1) */
-#define REG_DMAC_DPIP1           (0x400B0080U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 1) */
 #define REG_DMAC_SADDR2          (0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
 #define REG_DMAC_DADDR2          (0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
 #define REG_DMAC_DSCR2           (0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
 #define REG_DMAC_CTRLA2          (0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
 #define REG_DMAC_CTRLB2          (0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
 #define REG_DMAC_CFG2            (0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
-#define REG_DMAC_SPIP2           (0x400B00A4U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 2) */
-#define REG_DMAC_DPIP2           (0x400B00A8U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 2) */
 #define REG_DMAC_SADDR3          (0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
 #define REG_DMAC_DADDR3          (0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
 #define REG_DMAC_DSCR3           (0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
 #define REG_DMAC_CTRLA3          (0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
 #define REG_DMAC_CTRLB3          (0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
 #define REG_DMAC_CFG3            (0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
-#define REG_DMAC_SPIP3           (0x400B00CCU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 3) */
-#define REG_DMAC_DPIP3           (0x400B00D0U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 3) */
 #else
 #define REG_DMAC_GCFG   (*(RwReg*)0x400B0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
 #define REG_DMAC_EN     (*(RwReg*)0x400B0004U) /**< \brief (DMAC) DMAC Enable Register */
 #define REG_DMAC_SREQ   (*(RwReg*)0x400B0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
 #define REG_DMAC_CREQ   (*(RwReg*)0x400B000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
 #define REG_DMAC_LAST   (*(RwReg*)0x400B0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
-#define REG_DMAC_SYNC   (*(RwReg*)0x400B0014U) /**< \brief (DMAC) DMAC Request Synchronization Register */
 #define REG_DMAC_EBCIER (*(WoReg*)0x400B0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. */
 #define REG_DMAC_EBCIDR (*(WoReg*)0x400B001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. */
 #define REG_DMAC_EBCIMR (*(RoReg*)0x400B0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. */
@@ -70,32 +60,24 @@
 #define REG_DMAC_CTRLA0 (*(RwReg*)0x400B0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
 #define REG_DMAC_CTRLB0 (*(RwReg*)0x400B004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
 #define REG_DMAC_CFG0   (*(RwReg*)0x400B0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
-#define REG_DMAC_SPIP0  (*(RwReg*)0x400B0054U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 0) */
-#define REG_DMAC_DPIP0  (*(RwReg*)0x400B0058U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 0) */
 #define REG_DMAC_SADDR1 (*(RwReg*)0x400B0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
 #define REG_DMAC_DADDR1 (*(RwReg*)0x400B0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
 #define REG_DMAC_DSCR1  (*(RwReg*)0x400B006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
 #define REG_DMAC_CTRLA1 (*(RwReg*)0x400B0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
 #define REG_DMAC_CTRLB1 (*(RwReg*)0x400B0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
 #define REG_DMAC_CFG1   (*(RwReg*)0x400B0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
-#define REG_DMAC_SPIP1  (*(RwReg*)0x400B007CU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 1) */
-#define REG_DMAC_DPIP1  (*(RwReg*)0x400B0080U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 1) */
 #define REG_DMAC_SADDR2 (*(RwReg*)0x400B008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
 #define REG_DMAC_DADDR2 (*(RwReg*)0x400B0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
 #define REG_DMAC_DSCR2  (*(RwReg*)0x400B0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
 #define REG_DMAC_CTRLA2 (*(RwReg*)0x400B0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
 #define REG_DMAC_CTRLB2 (*(RwReg*)0x400B009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
 #define REG_DMAC_CFG2   (*(RwReg*)0x400B00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
-#define REG_DMAC_SPIP2  (*(RwReg*)0x400B00A4U) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 2) */
-#define REG_DMAC_DPIP2  (*(RwReg*)0x400B00A8U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 2) */
 #define REG_DMAC_SADDR3 (*(RwReg*)0x400B00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
 #define REG_DMAC_DADDR3 (*(RwReg*)0x400B00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
 #define REG_DMAC_DSCR3  (*(RwReg*)0x400B00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
 #define REG_DMAC_CTRLA3 (*(RwReg*)0x400B00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
 #define REG_DMAC_CTRLB3 (*(RwReg*)0x400B00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
 #define REG_DMAC_CFG3   (*(RwReg*)0x400B00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
-#define REG_DMAC_SPIP3  (*(RwReg*)0x400B00CCU) /**< \brief (DMAC) DMAC Channel Source Picture in Picture Configuration Register (ch_num = 3) */
-#define REG_DMAC_DPIP3  (*(RwReg*)0x400B00D0U) /**< \brief (DMAC) DMAC Channel Destination Picture in Picture Configuration Register (ch_num = 3) */
 #endif /* __ASSEMBLY__ */
 
 #endif /* _SAM3U_DMAC_INSTANCE_ */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h
index b19f4ae5a..b51f5c279 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1c.h
@@ -81,9 +81,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3U1C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3U1C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3U1C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U1C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U1C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -299,11 +300,11 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U1C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 8192
-#define IFLASH_NB_OF_PAGES      32
-#define IRAM_SIZE               0x5000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (32u)
+#define IRAM_SIZE               (0x5000u)
 
 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h
index 7bf2138b6..9b9e4e6df 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u1e.h
@@ -83,9 +83,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3U1E does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3U1E uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3U1E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U1E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U1E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -311,11 +312,11 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U1E */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x10000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 8192
-#define IFLASH_NB_OF_PAGES      32
-#define IRAM_SIZE               0x5000
+#define IFLASH_SIZE             (0x10000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (32u)
+#define IRAM_SIZE               (0x5000u)
 
 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h
index ef890fa76..aac0bbf78 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2c.h
@@ -81,9 +81,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3U2C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3U2C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3U2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -299,11 +300,11 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U2C */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 8192
-#define IFLASH_NB_OF_PAGES      64
-#define IRAM_SIZE               0x9000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (64u)
+#define IRAM_SIZE               (0x9000u)
 
 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h
index c8dfb5405..db0f68e6f 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u2e.h
@@ -83,9 +83,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3U2E does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3U2E uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3U2E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U2E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U2E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -311,11 +312,11 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U2E */
 /* ************************************************************************** */
 
-#define IFLASH_SIZE             0x20000
-#define IFLASH_PAGE_SIZE        256
-#define IFLASH_LOCK_REGION_SIZE 8192
-#define IFLASH_NB_OF_PAGES      64
-#define IRAM_SIZE               0x9000
+#define IFLASH_SIZE             (0x20000u)
+#define IFLASH_PAGE_SIZE        (256u)
+#define IFLASH_LOCK_REGION_SIZE (8192u)
+#define IFLASH_NB_OF_PAGES      (64u)
+#define IRAM_SIZE               (0x9000u)
 
 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h
index d5a7449e7..6f45230b6 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4c.h
@@ -81,9 +81,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3U4C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3U4C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3U4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -299,16 +300,16 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U4C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 8192
-#define IFLASH0_NB_OF_PAGES      64
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 8192
-#define IFLASH1_NB_OF_PAGES      64
-#define IRAM_SIZE                0xD000
-#define IFLASH_SIZE              0x40000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (64u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (8192u)
+#define IFLASH1_NB_OF_PAGES      (64u)
+#define IRAM_SIZE                (0xD000u)
+#define IFLASH_SIZE              (0x40000u)
 
 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h
index 2adca5b67..dc0c02726 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/include/sam3u4e.h
@@ -83,9 +83,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3U4E does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3U4E uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3U4E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3U4E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3U4E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -311,16 +312,16 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3U4E */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 8192
-#define IFLASH0_NB_OF_PAGES      64
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 8192
-#define IFLASH1_NB_OF_PAGES      64
-#define IRAM_SIZE                0xD000
-#define IFLASH_SIZE              0x40000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (8192u)
+#define IFLASH0_NB_OF_PAGES      (64u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (8192u)
+#define IFLASH1_NB_OF_PAGES      (64u)
+#define IRAM_SIZE                (0xD000u)
+#define IFLASH_SIZE              (0x40000u)
 
 #define IFLASH0_ADDR   (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c
index 2afa37023..3a13095d7 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.c
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \note
@@ -17,8 +19,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "exceptions.h"
 
 /* @cond 0 */
@@ -136,3 +136,4 @@ void Dummy_Handler( void )
 #endif
 /**INDENT-ON**/
 /* @endcond */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h
index 6aaca348b..33682582f 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/exceptions.h
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the interface for default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \author               Atmel Corporation: http://www.atmel.com \n
@@ -12,10 +14,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef _EXCEPTIONS_
-#define _EXCEPTIONS_
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -83,4 +83,5 @@ extern void UDPHS_IrqHandler( void ) ;
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* _EXCEPTIONS_ */
+#endif /* EXCEPTIONS_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c
index d95e4de79..2f206118e 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/gcc/startup_sam3u.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3U.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           ARMGCC
@@ -10,20 +12,10 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3u.h"
 #include "system_sam3u.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
 /* Stack Configuration */
 #define STACK_SIZE       0x900     /** Stack size (in DWords) */
 __attribute__ ((aligned(8),section(".stack")))
@@ -38,20 +30,12 @@ extern uint32_t _erelocate;
 extern uint32_t _szero;
 extern uint32_t _ezero;
 
-
-/*----------------------------------------------------------------------------
- *        ProtoTypes
- *----------------------------------------------------------------------------*/
-
 /** \cond DOXYGEN_SHOULD_SKIP_THIS */
 extern int main( void ) ;
 /** \endcond */
 extern void __libc_init_array( void ) ;
 
-/*------------------------------------------------------------------------------
- *         Exception Table
- *------------------------------------------------------------------------------*/
-
+/* Exception Table */
 __attribute__((section(".vectors")))
 IntFunc exception_table[] = {
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c
index 84a59eb8e..0b4563cd9 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/iar/startup_sam3u.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3U.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           IAR EWARM
@@ -10,39 +12,20 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "board.h"
 #include "system_sam3u.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- *        Types
- *----------------------------------------------------------------------------*/
 typedef void( *intfunc )( void );
 typedef union { intfunc __fun; void * __ptr; } intvec_elem;
 
-/*------------------------------------------------------------------------------
- *         Prototypes
- *------------------------------------------------------------------------------*/
 extern void __iar_program_start( void ) ;
 extern int __low_level_init( void ) ;
 
-/*----------------------------------------------------------------------------
- *         Exception Table
- *----------------------------------------------------------------------------*/
+/* Exception Table */
 #pragma language=extended
 #pragma segment="CSTACK"
 
-
 /*  The name "__vector_table" has special meaning for C-SPY: */
 /*  it is where the SP start value is found, and the NVIC vector */
 /*  table register (VTOR) is initialized to this address if != 0. */
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c
index 90eb3fee5..bfd86e27d 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.c
@@ -3,6 +3,8 @@
  * \brief Provides the low-level initialization functions that called
  * on chip startup.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,8 +15,7 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
+#include "system_sam3u.h"
 #include "sam3.h"
 
 /* @cond 0 */
@@ -89,14 +90,17 @@ extern void SystemCoreClockUpdate( void )
 	/* Determine clock frequency according to clock register values */
 	switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
 	case PMC_MCKR_CSS_SLOW_CLK:                             /* Slow clock */
-		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
+		if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
 			SystemCoreClock = OSC32_CLK;
-		else
+        }
+		else {
 			SystemCoreClock = ERC_OSC;
+        }
 		break;
 	case PMC_MCKR_CSS_MAIN_CLK:                             /* Main clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -116,8 +120,9 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	case PMC_MCKR_CSS_PLLA_CLK:                             /* PLLA clock */
 	case PMC_MCKR_CSS_UPLL_CLK:                             /* UPLL clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -144,10 +149,12 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	}
 
-	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
 		SystemCoreClock /= 3;
-	else
+    }
+	else {
 		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+    }
 }
 
 /* @cond 0 */
@@ -157,3 +164,4 @@ extern void SystemCoreClockUpdate( void )
 #endif
 /**INDENT-ON**/
 /* @endcond */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h
index 31cbae471..693d43a09 100644
--- a/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h
+++ b/hardware/sam/system/libsam/cmsis/sam3u/source/templates/system_sam3u.h
@@ -3,6 +3,8 @@
  * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
  *           for SAM3 devices.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,10 +15,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef __SYSTEM_SAM3U_
-#define __SYSTEM_SAM3U_
+#ifndef SYSTEM_SAM3U_H_INCLUDED
+#define SYSTEM_SAM3U_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -50,4 +50,5 @@ extern void SystemCoreClockUpdate(void);
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* __SYSTEM_SAM3U_ */
+#endif /* SYSTEM_SAM3U_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a2c.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a2c.h
index e9258e68e..ab100e2dd 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a2c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a2c.h
@@ -86,9 +86,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3A2C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3A2C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3A2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -319,18 +320,18 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3A2C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x10000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      256
-#define IFLASH1_SIZE             0x10000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      256
-#define IRAM0_SIZE               0x4000
-#define IRAM1_SIZE               0x4000
-#define IFLASH_SIZE              0x20000
-#define IRAM_SIZE                0x8000
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IFLASH1_SIZE             (0x10000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define IFLASH_SIZE              (0x20000u)
+#define IRAM_SIZE                (0x8000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a4c.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a4c.h
index 46f66e7a5..98e9327cb 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a4c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a4c.h
@@ -86,9 +86,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3A4C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3A4C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3A4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -319,18 +320,18 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3A4C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      512
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      512
-#define IRAM0_SIZE               0x8000
-#define IRAM1_SIZE               0x8000
-#define IFLASH_SIZE              0x40000
-#define IRAM_SIZE                0x10000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a8c.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a8c.h
index 56bdd0a81..d466bf57a 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a8c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3a8c.h
@@ -86,9 +86,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3A8C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3A8C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3A8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3A8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3A8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -319,18 +320,18 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3A8C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x40000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      1024
-#define IFLASH1_SIZE             0x40000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      1024
-#define IRAM0_SIZE               0x10000
-#define IRAM1_SIZE               0x8000
-#define IFLASH_SIZE              0x80000
-#define IRAM_SIZE                0x18000
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2c.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2c.h
index 5291c8f4d..2c2c7994e 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2c.h
@@ -87,9 +87,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X2C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X2C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X2C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X2C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X2C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -325,18 +326,18 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X2C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x10000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      256
-#define IFLASH1_SIZE             0x10000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      256
-#define IRAM0_SIZE               0x4000
-#define IRAM1_SIZE               0x4000
-#define IFLASH_SIZE              0x20000
-#define IRAM_SIZE                0x8000
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IFLASH1_SIZE             (0x10000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define IFLASH_SIZE              (0x20000u)
+#define IRAM_SIZE                (0x8000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2e.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2e.h
index f96eb10fe..9249ca6c1 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2e.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2e.h
@@ -94,9 +94,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X2E does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X2E uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X2E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X2E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X2E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -357,19 +358,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X2E */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x10000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      256
-#define IFLASH1_SIZE             0x10000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      256
-#define IRAM0_SIZE               0x4000
-#define IRAM1_SIZE               0x4000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x20000
-#define IRAM_SIZE                0x8000
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IFLASH1_SIZE             (0x10000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x20000u)
+#define IRAM_SIZE                (0x8000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2g.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2g.h
index 9c71dd8d7..ce2ea92b9 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2g.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2g.h
@@ -98,9 +98,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X2G does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X2G uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X2G core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X2G does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X2G uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -378,19 +379,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X2G */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x10000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      256
-#define IFLASH1_SIZE             0x10000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      256
-#define IRAM0_SIZE               0x4000
-#define IRAM1_SIZE               0x4000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x20000
-#define IRAM_SIZE                0x8000
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IFLASH1_SIZE             (0x10000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x20000u)
+#define IRAM_SIZE                (0x8000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2h.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2h.h
index cc084b787..ea22bb667 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2h.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x2h.h
@@ -98,9 +98,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X2H does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X2H uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X2H core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X2H does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X2H uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -378,19 +379,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X2H */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x10000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      256
-#define IFLASH1_SIZE             0x10000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      256
-#define IRAM0_SIZE               0x4000
-#define IRAM1_SIZE               0x4000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x20000
-#define IRAM_SIZE                0x8000
+#define IFLASH0_SIZE             (0x10000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (256u)
+#define IFLASH1_SIZE             (0x10000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (256u)
+#define IRAM0_SIZE               (0x4000u)
+#define IRAM1_SIZE               (0x4000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x20000u)
+#define IRAM_SIZE                (0x8000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4c.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4c.h
index e277b87ab..8c021bdcf 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4c.h
@@ -87,9 +87,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X4C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X4C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X4C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -325,18 +326,18 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X4C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      512
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      512
-#define IRAM0_SIZE               0x8000
-#define IRAM1_SIZE               0x8000
-#define IFLASH_SIZE              0x40000
-#define IRAM_SIZE                0x10000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4e.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4e.h
index 0a6a65b29..258c5f267 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4e.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4e.h
@@ -94,9 +94,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X4E does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X4E uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X4E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -357,19 +358,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X4E */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      512
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      512
-#define IRAM0_SIZE               0x8000
-#define IRAM1_SIZE               0x8000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x40000
-#define IRAM_SIZE                0x10000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4g.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4g.h
index 08e560e2c..5882e834d 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4g.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4g.h
@@ -98,9 +98,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X4G does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X4G uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X4G core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4G does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4G uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -378,19 +379,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X4G */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      512
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      512
-#define IRAM0_SIZE               0x8000
-#define IRAM1_SIZE               0x8000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x40000
-#define IRAM_SIZE                0x10000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4h.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4h.h
index 2562adaec..8a84c0f81 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4h.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x4h.h
@@ -98,9 +98,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X4H does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X4H uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X4H core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X4H does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X4H uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -378,19 +379,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X4H */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x20000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      512
-#define IFLASH1_SIZE             0x20000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      512
-#define IRAM0_SIZE               0x8000
-#define IRAM1_SIZE               0x8000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x40000
-#define IRAM_SIZE                0x10000
+#define IFLASH0_SIZE             (0x20000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (512u)
+#define IFLASH1_SIZE             (0x20000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (512u)
+#define IRAM0_SIZE               (0x8000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x40000u)
+#define IRAM_SIZE                (0x10000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8c.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8c.h
index 7ffa0049a..949f3b1bd 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8c.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8c.h
@@ -87,9 +87,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X8C does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X8C uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X8C core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8C does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8C uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -325,18 +326,18 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X8C */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x40000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      1024
-#define IFLASH1_SIZE             0x40000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      1024
-#define IRAM0_SIZE               0x10000
-#define IRAM1_SIZE               0x8000
-#define IFLASH_SIZE              0x80000
-#define IRAM_SIZE                0x18000
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8e.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8e.h
index 96a5b3dd0..aecb05c7e 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8e.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8e.h
@@ -94,9 +94,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X8E does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X8E uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X8E core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8E does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8E uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -357,19 +358,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X8E */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x40000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      1024
-#define IFLASH1_SIZE             0x40000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      1024
-#define IRAM0_SIZE               0x10000
-#define IRAM1_SIZE               0x8000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x80000
-#define IRAM_SIZE                0x18000
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8g.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8g.h
index 5d59bf7b0..7f5575f20 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8g.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8g.h
@@ -98,9 +98,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X8G does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X8G uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X8G core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8G does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8G uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -378,19 +379,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X8G */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x40000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      1024
-#define IFLASH1_SIZE             0x40000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      1024
-#define IRAM0_SIZE               0x10000
-#define IRAM1_SIZE               0x8000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x80000
-#define IRAM_SIZE                0x18000
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8h.h b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8h.h
index f2b15837a..e5ad58d3b 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8h.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/include/sam3x8h.h
@@ -98,9 +98,10 @@ typedef enum IRQn
  * \brief Configuration of the Cortex-M3 Processor and Core Peripherals 
  */
 
-#define __MPU_PRESENT          1 /**< SAM3X8H does provide a MPU */
-#define __NVIC_PRIO_BITS       4 /**< SAM3X8H uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
+#define __CM3_REV              0x0200 /**< SAM3X8H core revision number ([15:8] revision number, [7:0] patch number) */
+#define __MPU_PRESENT          1      /**< SAM3X8H does provide a MPU */
+#define __NVIC_PRIO_BITS       4      /**< SAM3X8H uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
 
 /*
  * \brief CMSIS includes
@@ -378,19 +379,19 @@ typedef enum IRQn
 /*   MEMORY MAPPING DEFINITIONS FOR SAM3X8H */
 /* ************************************************************************** */
 
-#define IFLASH0_SIZE             0x40000
-#define IFLASH0_PAGE_SIZE        256
-#define IFLASH0_LOCK_REGION_SIZE 16384
-#define IFLASH0_NB_OF_PAGES      1024
-#define IFLASH1_SIZE             0x40000
-#define IFLASH1_PAGE_SIZE        256
-#define IFLASH1_LOCK_REGION_SIZE 16384
-#define IFLASH1_NB_OF_PAGES      1024
-#define IRAM0_SIZE               0x10000
-#define IRAM1_SIZE               0x8000
-#define NFCRAM_SIZE              0x1000
-#define IFLASH_SIZE              0x80000
-#define IRAM_SIZE                0x18000
+#define IFLASH0_SIZE             (0x40000u)
+#define IFLASH0_PAGE_SIZE        (256u)
+#define IFLASH0_LOCK_REGION_SIZE (16384u)
+#define IFLASH0_NB_OF_PAGES      (1024u)
+#define IFLASH1_SIZE             (0x40000u)
+#define IFLASH1_PAGE_SIZE        (256u)
+#define IFLASH1_LOCK_REGION_SIZE (16384u)
+#define IFLASH1_NB_OF_PAGES      (1024u)
+#define IRAM0_SIZE               (0x10000u)
+#define IRAM1_SIZE               (0x8000u)
+#define NFCRAM_SIZE              (0x1000u)
+#define IFLASH_SIZE              (0x80000u)
+#define IRAM_SIZE                (0x18000u)
 
 #define IFLASH0_ADDR    (0x00080000u) /**< Internal Flash 0 base address */
 #if defined IFLASH0_SIZE
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.c b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.c
index 78f90563f..f353387c7 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.c
+++ b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.c
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \note
@@ -17,8 +19,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "exceptions.h"
 
 /* @cond 0 */
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.h b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.h
index b73fdd12b..8bb56bca2 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/exceptions.h
@@ -2,9 +2,11 @@
  *
  * \brief This file contains the interface for default exception handlers.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
- * This file provides basic support for Cortex-M processor based 
+ * This file provides basic support for Cortex-M processor based
  * microcontrollers.
  *
  * \author               Atmel Corporation: http://www.atmel.com \n
@@ -12,10 +14,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef _EXCEPTIONS_
-#define _EXCEPTIONS_
+#ifndef EXCEPTIONS_H_INCLUDED
+#define EXCEPTIONS_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -100,4 +100,5 @@ extern void WDT_IrqHandler( void ) ;
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* _EXCEPTIONS_ */
+#endif /* EXCEPTIONS_H_INCLUDED */
+
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/gcc/startup_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/gcc/startup_sam3x.c
index 8797a1809..99e9d1bb1 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/gcc/startup_sam3x.c
+++ b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/gcc/startup_sam3x.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3X.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           ARMGCC
@@ -10,20 +12,10 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3xa.h"
 #include "system_sam3x.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
 /* Stack Configuration */
 #define STACK_SIZE       0x900     /** Stack size (in DWords) */
 __attribute__ ((aligned(8),section(".stack")))
@@ -38,21 +30,13 @@ extern uint32_t _erelocate;
 extern uint32_t _szero;
 extern uint32_t _ezero;
 
-
-/*----------------------------------------------------------------------------
- *        ProtoTypes
- *----------------------------------------------------------------------------*/
-
 /** \cond DOXYGEN_SHOULD_SKIP_THIS */
 extern int main( void ) ;
 /** \endcond */
 void ResetException( void ) ;
 extern void __libc_init_array( void ) ;
 
-/*----------------------------------------------------------------------------
- *         Exception Table
- *----------------------------------------------------------------------------*/
-
+/* Exception Table */
 __attribute__((section(".vectors")))
 IntFunc exception_table[] = {
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/iar/startup_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/iar/startup_sam3x.c
index 24fa83012..45afca25f 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/iar/startup_sam3x.c
+++ b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/iar/startup_sam3x.c
@@ -2,6 +2,8 @@
  *
  * \brief Startup file for SAM3X.
  *
+ * $asf_license$
+ *
  * This file defines common SAM series.
  *
  * - Compiler:           IAR EWARM
@@ -10,35 +12,17 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-/*----------------------------------------------------------------------------
- *        Headers
- *----------------------------------------------------------------------------*/
-
 #include "exceptions.h"
 #include "sam3xa.h"
 #include "system_sam3x.h"
 
-/*----------------------------------------------------------------------------
- *        Exported variables
- *----------------------------------------------------------------------------*/
-
-/*------------------------------------------------------------------------------
- *         Types
- *------------------------------------------------------------------------------*/
 typedef void( *intfunc )( void );
 typedef union { intfunc __fun; void * __ptr; } intvec_elem;
 
-/*------------------------------------------------------------------------------
- *         Prototypes
- *------------------------------------------------------------------------------*/
 extern void __iar_program_start( void ) ;
 extern int __low_level_init( void ) ;
 
-/*------------------------------------------------------------------------------
- *         Exception Table
- *------------------------------------------------------------------------------*/
+/* Exception Table */
 #pragma language=extended
 #pragma segment="CSTACK"
 
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.c b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.c
index 6a440793c..458e86197 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.c
+++ b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.c
@@ -3,6 +3,8 @@
  * \brief Provides the low-level initialization functions that called
  * on chip startup.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,8 +15,6 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
 #include "system_sam3x.h"
 #include "sam3xa.h"
 
@@ -117,8 +117,9 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	case PMC_MCKR_CSS_PLLA_CLK:                             /* PLLA clock */
 	case PMC_MCKR_CSS_UPLL_CLK:                             /* UPLL clock */
-		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
+		if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
 			SystemCoreClock = MAINCK_XTAL_HZ;
+        }
 		else {
 			SystemCoreClock = EFRC_OSC;
 
@@ -145,10 +146,12 @@ extern void SystemCoreClockUpdate( void )
 		break;
 	}
 
-	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
+	if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
 		SystemCoreClock /= 3;
-	else
+    }
+	else {
 		SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
+    }
 }
 
 /* @cond 0 */
diff --git a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.h b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.h
index c487529cb..9cf0e2526 100644
--- a/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.h
+++ b/hardware/sam/system/libsam/cmsis/sam3x/source/templates/system_sam3x.h
@@ -3,6 +3,8 @@
  * \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
  *           for SAM3 devices.
  *
+ * $asf_license$
+ *
  * \par Purpose
  *
  * This file provides basic support for Cortex-M processor based
@@ -13,10 +15,8 @@
  *
  ******************************************************************************/
 
-/* $asf_license$ */
-
-#ifndef __SYSTEM_SAM3X_
-#define __SYSTEM_SAM3X_
+#ifndef SYSTEM_SAM3X_H_INCLUDED
+#define SYSTEM_SAM3X_H_INCLUDED
 
 /* @cond 0 */
 /**INDENT-OFF**/
@@ -50,4 +50,5 @@ extern void SystemCoreClockUpdate(void);
 /**INDENT-ON**/
 /* @endcond */
 
-#endif /* __SYSTEM_SAM3X_ */
+#endif /* SYSTEM_SAM3X_H_INCLUDED */
+
diff --git a/hardware/sam/variants/arduino_due/variant.cpp b/hardware/sam/variants/arduino_due/variant.cpp
index 5ec853d38..923cd48fa 100644
--- a/hardware/sam/variants/arduino_due/variant.cpp
+++ b/hardware/sam/variants/arduino_due/variant.cpp
@@ -35,117 +35,117 @@
 extern const PinDescription g_APinDescription[]=
 {
   // LEDS, 0..2
-  { PIOC, PIO_PC21, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // LED AMBER PIN 13
-  { PIOC, PIO_PC14, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // LED AMBER RXL
-  { PIOC, PIO_PC19, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // LED AMBER TXL
+  { PIOC, PIO_PC21, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // LED AMBER PIN 13
+  { PIOC, PIO_PC14, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // LED AMBER RXL
+  { PIOC, PIO_PC19, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // LED AMBER TXL
 
   // UART (Serial), 3..5
-  { PIOA, PIO_PA11A_URXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // URXD
-  { PIOA, PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // UTXD
-  { PIOA, PIO_PA11A_URXD|PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All UART pins
+  { PIOA, PIO_PA11A_URXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // URXD
+  { PIOA, PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // UTXD
+  { PIOA, PIO_PA11A_URXD|PIO_PA12A_UTXD, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), 0 }, // All UART pins
 
   // USART0 (Serial2), 6..8
-  { PIOA, PIO_PA19A_RXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RXD0
-  { PIOA, PIO_PA18A_TXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TXD0
-  { PIOA, PIO_PA19A_RXD0|PIO_PA18A_TXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All USART0 pins
+  { PIOA, PIO_PA19A_RXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // RXD0
+  { PIOA, PIO_PA18A_TXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TXD0
+  { PIOA, PIO_PA19A_RXD0|PIO_PA18A_TXD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), 0 }, // All USART0 pins
 
   // USART1 (Serial3), 9..11
-  { PIOA, PIO_PA21A_RXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RXD1
-  { PIOA, PIO_PA20A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TXD1
-  { PIOA, PIO_PA21A_RXD1|PIO_PA20A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All USART1 pins
+  { PIOA, PIO_PA21A_RXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // RXD1
+  { PIOA, PIO_PA20A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TXD1
+  { PIOA, PIO_PA21A_RXD1|PIO_PA20A_TXD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), 0 }, // All USART1 pins
 
   // USART2 (Serial4), 12..14
-  { PIOA, PIO_PA23A_RXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // RXD2
-  { PIOA, PIO_PA22A_TXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TXD2
-  { PIOA, PIO_PA23A_RXD2|PIO_PA22A_TXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All USART2 pins
+  { PIOA, PIO_PA23A_RXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // RXD2
+  { PIOA, PIO_PA22A_TXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TXD2
+  { PIOA, PIO_PA23A_RXD2|PIO_PA22A_TXD2, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), 0 }, // All USART2 pins
 
   // SPI, 15..18
-  { PIOA, PIO_PA13A_MISO, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // MISO
-  { PIOA, PIO_PA14A_MOSI, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // MOSI
-  { PIOA, PIO_PA15A_SPCK, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // SPCK
-  { PIOC, PIO_PA16A_NPCS0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // NPCS0
+  { PIOA, PIO_PA13A_MISO, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // MISO
+  { PIOA, PIO_PA14A_MOSI, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // MOSI
+  { PIOA, PIO_PA15A_SPCK, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // SPCK
+  { PIOC, PIO_PA16A_NPCS0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // NPCS0
 
   // TWI0, 19..21
-  { PIOA, PIO_PA9A_TWD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TWD0 - SDA1
-  { PIOA, PIO_PA10A_TWCK0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TWCK0 - SCL1
-  { PIOA, PIO_PA9A_TWD0|PIO_PA10A_TWCK0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All TWI0 pins
-  
+  { PIOA, PIO_PA9A_TWD0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TWD0 - SDA1
+  { PIOA, PIO_PA10A_TWCK0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TWCK0 - SCL1
+  { PIOA, PIO_PA9A_TWD0|PIO_PA10A_TWCK0, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), 0 }, // All TWI0 pins
+
   // TWI1, 22..24
-  { PIOA, PIO_PA24A_TWD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TWD1 - SDA0
-  { PIOA, PIO_PA25A_TWCK1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // TWCK1 - SCL0
-  { PIOA, PIO_PA24A_TWD1|PIO_PA25A_TWCK1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT }, // All TWI1 pins
-  
+  { PIOA, PIO_PA24A_TWD1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TWD1 - SDA0
+  { PIOA, PIO_PA25A_TWCK1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // TWCK1 - SCL0
+  { PIOA, PIO_PA24A_TWD1|PIO_PA25A_TWCK1, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_COMBO), 0 }, // All TWI1 pins
+
   // Analog, 25..38
-  { PIOB, PIO_PB5X1_AD0, ID_PIOB, PIO_INPUT, PIO_DEFAULT }, // AD0
-  { PIOB, PIO_PB6X1_AD1, ID_PIOB, PIO_INPUT, PIO_DEFAULT }, // AD1
-  { PIOB, PIO_PB7X1_AD2, ID_PIOB, PIO_INPUT, PIO_DEFAULT }, // AD2
-  { PIOB, PIO_PB8X1_AD3, ID_PIOB, PIO_INPUT, PIO_DEFAULT }, // AD3
-  { PIOC, PIO_PC28X1_AD4, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD4
-  { PIOC, PIO_PC29X1_AD5, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD5
-  { PIOC, PIO_PC30X1_AD6, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD6
-  { PIOC, PIO_PC31X1_AD7, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD7
-  
-  { PIOB, PIO_PB3X1_AD12B2, ID_PIOB, PIO_INPUT, PIO_DEFAULT }, // AD8
-  { PIOB, PIO_PB4X1_AD12B3, ID_PIOB, PIO_INPUT, PIO_DEFAULT }, // AD9
-  { PIOC, PIO_PC15X1_AD12B4, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD10
-  { PIOC, PIO_PC16X1_AD12B5, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD11
-  { PIOC, PIO_PC17X1_AD12B6, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD12
-  { PIOC, PIO_PC18X1_AD12B7, ID_PIOC, PIO_INPUT, PIO_DEFAULT }, // AD13
-  
+  { PIOB, PIO_PB5X1_AD0, ID_PIOB, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC0 }, // AD0
+  { PIOB, PIO_PB6X1_AD1, ID_PIOB, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC1 }, // AD1
+  { PIOB, PIO_PB7X1_AD2, ID_PIOB, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC2 }, // AD2
+  { PIOB, PIO_PB8X1_AD3, ID_PIOB, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC3 }, // AD3
+  { PIOC, PIO_PC28X1_AD4, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC4 }, // AD4
+  { PIOC, PIO_PC29X1_AD5, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC5 }, // AD5
+  { PIOC, PIO_PC30X1_AD6, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC6 }, // AD6
+  { PIOC, PIO_PC31X1_AD7, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC7 }, // AD7
+
+  { PIOB, PIO_PB3X1_AD12B2, ID_PIOB, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC8 }, // AD8
+  { PIOB, PIO_PB4X1_AD12B3, ID_PIOB, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC9 }, // AD9
+  { PIOC, PIO_PC15X1_AD12B4, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC10 }, // AD10
+  { PIOC, PIO_PC16X1_AD12B5, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC11 }, // AD11
+  { PIOC, PIO_PC17X1_AD12B6, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC12 }, // AD12
+  { PIOC, PIO_PC18X1_AD12B7, ID_PIOC, PIO_INPUT, PIO_DEFAULT, PIN_ATTR_ANALOG, ADC13 }, // AD13
+
   // External DAC, 39..41
-  { PIOB, PIO_PB9, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT }, // DAC-CS
-  { PIOB, PIO_PB10, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT }, // DAC-SCK
-  { PIOB, PIO_PB14, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT }, // DAC-DIN
+  { PIOB, PIO_PB9, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // DAC-CS
+  { PIOB, PIO_PB10, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // DAC-SCK
+  { PIOB, PIO_PB14, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // DAC-DIN
   
   // PWM, 42..50
-  { PIOA, PIO_PA30B_TIOA2, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT }, // PWM
-  { PIOA, PIO_PA4B_PWMH0, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT }, // PWMH0
-  { PIOA, PIO_PA5B_PWMH1, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT }, // PWMH1
-  { PIOA, PIO_PA6B_PWMH2, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT }, // PWMH2
-  { PIOB, PIO_PB16B_PWMH3, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT }, // PWMH3
-  { PIOC, PIO_PC6B_PWML0, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT }, // PWML0
-  { PIOC, PIO_PC7B_PWML1, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT }, // PWML1
-  { PIOC, PIO_PC8B_PWML2, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT }, // PWML2
-  { PIOC, PIO_PC9B_PWML3, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT }, // PWML3
+  { PIOA, PIO_PA30B_TIOA2, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWM
+  { PIOA, PIO_PA4B_PWMH0, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWMH0
+  { PIOA, PIO_PA5B_PWMH1, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWMH1
+  { PIOA, PIO_PA6B_PWMH2, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWMH2
+  { PIOB, PIO_PB16B_PWMH3, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWMH3
+  { PIOC, PIO_PC6B_PWML0, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWML0
+  { PIOC, PIO_PC7B_PWML1, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWML1
+  { PIOC, PIO_PC8B_PWML2, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWML2
+  { PIOC, PIO_PC9B_PWML3, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT, (PIN_ATTR_DIGITAL|PIN_ATTR_PWM), 0 }, // PWML3
   
   // 51
-  { PIOA, PIO_PA1, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 10
+  { PIOA, PIO_PA1, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, 0, 0 }, // PIN 10
   
   // Digital, 52..83
-  { PIOC, PIO_PC3 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 22
-  { PIOC, PIO_PC2 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 23
-  { PIOC, PIO_PC1 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 24
-  { PIOC, PIO_PC0 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 25
-  { PIOB, PIO_PB28, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 26
-  { PIOB, PIO_PB27, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 27
-  { PIOB, PIO_PB26, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 28
-  { PIOB, PIO_PB25, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 29
-  { PIOB, PIO_PB24, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 30
-  { PIOB, PIO_PB23, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 31
-  { PIOB, PIO_PB22, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 32
-  { PIOB, PIO_PB21, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 33
-  { PIOB, PIO_PB20, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 34
-  { PIOB, PIO_PB19, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 35
-  { PIOB, PIO_PB18, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 36
-  { PIOB, PIO_PB17, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 37
-  { PIOA, PIO_PA28, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 38
-  { PIOA, PIO_PA29, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 39
-  { PIOC, PIO_PC22, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 40
-  { PIOA, PIO_PA31, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 41
-  { PIOC, PIO_PC23, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 42
-  { PIOB, PIO_PB0 , ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 43
-  { PIOC, PIO_PC24, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 44
-  { PIOB, PIO_PB1 , ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 45
-  { PIOC, PIO_PC25, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 46
-  { PIOB, PIO_PB2 , ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 47
-  { PIOC, PIO_PC26, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 48
-  { PIOB, PIO_PB11, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 49
-  { PIOB, PIO_PB12, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 50
-  { PIOB, PIO_PB13, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 51
-  { PIOC, PIO_PC27, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 52
-  { PIOA, PIO_PA27, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT }, // PIN 53
+  { PIOC, PIO_PC3 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 22
+  { PIOC, PIO_PC2 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 23
+  { PIOC, PIO_PC1 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 24
+  { PIOC, PIO_PC0 , ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 25
+  { PIOB, PIO_PB28, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 26
+  { PIOB, PIO_PB27, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 27
+  { PIOB, PIO_PB26, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 28
+  { PIOB, PIO_PB25, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 29
+  { PIOB, PIO_PB24, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 30
+  { PIOB, PIO_PB23, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 31
+  { PIOB, PIO_PB22, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 32
+  { PIOB, PIO_PB21, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 33
+  { PIOB, PIO_PB20, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 34
+  { PIOB, PIO_PB19, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 35
+  { PIOB, PIO_PB18, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 36
+  { PIOB, PIO_PB17, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 37
+  { PIOA, PIO_PA28, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 38
+  { PIOA, PIO_PA29, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 39
+  { PIOC, PIO_PC22, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 40
+  { PIOA, PIO_PA31, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 41
+  { PIOC, PIO_PC23, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 42
+  { PIOB, PIO_PB0 , ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 43
+  { PIOC, PIO_PC24, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 44
+  { PIOB, PIO_PB1 , ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 45
+  { PIOC, PIO_PC25, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 46
+  { PIOB, PIO_PB2 , ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 47
+  { PIOC, PIO_PC26, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 48
+  { PIOB, PIO_PB11, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 49
+  { PIOB, PIO_PB12, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 50
+  { PIOB, PIO_PB13, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 51
+  { PIOC, PIO_PC27, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 52
+  { PIOA, PIO_PA27, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT, PIN_ATTR_DIGITAL, 0 }, // PIN 53
 
-  { NULL, 0, 0, PIO_NOT_A_PIN, PIO_DEFAULT } // END
+  { NULL, 0, 0, PIO_NOT_A_PIN, PIO_DEFAULT, 0, 0 } /* END */
 } ;
 
 /*
@@ -234,7 +234,7 @@ extern void init( void )
 
   // Initialize Serial port UART, common to all SAM3 variants
   PIO_Configure( g_APinDescription[PINS_UART].pPort, g_APinDescription[PINS_UART].ulPinType,
-                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinAttribute ) ;
+                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinConfiguration ) ;
 }
 #ifdef __cplusplus
 }
diff --git a/hardware/sam/variants/sam3s_ek/variant.cpp b/hardware/sam/variants/sam3s_ek/variant.cpp
index 6dec8ee48..b637274c6 100644
--- a/hardware/sam/variants/sam3s_ek/variant.cpp
+++ b/hardware/sam/variants/sam3s_ek/variant.cpp
@@ -227,11 +227,11 @@ extern void init( void )
 
   // Initialize Serial port UART0, common to all SAM3 variants
   PIO_Configure( g_APinDescription[PINS_UART].pPort, g_APinDescription[PINS_UART].ulPinType,
-                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinAttribute ) ;
+                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinConfiguration ) ;
 
   // Switch off Power LED
   PIO_Configure( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPinType,
-                 g_APinDescription[PIN_LED_RED].ulPin, g_APinDescription[PIN_LED_RED].ulPinAttribute ) ;
+                 g_APinDescription[PIN_LED_RED].ulPin, g_APinDescription[PIN_LED_RED].ulPinConfiguration ) ;
   PIO_Clear( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPin ) ;
 }
 #ifdef __cplusplus
diff --git a/hardware/sam/variants/sam3u_ek/variant.cpp b/hardware/sam/variants/sam3u_ek/variant.cpp
index 213cd7cc7..23a92b24b 100644
--- a/hardware/sam/variants/sam3u_ek/variant.cpp
+++ b/hardware/sam/variants/sam3u_ek/variant.cpp
@@ -169,11 +169,11 @@ extern void init( void )
 
   // Initialize UART Serial port 
   PIO_Configure( g_APinDescription[PINS_UART].pPort, g_APinDescription[PINS_UART].ulPinType,
-                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinAttribute ) ;
+                 g_APinDescription[PINS_UART].ulPin, g_APinDescription[PINS_UART].ulPinConfiguration ) ;
 
   // Switch off Power LED
   PIO_Configure( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPinType,
-                 g_APinDescription[PIN_LED_RED].ulPin, g_APinDescription[PIN_LED_RED].ulPinAttribute ) ;
+                 g_APinDescription[PIN_LED_RED].ulPin, g_APinDescription[PIN_LED_RED].ulPinConfiguration ) ;
   PIO_Clear( g_APinDescription[PIN_LED_RED].pPort, g_APinDescription[PIN_LED_RED].ulPin ) ;
 }
 #ifdef __cplusplus