Adding libchip_sam3s into tools, needed to add all SAM3S peripheral drivers

hardware/tools/libchip_sam3s/build_gcc/Makefile

@@ -0,0 +1,25 @@
+# Makefile for compiling libchip
+
+SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+all: libchip_sam3s4_gcc_dbg.a libchip_sam3s4_gcc_rel.a
+
+libchip_sam3s4_gcc_dbg.a:
+	@echo --- Making $@
+	@$(MAKE) CHIP=sam3s4 DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3s.mk
+
+libchip_sam3s4_gcc_rel.a:
+	@echo --- Making $@
+	@$(MAKE) CHIP=sam3s4 $(SUBMAKE_OPTIONS) -f sam3s.mk
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning sam3s4 release and debug
+	@$(MAKE) CHIP=sam3s4 $(SUBMAKE_OPTIONS) -f sam3s.mk $@
+	@$(MAKE) CHIP=sam3s4 DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3s.mk $@
+
+

hardware/tools/libchip_sam3s/build_gcc/debug.mk

@@ -0,0 +1,7 @@
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -g -O0 -DDEBUG

hardware/tools/libchip_sam3s/build_gcc/gcc.mk

@@ -0,0 +1,39 @@
+
+# Tool suffix when cross-compiling
+#CROSS_COMPILE = ../../CodeSourcery_arm/bin/arm-none-eabi-
+CROSS_COMPILE = C:/CodeSourcery_2011.03-42/bin/arm-none-eabi-
+
+# Compilation tools
+AR = $(CROSS_COMPILE)ar
+CC = $(CROSS_COMPILE)gcc
+AS = $(CROSS_COMPILE)as
+#LD = $(CROSS_COMPILE)ld
+#SIZE = $(CROSS_COMPILE)size
+NM = $(CROSS_COMPILE)nm
+#OBJCOPY = $(CROSS_COMPILE)objcopy
+RM=cs-rm -Rf
+SEP=/
+
+# Flags
+
+CFLAGS += -Wall -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int
+CFLAGS += -Werror-implicit-function-declaration -Wmain -Wparentheses
+CFLAGS += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused
+CFLAGS += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef
+CFLAGS += -Wshadow -Wpointer-arith -Wbad-function-cast -Wwrite-strings
+CFLAGS += -Wsign-compare -Waggregate-return -Wstrict-prototypes
+CFLAGS += -Wmissing-prototypes -Wmissing-declarations
+CFLAGS += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations
+CFLAGS += -Wpacked -Wredundant-decls -Wnested-externs -Winline -Wlong-long
+CFLAGS += -Wunreachable-code
+CFLAGS += -Wcast-align
+#CFLAGS += -Wmissing-noreturn
+#CFLAGS += -Wconversion
+
+# To reduce application size use only integer printf function.
+CFLAGS += -Dprintf=iprintf
+
+CFLAGS += --param max-inline-insns-single=500 -mcpu=cortex-m3 -mthumb -mlong-calls -ffunction-sections
+CFLAGS += $(OPTIMIZATION) $(INCLUDES) -D$(CHIP)
+
+ASFLAGS = -mcpu=cortex-m3 -mthumb -Wall -a -g $(INCLUDES)

hardware/tools/libchip_sam3s/build_gcc/release.mk

@@ -0,0 +1,7 @@
+# Optimization level
+# -O1 Optimize
+# -O2 Optimize even more
+# -O3 Optimize yet more
+# -O0 Reduce compilation time and make debugging produce the expected results
+# -Os Optimize for size
+OPTIMIZATION = -Os

hardware/tools/libchip_sam3s/build_gcc/sam3s.mk

@@ -0,0 +1,129 @@
+# Makefile for compiling libchip
+.SUFFIXES: .o .a .c .s
+SUB_MAKEFILES=debug.mk gcc.mk release.mk win.mk sam3s.mk
+
+LIBNAME=libchip
+TOOLCHAIN=gcc
+
+ifeq ($(CHIP),)
+$(error CHIP not defined)
+endif
+
+#-------------------------------------------------------------------------------
+# Path
+#-------------------------------------------------------------------------------
+
+# Output directories
+OUTPUT_BIN = ../lib
+
+# Libraries
+PROJECT_BASE_PATH = ..
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+vpath %.h $(PROJECT_BASE_PATH)/include
+vpath %.c $(PROJECT_BASE_PATH)/source $(PROJECT_BASE_PATH)/cmsis
+vpath %.s $(PROJECT_BASE_PATH)/source $(PROJECT_BASE_PATH)/cmsis
+
+VPATH+=$(PROJECT_BASE_PATH)/source
+VPATH+=$(PROJECT_BASE_PATH)/cmsis
+
+INCLUDES = -I$(PROJECT_BASE_PATH)
+INCLUDES += -I$(PROJECT_BASE_PATH)/include
+INCLUDES += -I$(PROJECT_BASE_PATH)/cmsis
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+include debug.mk
+else
+include release.mk
+endif
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+include $(TOOLCHAIN).mk
+
+#-------------------------------------------------------------------------------
+ifdef DEBUG
+OUTPUT_OBJ=debug
+OUTPUT_LIB=$(LIBNAME)_$(CHIP)_$(TOOLCHAIN)_dbg.a
+else
+OUTPUT_OBJ=release
+OUTPUT_LIB=$(LIBNAME)_$(CHIP)_$(TOOLCHAIN)_rel.a
+endif
+
+OUTPUT_PATH=$(OUTPUT_OBJ)_$(CHIP)
+
+#-------------------------------------------------------------------------------
+# C source files and objects
+#-------------------------------------------------------------------------------
+C_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.c)
+C_SRC+=$(wildcard $(PROJECT_BASE_PATH)/cmsis/*.c)
+
+C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC)))
+
+# during development, remove some files
+C_OBJ_FILTER=pio_it.o
+
+C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Assembler source files and objects
+#-------------------------------------------------------------------------------
+A_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.s)
+A_SRC+=$(wildcard $(PROJECT_BASE_PATH)/cmsis/*.s)
+
+A_OBJ_TEMP=$(patsubst %.s, %.o, $(notdir $(A_SRC)))
+
+# during development, remove some files
+A_OBJ_FILTER=
+
+A_OBJ=$(filter-out $(A_OBJ_FILTER), $(A_OBJ_TEMP))
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+all: $(CHIP)
+
+$(CHIP): create_output $(OUTPUT_LIB)
+
+.PHONY: create_output
+create_output:
+	@echo --- Preparing $(CHIP) files $(OUTPUT_PATH) $(OUTPUT_BIN)
+#	@echo -------------------------
+#	@echo *$(C_SRC)
+#	@echo -------------------------
+#	@echo *$(C_OBJ)
+#	@echo -------------------------
+#	@echo *$(addprefix $(OUTPUT_PATH)/, $(C_OBJ))
+#	@echo -------------------------
+#	@echo *$(A_SRC)
+#	@echo -------------------------
+
+	-@mkdir $(subst /,$(SEP),$(OUTPUT_BIN)) 1>NUL 2>&1
+	-@mkdir $(OUTPUT_PATH) 1>NUL 2>&1
+
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: %.c
+#	"$(CC)" -v -c $(CFLAGS) -Wa,aln=$(subst .o,.s,$@) $< -o $@
+	@"$(CC)" -c $(CFLAGS) $< -o $@
+
+$(addprefix $(OUTPUT_PATH)/,$(A_OBJ)): $(OUTPUT_PATH)/%.o: %.s
+	@"$(AS)" -c $(ASFLAGS) $< -o $@
+
+$(OUTPUT_LIB): $(addprefix $(OUTPUT_PATH)/, $(C_OBJ)) $(addprefix $(OUTPUT_PATH)/, $(A_OBJ))
+	@"$(AR)" -r "$(OUTPUT_BIN)/$@" $^
+	@"$(NM)" "$(OUTPUT_BIN)/$@" > "$(OUTPUT_BIN)/$@.txt"
+
+.PHONY: clean
+clean:
+	@echo --- Cleaning $(CHIP) files
+	-@$(RM) $(OUTPUT_PATH) 1>NUL 2>&1
+	-@$(RM) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB)) 1>NUL 2>&1
+	-@$(RM) $(subst /,$(SEP),$(OUTPUT_BIN)/$(OUTPUT_LIB)).txt 1>NUL 2>&1
+
+# dependencies
+$(addprefix $(OUTPUT_PATH)/,$(C_OBJ)): $(OUTPUT_PATH)/%.o: $(PROJECT_BASE_PATH)/chip.h $(wildcard $(PROJECT_BASE_PATH)/include/*.h) $(wildcard $(PROJECT_BASE_PATH)/cmsis/*.h)

hardware/tools/libchip_sam3s/chip.h

@@ -0,0 +1,62 @@
+#ifndef _LIB_SAM3S_
+#define _LIB_SAM3S_
+
+/*
+ * Peripherals registers definitions
+ */
+#if defined sam3s4
+#elif defined sam3s2
+#elif defined sam3s1
+#else
+    #warning Library does not support the specified chip, specifying sam3s4.
+    #define sam3s4
+#endif
+#include "include/SAM3S.h"
+
+/** Define MAX number of Interrupts: (IRQn_Type+1) + 8 for CM3 core */
+#define EXTERNAL_NUM_INTERRUPTS (UDP_IRQn+1+8)
+
+/* Define attribute */
+#if defined (  __GNUC__  ) /* GCC CS3 */
+    #define WEAK __attribute__ ((weak))
+#endif
+
+/* Define NO_INIT attribute */
+#if defined (  __GNUC__  )
+    #define NO_INIT
+#endif
+
+
+/*
+ * Core
+ */
+
+#include "include/exceptions.h"
+
+/*
+ * Peripherals
+ */
+#include "include/acc.h"
+#include "include/adc.h"
+#include "include/async.h"
+#include "include/crccu.h"
+#include "include/dacc.h"
+#include "include/efc.h"
+#include "include/flashd.h"
+#include "include/pio.h"
+//#include "include/pio_it.h"
+#include "include/pio_capture.h"
+#include "include/pmc.h"
+#include "include/pwmc.h"
+#include "include/rtc.h"
+#include "include/rtt.h"
+#include "include/spi.h"
+#include "include/spi_pdc.h"
+#include "include/ssc.h"
+#include "include/tc.h"
+#include "include/twi.h"
+#include "include/twid.h"
+#include "include/usart.h"
+#include "include/wdt.h"
+
+#endif /* _LIB_SAM3S_ */

hardware/tools/libchip_sam3s/cmsis/core_cm3.c

@@ -0,0 +1,339 @@
+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V2.00
+ * @date     13. September 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ##########################  Core Instruction Access  ######################### */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+__ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+__ASM void __CLREX(void)
+{
+  clrex
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_IPSR(void)
+{
+  mrs r0, ipsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_APSR(void)
+{
+  mrs r0, apsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_xPSR(void)
+{
+  mrs r0, xpsr
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask Register.
+
+    \return               Fault Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set the Fault Mask
+
+     This function assigns the given value to the Fault Mask Register.
+
+    \param [in]    faultMask  Fault Mask value value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* obsolete */
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* obsolete */
+#endif

hardware/tools/libchip_sam3s/cmsis/core_cmFunc.h

@@ -0,0 +1,844 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.01
+ * @date     06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H__
+#define __CORE_CMFUNC_H__
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_CONTROL(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_CONTROL(uint32_t control);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_IPSR(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_APSR(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_xPSR(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_PSP(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_PSP(uint32_t topOfProcStack);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_MSP(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_MSP(uint32_t topOfMainStack);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_PRIMASK(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_PRIMASK(uint32_t priMask);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_BASEPRI(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_BASEPRI(uint32_t basePri);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_FAULTMASK(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_FAULTMASK(uint32_t faultMask);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & 1);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+ #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#if defined (__ICCARM__)
+  #include <intrinsics.h>                     /* IAR Intrinsics   */
+#endif
+
+#pragma diag_suppress=Pe940
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+#define __enable_irq                              __enable_interrupt
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+#define __disable_irq                             __disable_interrupt
+
+
+/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
+/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static uint32_t __get_IPSR(void)
+{
+  __ASM("mrs r0, ipsr");
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static uint32_t __get_APSR(void)
+{
+  __ASM("mrs r0, apsr");
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static uint32_t __get_xPSR(void)
+{
+  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+}
+ 
+
+/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
+/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+static __INLINE void __enable_fault_irq(void)
+{
+  __ASM ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+static __INLINE void __disable_fault_irq(void)
+{
+  __ASM ("cpsid f");
+}
+
+
+/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
+/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
+/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
+/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM("vmrs r0, fpscr"); 
+#else
+  return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM("vmsr fpscr, r0");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H__ */

hardware/tools/libchip_sam3s/cmsis/core_cmInstr.h

@@ -0,0 +1,775 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.01
+ * @date     06. December 2010
+ *
+ * @note
+ * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H__
+#define __CORE_CMINSTR_H__
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern uint32_t __REV16(uint32_t value);
+#else  /* (__ARMCC_VERSION >= 400677)  */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern int32_t __REVSH(int32_t value);
+#else  /* (__ARMCC_VERSION >= 400677)  */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __CLREX(void);
+#else  /* (__ARMCC_VERSION >= 400000)  */
+#define __CLREX                           __clrex
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#include <intrinsics.h>                     /* IAR Intrinsics   */
+
+#pragma diag_suppress=Pe940
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                           __no_operation
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+static __INLINE  void __WFI(void)
+{
+  __ASM ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+static __INLINE  void __WFE(void)
+{
+  __ASM ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+static __INLINE  void __SEV(void)
+{
+  __ASM ("sev");
+}
+
+
+/* intrinsic     void __ISB(void)            (see intrinsics.h) */
+/* intrinsic     void __DSB(void)            (see intrinsics.h) */
+/* intrinsic     void __DMB(void)            (see intrinsics.h) */
+/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
+/* intrinsic          __SSAT                 (see intrinsics.h) */
+/* intrinsic          __USAT                 (see intrinsics.h) */
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static uint32_t __REV16(uint32_t value)
+{
+  __ASM("rev16 r0, r0");
+}
+
+
+/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+static uint8_t __LDREXB(volatile uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+static uint16_t __LDREXH(volatile uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
+static uint32_t __LDREXW(volatile uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
+static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+static __INLINE void __CLREX(void)
+{
+  __ASM ("clrex");
+}
+
+/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#pragma diag_default=Pe940
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H__ */

hardware/tools/libchip_sam3s/include/acc.h

@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuration the Analog-to-Digital Converter (ACC) peripheral.
+ *
+ *  \section Usage
+ *
+ *  -# Configurate the pins for ACC
+ *  -# Initialize the ACC with ACC_Initialize().
+ *  -# Select the active channel using ACC_EnableChannel()
+ *  -# Start the conversion with ACC_StartConversion()
+ *  -# Wait the end of the conversion by polling status with ACC_GetStatus()
+ *  -# Finally, get the converted data using ACC_GetConvertedData()
+ *
+ */
+#ifndef _ACC_
+#define _ACC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+#include <assert.h>
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+#define ACC_SELPLUS_AD12B0 0
+#define ACC_SELPLUS_AD12B1 1
+#define ACC_SELPLUS_AD12B2 2
+#define ACC_SELPLUS_AD12B3 3
+#define ACC_SELPLUS_AD12B4 4
+#define ACC_SELPLUS_AD12B5 5
+#define ACC_SELPLUS_AD12B6 6
+#define ACC_SELPLUS_AD12B7 7
+#define ACC_SELMINUS_TS 0
+#define ACC_SELMINUS_ADVREF 1
+#define ACC_SELMINUS_DAC0   2
+#define ACC_SELMINUS_DAC1   3
+#define ACC_SELMINUS_AD12B0 4
+#define ACC_SELMINUS_AD12B1 5
+#define ACC_SELMINUS_AD12B2 6
+#define ACC_SELMINUS_AD12B3 7
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ *         Macros function of register access
+ *------------------------------------------------------------------------------*/
+#define ACC_CfgModeReg(pAcc, mode)  { \
+            (pAcc)->ACC_MR = (mode);\
+        }
+
+#define ACC_GetModeReg( pAcc )                ((pAcc)->ACC_MR)
+
+#define ACC_StartConversion( pAcc )           ((pAcc)->ACC_CR = ACC_CR_START)
+
+#define ACC_SoftReset( pAcc )                 ((pAcc)->ACC_CR = ACC_CR_SWRST)
+
+#define ACC_EnableChannel( pAcc, dwChannel )    {\
+            assert( dwChannel < 16 ) ;\
+            (pAcc)->ACC_CHER = (1 << (dwChannel));\
+        }
+
+#define ACC_DisableChannel( pAcc, dwChannel )  {\
+            assert( dwChannel < 16 ) ;\
+            (pAcc)->ACC_CHDR = (1 << (dwChannel));\
+        }
+
+#define ACC_EnableIt( pAcc, dwMode )            {\
+            assert( ((dwMode)&0xFFF00000)== 0 ) ;\
+            (pAcc)->ACC_IER = (dwMode);\
+        }
+
+#define ACC_DisableIt( pAcc, dwMode )           {\
+            assert( ((dwMode)&0xFFF00000)== 0 ) ;\
+            (pAcc)->ACC_IDR = (dwMode);\
+        }
+
+#define ACC_EnableDataReadyIt( pAcc )         ((pAcc)->ACC_IER = AT91C_ACC_DRDY)
+
+#define ACC_GetStatus( pAcc )                 ((pAcc)->ACC_ISR)
+
+#define ACC_GetChannelStatus( pAcc )          ((pAcc)->ACC_CHSR)
+
+#define ACC_GetInterruptMaskStatus( pAcc )    ((pAcc)->ACC_IMR)
+
+#define ACC_GetLastConvertedData( pAcc )      ((pAcc)->ACC_LCDR)
+
+#define ACC_CfgAnalogCtrlReg( pAcc, dwMode )     {\
+            assert( ((dwMode) & 0xFFFCFF3C) == 0 ) ;\
+            (pAcc)->ACC_ACR = (dwMode);\
+        }
+
+#define ACC_CfgExtModeReg( pAcc, extmode )    {\
+            assert( ((extmode) & 0xFF00FFFE) == 0 ) ;\
+            (pAcc)->ACC_EMR = (extmode);\
+        }
+
+#define ACC_GetAnalogCtrlReg( pAcc )          ((pAcc)->ACC_ACR)
+
+/*------------------------------------------------------------------------------
+ *         Exported functions
+ *------------------------------------------------------------------------------*/
+extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, uint8_t ucSelminus,
+                           uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert ) ;
+
+extern void ACC_SetComparisionPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus ) ;
+
+extern uint32_t ACC_GetComparisionResult( Acc* pAcc, uint32_t dwStatus ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _ACC_ */

hardware/tools/libchip_sam3s/include/adc.h

@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuration the Analog-to-Digital Converter (ADC) peripheral.
+ *
+ *  \section Usage
+ *
+ *  -# Configurate the pins for ADC
+ *  -# Initialize the ADC with ADC_Initialize().
+ *  -# Select the active channel using ADC_EnableChannel()
+ *  -# Start the conversion with ADC_StartConversion()
+ *  -# Wait the end of the conversion by polling status with ADC_GetStatus()
+ *  -# Finally, get the converted data using ADC_GetConvertedData()
+ *
+*/
+#ifndef _ADC_
+#define _ADC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <assert.h>
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+/* SAM3S */
+#define ADC_FREQ_MAX   20000000
+#define ADC_FREQ_MIN    1000000
+
+#define ADC_STARTUP_NORM     40
+#define ADC_STARTUP_FAST     12
+
+#define ADC_CHANNEL_0  0
+#define ADC_CHANNEL_1  1
+#define ADC_CHANNEL_2  2
+#define ADC_CHANNEL_3  3
+#define ADC_CHANNEL_4  4
+#define ADC_CHANNEL_5  5
+#define ADC_CHANNEL_6  6
+#define ADC_CHANNEL_7  7
+#define ADC_CHANNEL_8  8
+#define ADC_CHANNEL_9  9
+#define ADC_CHANNEL_10 10
+#define ADC_CHANNEL_11 11
+#define ADC_CHANNEL_12 12
+#define ADC_CHANNEL_13 13
+#define ADC_CHANNEL_14 14
+#define ADC_CHANNEL_15 15
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ *         Macros function of register access
+ *------------------------------------------------------------------------------*/
+
+#define ADC_GetModeReg( pAdc )                ((pAdc)->ADC_MR)
+
+#define ADC_StartConversion( pAdc )           ((pAdc)->ADC_CR = ADC_CR_START)
+
+
+#define ADC_EnableChannel( pAdc, channel )    {\
+            assert( channel < 16 ) ;\
+            (pAdc)->ADC_CHER = (1 << (channel));\
+        }
+
+#define ADC_DisableChannel(pAdc, channel)  {\
+            assert( (channel) < 16 ) ;\
+            (pAdc)->ADC_CHDR = (1 << (channel));\
+        }
+
+#define ADC_EnableIt(pAdc, dwMode)            {\
+            (pAdc)->ADC_IER = (dwMode);\
+        }
+
+#define ADC_DisableIt(pAdc, dwMode)           {\
+            (pAdc)->ADC_IDR = (dwMode);\
+        }
+
+#define ADC_EnableTS(pAdc,dwMode)             {\
+            (pAdc)->ADC_ACR |= dwMode;\
+        }
+
+#define ADC_EnableDataReadyIt(pAdc)         ((pAdc)->ADC_IER = AT91C_ADC_DRDY)
+
+#define ADC_GetStatus(pAdc)                 ((pAdc)->ADC_ISR)
+
+#define ADC_GetCompareMode(pAdc)            (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk))
+
+#define ADC_GetChannelStatus(pAdc)          ((pAdc)->ADC_CHSR)
+
+#define ADC_GetInterruptMaskStatus(pAdc)    ((pAdc)->ADC_IMR)
+
+#define ADC_GetLastConvertedData(pAdc)      ((pAdc)->ADC_LCDR)
+
+/*------------------------------------------------------------------------------
+ *         Exported functions
+ *------------------------------------------------------------------------------*/
+extern void ADC_Initialize( Adc* pAdc, uint32_t idAdc );
+extern void ADC_CfgTiming( Adc* pAdc, uint32_t tracking, uint32_t settling, uint32_t transfer );
+extern void ADC_cfgFrequency( Adc* pAdc, uint32_t startup, uint32_t prescal );
+extern void ADC_CfgTrigering( Adc* pAdc, uint32_t trgEn, uint32_t trgSel, uint32_t freeRun );
+extern void ADC_CfgLowRes( Adc* pAdc, uint32_t resolution );
+extern void ADC_CfgPowerSave( Adc* pAdc, uint32_t sleep, uint32_t fwup );
+extern void ADC_CfgChannelMode( Adc* pAdc, uint32_t useq, uint32_t anach );
+extern void ADC_check( Adc* pAdc, uint32_t mck_freq );
+
+extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ;
+extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ;
+extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ;
+extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ;
+extern uint32_t ADC_IsInterruptMasked( Adc* pAdc, uint32_t dwFlag ) ;
+extern uint32_t ADC_IsStatusSet( Adc* pAdc, uint32_t dwFlag ) ;
+extern uint32_t ADC_IsChannelInterruptStatusSet( uint32_t adc_sr, uint32_t dwChannel ) ;
+extern uint32_t ADC_ReadBuffer( Adc* pADC, int16_t *pwBuffer, uint32_t dwSize ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _ADC_ */

hardware/tools/libchip_sam3s/include/async.h

@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Provide a routine for asynchronous transfer.
+ *
+ */
+
+#ifndef _ASYNC_
+#define _ASYNC_
+
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Definition
+ *----------------------------------------------------------------------------*/
+/** Transfer is still pending.*/
+#define ASYNC_STATUS_PENDING        0xFF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Type
+ *----------------------------------------------------------------------------*/
+/** \brief Asynchronous transfer descriptor. */
+typedef struct _Async
+{
+    /** Asynchronous transfer status.*/
+    volatile uint8_t status ;
+    /** Callback function to invoke when transfer completes or fails.*/
+    void *callback ;
+    /** Driver storage area; do not use.*/
+    uint32_t pStorage[4] ;
+} Async ;
+
+/*----------------------------------------------------------------------------
+ *        Global functions
+ *----------------------------------------------------------------------------*/
+extern uint32_t ASYNC_IsFinished( Async* pAsync ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _ASYNC_ */
+

hardware/tools/libchip_sam3s/include/crccu.h

@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Cyclic Redundancy Check Calculation Unit (CRCCU).
+ */
+
+#ifndef _CRCCU_
+#define _CRCCU_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+typedef struct
+{
+    uint32_t TR_ADDR ;
+    uint32_t TR_CTRL ;
+} CrcDscr ;
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void CRCCU_ResetCrcValue( Crccu* pCrccu ) ;
+extern void CRCCU_Configure( Crccu* pCrccu, uint32_t dwDscrAddr, uint32_t dwMode ) ;
+extern uint32_t CRCCU_ComputeCrc( Crccu* pCrccu ) ;
+
+#endif /* #ifndef _CRCCU_ */
+

hardware/tools/libchip_sam3s/include/dacc.h

@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuration the Analog-to-Digital Converter (DACC) peripheral.
+ *
+ *  \section Usage
+ *
+ *  -# Configurate the pins for DACC
+ *  -# Initialize the DACC with DACC_Initialize().
+ *  -# Select the active channel using DACC_EnableChannel()
+ *  -# Start the conversion with DACC_StartConversion()
+ *  -# Wait the end of the conversion by polling status with DACC_GetStatus()
+ *  -# Finally, get the converted data using DACC_GetConvertedData()
+ *
+*/
+#ifndef _DACC_
+#define _DACC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+#include <assert.h>
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+#define DACC_CHANNEL_0 0
+#define DACC_CHANNEL_1 1
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ *         Macros function of register access
+ *------------------------------------------------------------------------------*/
+#define DACC_CfgModeReg(pDACC, mode)  { \
+             (pDACC)->DACC_MR = (mode);\
+        }
+
+#define DACC_GetModeReg(pDACC)                ((pDACC)->DACC_MR)
+
+#define DACC_StartConversion(pDACC)           ((pDACC)->DACC_CR = DACC_CR_START)
+
+#define DACC_SoftReset(pDACC)                 ((pDACC)->DACC_CR = DACC_CR_SWRST)
+
+#define DACC_EnableChannel(pDACC, channel)    {\
+            (pDACC)->DACC_CHER = (1 << (channel));\
+        }
+
+#define DACC_DisableChannel(pDACC, channel)  {\
+            (pDACC)->DACC_CHDR = (1 << (channel));\
+        }
+
+#define DACC_EnableIt(pDACC, mode)            {\
+            assert( ((mode)&0xFFF00000)== 0 ) ;\
+            (pDACC)->DACC_IER = (mode);\
+        }
+
+#define DACC_DisableIt(pDACC, mode)           {\
+            assert( ((mode)&0xFFF00000)== 0 ) ;\
+            (pDACC)->DACC_IDR = (mode);\
+        }
+
+#define DACC_EnableDataReadyIt(pDACC)         ((pDACC)->DACC_IER = AT91C_DACC_DRDY)
+
+#define DACC_GetStatus(pDACC)                 ((pDACC)->DACC_ISR)
+
+#define DACC_GetChannelStatus(pDACC)          ((pDACC)->DACC_CHSR)
+
+#define DACC_GetInterruptMaskStatus(pDACC)    ((pDACC)->DACC_IMR)
+
+#define DACC_GetLastConvertedData(pDACC)      ((pDACC)->DACC_LCDR)
+
+#define DACC_CfgAnalogCtrlReg(pDACC,mode)     {\
+            assert( ((mode) & 0xFFFCFF3C)==0 ) ;\
+            (pDACC)->DACC_ACR = (mode);\
+        }
+
+#define DACC_CfgExtModeReg(pDACC, extmode)    {\
+            assert( ((extmode) & 0xFF00FFFE)==0 ) ;\
+            (pDACC)->DACC_EMR = (extmode);\
+        }
+
+#define DACC_GetAnalogCtrlReg(pDACC)          ((pDACC)->DACC_ACR)
+
+/*------------------------------------------------------------------------------
+ *         Exported functions
+ *------------------------------------------------------------------------------*/
+extern void DACC_Initialize( Dacc* pDACC,
+                     uint8_t idDACC,
+                     uint8_t trgEn,
+                     uint8_t trgSel,
+                     uint8_t word,
+                     uint8_t sleepMode,
+                     uint32_t mck,
+                     uint8_t refresh,/*refresh period*/
+                     uint8_t user_sel,/*user channel selection*/
+                     uint32_t tag_mode,/*using tag for channel number*/
+                     uint32_t startup
+                     );
+
+
+extern void DACC_SetConversionData( Dacc* pDACC, uint32_t dwData ) ;
+
+extern uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t* pwBuffer, uint32_t dwSize ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _DACC_ */

hardware/tools/libchip_sam3s/include/efc.h

@@ -0,0 +1,113 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \section Purpose
+ *
+ * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) peripheral.
+ *
+ * \section Usage
+ *
+ * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt()
+ *    and EFC_DisableFrdyIt().
+ * -# Translates the given address into which EEFC, page and offset values
+ *    for difference density %flash memory using EFC_TranslateAddress().
+ * -# Computes the address of a %flash access given the EFC, page and offset
+ *    for difference density %flash memory using EFC_ComputeAddress().
+ * -# Start the executing command with EFC_StartCommand()
+ * -# Retrieve the current status of the EFC using EFC_GetStatus().
+ * -# Retrieve the result of the last executed command with EFC_GetResult().
+ */
+
+#ifndef _EEFC_
+#define _EEFC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+/* EFC command */
+#define EFC_FCMD_GETD    0x00
+#define EFC_FCMD_WP      0x01
+#define EFC_FCMD_WPL     0x02
+#define EFC_FCMD_EWP     0x03
+#define EFC_FCMD_EWPL    0x04
+#define EFC_FCMD_EA      0x05
+#define EFC_FCMD_SLB     0x08
+#define EFC_FCMD_CLB     0x09
+#define EFC_FCMD_GLB     0x0A
+#define EFC_FCMD_SFB     0x0B
+#define EFC_FCMD_CFB     0x0C
+#define EFC_FCMD_GFB     0x0D
+#define EFC_FCMD_STUI    0x0E /* Start unique ID */
+#define EFC_FCMD_SPUI    0x0F /* Stop unique ID */
+
+/* The IAP function entry addreass */
+#define CHIP_FLASH_IAP_ADDRESS  (0x00800008)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void EFC_EnableFrdyIt( Efc* efc ) ;
+
+extern void EFC_DisableFrdyIt( Efc* efc ) ;
+
+extern void EFC_SetWaitState( Efc* efc, uint8_t cycles ) ;
+
+extern void EFC_TranslateAddress( Efc** pEfc, uint32_t dwAddress, uint16_t *pwPage, uint16_t *pwOffset ) ;
+
+extern void EFC_ComputeAddress( Efc* efc, uint16_t wPage, uint16_t wOffset, uint32_t *pdwAddress ) ;
+
+extern void EFC_StartCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument ) ;
+
+extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument, uint32_t dwUseIAP ) ;
+
+extern uint32_t EFC_GetStatus( Efc* efc ) ;
+
+extern uint32_t EFC_GetResult( Efc* efc ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _EEFC_ */
+

hardware/tools/libchip_sam3s/include/exceptions.h

@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ * Interface for default exception handlers.
+ */
+
+#ifndef _EXCEPTIONS_
+#define _EXCEPTIONS_
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+/* Function prototype for exception table items (interrupt handler). */
+typedef void( *IntFunc )( void ) ;
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#endif /* _EXCEPTIONS_ */

hardware/tools/libchip_sam3s/include/flashd.h

@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+*/
+
+/**
+ * \file
+ *
+ * The flash driver provides the unified interface for flash program operations.
+ *
+ */
+
+#ifndef _FLASHD_
+#define _FLASHD_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP ) ;
+
+extern uint32_t FLASHD_Erase( uint32_t dwAddress ) ;
+
+extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, uint32_t dwSize ) ;
+
+extern uint32_t FLASHD_Lock( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ;
+
+extern uint32_t FLASHD_Unlock( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ;
+
+extern uint32_t FLASHD_IsLocked( uint32_t dwStart, uint32_t dwEnd ) ;
+
+extern uint32_t FLASHD_SetGPNVM( uint8_t gpnvm ) ;
+
+extern uint32_t FLASHD_ClearGPNVM( uint8_t gpnvm ) ;
+
+extern uint32_t FLASHD_IsGPNVMSet( uint8_t gpnvm ) ;
+
+#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet( 0 )
+
+#define FLASHD_SetSecurityBit()   FLASHD_SetGPNVM( 0 )
+
+extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _FLASHD_ */
+

hardware/tools/libchip_sam3s/include/pio.h

@@ -0,0 +1,101 @@
+#ifndef _PIO_
+#define _PIO_
+
+/*
+ *         Headers
+ */
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*
+ *         Global Definitions
+ */
+typedef enum _EPioType
+{
+  PIO_NOT_A_PIN, /* The pin is controlled by the associated signal of peripheral A. */
+  PIO_PERIPH_A, /* The pin is controlled by the associated signal of peripheral A. */
+  PIO_PERIPH_B, /* The pin is controlled by the associated signal of peripheral B. */
+  PIO_PERIPH_C, /* The pin is controlled by the associated signal of peripheral C. */
+  PIO_PERIPH_D, /* The pin is controlled by the associated signal of peripheral D. */
+  PIO_INPUT, /* The pin is an input. */
+  PIO_OUTPUT_0, /* The pin is an output and has a default level of 0. */
+  PIO_OUTPUT_1, /* The pin is an output and has a default level of 1. */
+} EPioType ;
+
+
+/*  Default pin configuration (no attribute). */
+#define PIO_DEFAULT                 (0u << 0)
+/*  The internal pin pull-up is active. */
+#define PIO_PULLUP                  (1u << 0)
+/*  The internal glitch filter is active. */
+#define PIO_DEGLITCH                (1u << 1)
+/*  The pin is open-drain. */
+#define PIO_OPENDRAIN               (1u << 2)
+
+/*  The internal debouncing filter is active. */
+#define PIO_DEBOUNCE                (1u << 3)
+
+/*  Enable additional interrupt modes. */
+#define PIO_IT_AIME                 (1u << 4)
+
+/*  Interrupt High Level/Rising Edge detection is active. */
+#define PIO_IT_RE_OR_HL             (1u << 5)
+/*  Interrupt Edge detection is active. */
+#define PIO_IT_EDGE                 (1u << 6)
+
+/*  Low level interrupt is active */
+#define PIO_IT_LOW_LEVEL            (0               | 0 | PIO_IT_AIME)
+/*  High level interrupt is active */
+#define PIO_IT_HIGH_LEVEL           (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME)
+/*  Falling edge interrupt is active */
+#define PIO_IT_FALL_EDGE            (0               | PIO_IT_EDGE | PIO_IT_AIME)
+/*  Rising edge interrupt is active */
+#define PIO_IT_RISE_EDGE            (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *  The #attribute# field is a bitmask that can either be set to PIO_DEFAULt,
+ *  or combine (using bitwise OR '|') any number of the following constants:
+ *     - PIO_PULLUP
+ *     - PIO_DEGLITCH
+ *     - PIO_DEBOUNCE
+ *     - PIO_OPENDRAIN
+ *     - PIO_IT_LOW_LEVEL
+ *     - PIO_IT_HIGH_LEVEL
+ *     - PIO_IT_FALL_EDGE
+ *     - PIO_IT_RISE_EDGE
+ */
+
+
+/*
+ *         Global Functions
+ */
+extern void PIO_DisableInterrupt( Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_PullUp( Pio* pPio, const uint32_t dwMask, const uint32_t dwPullUpEnable ) ;
+extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff ) ;
+
+extern void PIO_Set( Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_Clear( Pio* pPio, const uint32_t dwMask ) ;
+extern uint32_t PIO_Get( Pio* pPio, const EPioType dwType, const uint32_t dwMask ) ;
+
+extern void PIO_SetPeripheral( Pio* pPio, const EPioType dwType, const uint32_t dwMask ) ;
+extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute ) ;
+extern void PIO_SetOutput( Pio* pPio, uint32_t dwMask, uint32_t dwDefaultValue,
+                                      uint32_t dwMultiDriveEnable, uint32_t dwPullUpEnable ) ;
+
+extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t dwMask, const uint32_t dwAttribute ) ;
+
+extern uint32_t PIO_GetOutputDataStatus( const Pio* pPio, const uint32_t dwMask ) ;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_ */
+

hardware/tools/libchip_sam3s/include/pio_capture.h

@@ -0,0 +1,104 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \page sam3s_ppc SAM3S PIO Parallel Capture
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuration the PIO Parallel Capture peripheral.
+ *
+ *  \section Usage
+ *
+ *  -# Configurate the interrupt for PIOA, can be done by PIO_InitializeInterrupts()
+ *  -# Initialize the PIO Parallel Capture API by filing the SpioCaptureInit structur.
+ *     2 options:
+ *       - alwaysSampling: for sample data with or without take in account ENABLE pins.
+ *       - halfSampling: for sample all data or only one time out of two
+ *  -# Call PIO_CaptureInit() for init and enable the PDC, init the PIO capture.
+ *  -# Call PIO_CaptureEnable() for enable the PIO Parallel Capture.
+ *  -# When an interrupt is received, the PIO_CaptureHandler() is call and the respective
+ *     callback is launch.
+ *  -# When the transfer is complete, the user need to disable interrupt with
+ *     PIO_CaptureDisableIt(). Otherway, the PDC will send an interrupt.
+ *  -# The data receive by the PIO Parallel Capture is inside the buffer passed in the
+ *     PIO_CaptureInit().
+ *
+ */
+
+#ifndef PIO_CAPTURE_H
+#define PIO_CAPTURE_H
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+/** \brief PIO Parallel Capture structure for initialize.
+ *
+ * At the end of the transfer, the callback is invoked by the interrupt handler.
+ */
+typedef struct _SPioCaptureInit {
+
+    /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */
+    uint8_t dsize;
+    /** PDC size, data to be received */
+    uint16_t dPDCsize;
+    /** Data to be received */
+    uint32_t *pData;
+    /** Parallel Capture Mode Always Sampling */
+    uint8_t alwaysSampling;
+    /** Parallel Capture Mode Half Sampling */
+    uint8_t halfSampling;
+    /** Parallel Capture Mode First Sample */
+    uint8_t modeFirstSample;
+    /** Callback function invoked at Mode Data Ready */
+    void (*CbkDataReady)( struct _SPioCaptureInit* );
+    /** Callback function invoked at Mode Overrun Error */
+    void (*CbkOverrun)( struct _SPioCaptureInit* );
+    /** Callback function invoked at End of Reception Transfer */
+    void (*CbkEndReception)( struct _SPioCaptureInit* );
+    /** Callback function invoked at Reception Buffer Full */
+    void (*CbkBuffFull)( struct _SPioCaptureInit* );
+    /** Callback arguments.*/
+    void *pParam;
+
+} SPioCaptureInit ;
+
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+extern void PIO_CaptureDisableIt( uint32_t itToDisable ) ;
+extern void PIO_CaptureEnableIt( uint32_t itToEnable ) ;
+extern void PIO_CaptureEnable( void ) ;
+extern void PIO_CaptureDisable( void ) ;
+extern void PIO_CaptureInit( SPioCaptureInit* pInit ) ;
+
+#endif /* #ifndef PIO_CAPTURE_H */
+

hardware/tools/libchip_sam3s/include/pio_it.h

@@ -0,0 +1,67 @@
+/**
+ *  \file
+ *
+ *  \par Purpose
+ *
+ *  Configuration and handling of interrupts on PIO status changes. The API
+ *  provided here have several advantages over the traditional PIO interrupt
+ *  configuration approach:
+ *     - It is highly portable
+ *     - It automatically demultiplexes interrupts when multiples pins have been
+ *       configured on a single PIO controller
+ *     - It allows a group of pins to share the same interrupt
+ *
+ *  However, it also has several minor drawbacks that may prevent from using it
+ *  in particular applications:
+ *     - It enables the clocks of all PIO controllers
+ *     - PIO controllers all share the same interrupt handler, which does the
+ *       demultiplexing and can be slower than direct configuration
+ *     - It reserves space for a fixed number of interrupts, which can be
+ *       increased by modifying the appropriate constant in pio_it.c.
+ *
+ *  \par Usage
+ *
+ *  -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts()
+ *     with the desired priority (0 ... 7).
+ *  -# Configure a status change interrupt on one or more pin(s) with
+ *     PIO_ConfigureIt().
+ *  -# Enable & disable interrupts on pins using PIO_EnableIt() and
+ *     PIO_DisableIt().
+ */
+
+#ifndef _PIO_IT_
+#define _PIO_IT_
+
+/*
+ *         Headers
+ */
+
+#include "pio.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*
+ *         Global functions
+ */
+
+extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ;
+
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ;
+
+extern void PIO_EnableIt( const Pio* pPio, const uint32_t dwMask ) ;
+extern void PIO_DisableIt( const Pio* pPio, const uint32_t dwMask ) ;
+
+extern void PIO_IT_InterruptHandler( void ) ;
+
+extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ;
+
+extern void PIO_CaptureHandler( void ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PIO_IT_ */
+

hardware/tools/libchip_sam3s/include/pmc.h

@@ -0,0 +1,59 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _PMC_
+#define _PMC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void PMC_EnablePeripheral( uint32_t dwId ) ;
+extern void PMC_DisablePeripheral( uint32_t dwId ) ;
+
+extern void PMC_EnableAllPeripherals( void ) ;
+extern void PMC_DisableAllPeripherals( void ) ;
+
+extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PMC_ */
+

hardware/tools/libchip_sam3s/include/pwmc.h

@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * Interface for configuration the Pulse Width Modulation Controller (PWM) peripheral.
+ *
+ * \par Usage
+ *
+ *    -# Configures PWM clocks A & B to run at the given frequencies using
+ *       \ref PWMC_ConfigureClocks().
+ *    -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), \ref PWMC_ConfigureChannelExt()
+ *       \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and \ref PWMC_SetDeadTime().
+ *    -# Enable & disable channel using \ref PWMC_EnableChannel() and
+ *       \ref PWMC_DisableChannel().
+ *    -# Enable & disable the period interrupt for the given PWM channel using
+ *       \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt().
+ *    -# Enable & disable the selected interrupts sources on a PWMC peripheral
+ *       using  \ref PWMC_EnableIt() and \ref PWMC_DisableIt().
+ *    -# Control syncronous channel using \ref PWMC_ConfigureSyncChannel(),
+ *       \ref PWMC_SetSyncChannelUpdatePeriod() and \ref PWMC_SetSyncChannelUpdateUnlock().
+ *    -# Control PWM override output using \ref PWMC_SetOverrideValue(),
+ *       \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput().
+ *    -# Send data through the transmitter using \ref PWMC_WriteBuffer().
+ *
+ */
+
+#ifndef _PWMC_
+#define _PWMC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void PWMC_ConfigureChannel(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity);
+extern void PWMC_ConfigureChannelExt(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity,
+    uint32_t countEventSelect,
+    uint32_t DTEnable,
+    uint32_t DTHInverte,
+    uint32_t DTLInverte);
+extern void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck);
+extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period);
+extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty);
+extern void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL);
+extern void PWMC_ConfigureSyncChannel( Pwm* pPwm,
+    uint32_t channels,
+    uint32_t updateMode,
+    uint32_t requestMode,
+    uint32_t requestComparisonSelect);
+extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period);
+extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm );
+extern void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel);
+extern void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel);
+extern void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel);
+extern void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel);
+extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);
+extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2);
+extern uint8_t PWMC_WriteBuffer(Pwm *pwmc,
+    void *buffer,
+    uint32_t length);
+extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value);
+extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);
+extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync);
+extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode);
+extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault);
+extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value);
+extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value);
+extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode);
+extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _PWMC_ */
+

hardware/tools/libchip_sam3s/include/rtc.h

@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Real Time Clock (RTC) controller.
+ *
+ */
+
+#ifndef _RTC_
+#define _RTC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+#define RTC_HOUR_BIT_LEN_MASK   0x3F
+#define RTC_MIN_BIT_LEN_MASK    0x7F
+#define RTC_SEC_BIT_LEN_MASK    0x7F
+#define RTC_CENT_BIT_LEN_MASK   0x7F
+#define RTC_YEAR_BIT_LEN_MASK   0xFF
+#define RTC_MONTH_BIT_LEN_MASK  0x1F
+#define RTC_DATE_BIT_LEN_MASK   0x3F
+#define RTC_WEEK_BIT_LEN_MASK   0x07
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ;
+
+extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ;
+
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ;
+
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ;
+
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) ;
+
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;
+
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond ) ;
+
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek ) ;
+
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek ) ;
+
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ;
+
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ;
+
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _RTC_ */
+

hardware/tools/libchip_sam3s/include/rtt.h

@@ -0,0 +1,82 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * Interface for Real Time Timer (RTT) controller.
+ *
+ * \par Usage
+ *
+ * -# Changes the prescaler value of the given RTT and restarts it
+ *    using \ref RTT_SetPrescaler().
+ * -# Get current value of the RTT using \ref RTT_GetTime().
+ * -# Enables the specified RTT interrupt using \ref RTT_EnableIT().
+ * -# Get the status register value of the given RTT using \ref RTT_GetStatus().
+ * -# Configures the RTT to generate an alarm at the given time
+ *    using \ref RTT_SetAlarm().
+ */
+
+#ifndef _RTT_
+#define _RTT_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void RTT_SetPrescaler( Rtt* pRtt, uint16_t wPrescaler ) ;
+
+extern uint32_t RTT_GetTime( Rtt* pRtt ) ;
+
+extern void RTT_EnableIT( Rtt* pRtt, uint32_t dwSources ) ;
+
+extern uint32_t RTT_GetStatus( Rtt *pRtt ) ;
+
+extern void RTT_SetAlarm( Rtt *pRtt, uint32_t dwTime ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef RTT_H */
+

hardware/tools/libchip_sam3s/include/spi.h

@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+#ifndef _SPI_
+#define _SPI_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+
+/**
+ *
+ * Here are several macros which should be used when configuring a SPI
+ * peripheral.
+ *
+ * \section spi_configuration_macros SPI Configuration Macros
+ * - \ref SPI_PCS
+ * - \ref SPI_SCBR
+ * - \ref SPI_DLYBS
+ * - \ref SPI_DLYBCT
+ */
+
+/** Calculate the PCS field value given the chip select NPCS value */
+#define SPI_PCS(npcs)       ((~(1 << npcs) & 0xF) << 16)
+
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
+#define SPI_SCBR(baudrate, masterClock) ((uint32_t) (masterClock / baudrate) << 8)
+
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#define SPI_DLYBS(delay, masterClock) ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
+
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
+#define SPI_DLYBCT(delay, masterClock) ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
+
+/*------------------------------------------------------------------------------ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void SPI_Enable( Spi* spi ) ;
+extern void SPI_Disable( Spi* spi ) ;
+extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ;
+extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ;
+
+extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ;
+extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ;
+
+extern uint32_t SPI_Read( Spi* spi ) ;
+extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ;
+
+extern uint32_t SPI_GetStatus( Spi* spi ) ;
+extern uint32_t SPI_IsFinished( Spi* pSpi ) ;
+
+extern void SPI_PdcEnableTx( Spi* spi ) ;
+extern void SPI_PdcDisableTx( Spi* spi ) ;
+extern void SPI_PdcEnableRx( Spi* spi ) ;
+extern void SPI_PdcDisableRx( Spi* spi ) ;
+
+extern void SPI_PdcSetTx( Spi* spi, void* pvTxBuf, uint32_t dwTxCount, void* pvTxNextBuf, uint32_t dwTxNextCount ) ;
+extern void SPI_PdcSetRx( Spi* spi, void* pvRxBuf, uint32_t dwRxCount, void* pvRxNextBuf, uint32_t dwRxNextCount ) ;
+
+extern uint32_t SPI_WriteBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+
+extern uint32_t SPI_ReadBuffer( Spi* spi, void* pvBuffer, uint32_t dwLength ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SPI_ */
+

hardware/tools/libchip_sam3s/include/spi_pdc.h

@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Implementation of SPI PDC driver.
+ *
+ */
+
+#ifndef _SPI_PDC_
+#define _SPI_PDC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+
+/** An unspecified error has occured.*/
+#define SPID_ERROR          1
+
+/** SPI driver is currently in use.*/
+#define SPID_ERROR_LOCK     2
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+
+/** Calculates the value of the SCBR field of the Chip Select Register given MCK and SPCK.*/
+#define SPID_CSR_SCBR(mck, spck)    (SPI_CSR_SCBR(((mck) / (spck))) )
+
+/** Calculates the value of the DLYBS field of the Chip Select Register given delay in ns and MCK.*/
+#define SPID_CSR_DLYBS(mck, delay)  ( SPI_CSR_DLYBS(((((delay) * ((mck) / 1000000)) / 1000) + 1)) )
+
+/** Calculates the value of the DLYBCT field of the Chip Select Register given delay in ns and MCK.*/
+#define SPID_CSR_DLYBCT(mck, delay) ( SPI_CSR_DLYBCT((((delay) / 32 * ((mck) / 1000000)) / 1000) + 1) )
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+/** SPI transfer complete callback. */
+typedef void (*SpidCallback)( uint8_t, void* ) ;
+
+/** \brief Spi Transfer Request prepared by the application upper layer.
+ *
+ * This structure is sent to the SPI_SendCommand function to start the transfer.
+ * At the end of the transfer, the callback is invoked by the interrupt handler.
+ */
+typedef struct _SpidCmd
+{
+    /** Pointer to the command data. */
+	uint8_t *pCmd;
+    /** Command size in bytes. */
+	uint8_t cmdSize;
+    /** Pointer to the data to be sent. */
+	uint8_t *pData;
+    /** Data size in bytes. */
+	unsigned short dataSize;
+    /** SPI chip select. */
+	uint8_t spiCs;
+    /** Callback function invoked at the end of transfer. */
+	SpidCallback callback;
+    /** Callback arguments. */
+	void *pArgument;
+} SpidCmd ;
+
+/** Constant structure associated with SPI port. This structure prevents
+    client applications to have access in the same time. */
+typedef struct _Spid
+{
+    /** Pointer to SPI Hardware registers */
+	Spi* pSpiHw ;
+    /** SPI Id as defined in the product datasheet */
+	char spiId ;
+    /** Current SpiCommand being processed */
+	SpidCmd *pCurrentCommand ;
+    /** Mutual exclusion semaphore. */
+	volatile char semaphore ;
+} Spid ;
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern uint32_t SPID_Configure( Spid* pSpid, Spi* pSpiHw, uint8_t spiId ) ;
+
+extern void SPID_ConfigureCS( Spid* pSpid, uint32_t dwCS, uint32_t dwCsr ) ;
+	
+extern uint32_t SPID_SendCommand( Spid* pSpid, SpidCmd* pCommand ) ;
+
+extern void SPID_Handler( Spid* pSpid ) ;
+
+extern uint32_t SPID_IsBusy( const Spid* pSpid ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SPI_PDC_ */
+

hardware/tools/libchip_sam3s/include/ssc.h

@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for Synchronous Serial (SSC) controller.
+ *
+ */
+
+#ifndef _SSC_
+#define _SSC_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+extern void SSC_Configure(uint32_t bitRate, uint32_t masterClock);
+extern void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr);
+extern void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr);
+extern void SSC_EnableTransmitter(void);
+extern void SSC_DisableTransmitter(void);
+extern void SSC_EnableReceiver(void);
+extern void SSC_DisableReceiver(void);
+extern void SSC_EnableInterrupts(uint32_t sources);
+extern void SSC_DisableInterrupts(uint32_t sources);
+extern void SSC_Write(uint32_t frame);
+extern uint32_t SSC_Read(void);
+extern uint8_t SSC_WriteBuffer(void *buffer, uint32_t length);
+extern uint8_t SSC_ReadBuffer(void *buffer, uint32_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SSC_ */
+

hardware/tools/libchip_sam3s/include/tc.h

@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ *  \file
+ *
+ *  \section Purpose
+ *
+ *  Interface for configuring and using Timer Counter (TC) peripherals.
+ *
+ *  \section Usage
+ *  -# Optionally, use TC_FindMckDivisor() to let the program find the best
+ *     TCCLKS field value automatically.
+ *  -# Configure a Timer Counter in the desired mode using TC_Configure().
+ *  -# Start or stop the timer clock using TC_Start() and TC_Stop().
+ */
+
+#ifndef _TC_
+#define _TC_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ *         Global functions
+ *------------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ;
+
+extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ;
+
+extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ;
+
+extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TC_ */
+

hardware/tools/libchip_sam3s/include/twi.h

@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Interface for configuration the Two Wire Interface (TWI) peripheral.
+ *
+ */
+
+#ifndef _TWI_
+#define _TWI_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Macros
+ *----------------------------------------------------------------------------*/
+/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/
+#define TWI_STATUS_TXRDY(status) ((status & TWI_SR_TXRDY) == TWI_SR_TXRDY)
+
+/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/
+#define TWI_STATUS_RXRDY(status) ((status & TWI_SR_RXRDY) == TWI_SR_RXRDY)
+
+/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/
+#define TWI_STATUS_TXCOMP(status) ((status & TWI_SR_TXCOMP) == TWI_SR_TXCOMP)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        External function
+ *----------------------------------------------------------------------------*/
+
+extern void TWI_ConfigureMaster(Twi *pTwi, uint32_t twck, uint32_t mck);
+
+extern void TWI_ConfigureSlave(Twi *pTwi, uint8_t slaveAddress);
+
+extern void TWI_Stop(Twi *pTwi);
+
+extern void TWI_StartRead(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize);
+
+extern uint8_t TWI_ReadByte(Twi *pTwi);
+
+extern void TWI_WriteByte(Twi *pTwi, uint8_t byte);
+
+extern void TWI_StartWrite(
+    Twi *pTwi,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t byte);
+
+extern uint8_t TWI_ByteReceived(Twi *pTwi);
+
+extern uint8_t TWI_ByteSent(Twi *pTwi);
+
+extern uint8_t TWI_TransferComplete(Twi *pTwi);
+
+extern void TWI_EnableIt(Twi *pTwi, uint32_t sources);
+
+extern void TWI_DisableIt(Twi *pTwi, uint32_t sources);
+
+extern uint32_t TWI_GetStatus(Twi *pTwi);
+
+extern uint32_t TWI_GetMaskedStatus(Twi *pTwi);
+
+extern void TWI_SendSTOPCondition(Twi *pTwi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _TWI_ */

hardware/tools/libchip_sam3s/include/twid.h

@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _TWID_
+#define _TWID_
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*----------------------------------------------------------------------------
+ *        Definition
+ *----------------------------------------------------------------------------*/
+
+/** TWI driver is currently busy. */
+#define TWID_ERROR_BUSY              1
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Types
+ *----------------------------------------------------------------------------*/
+
+/** \brief TWI driver structure. Holds the internal state of the driver.*/
+typedef struct _Twid
+{
+    /** Pointer to the underlying TWI peripheral.*/
+    Twi *pTwi ;
+    /** Current asynchronous transfer being processed.*/
+    Async *pTransfer ;
+} Twid;
+
+/*----------------------------------------------------------------------------
+ *        Export functions
+ *----------------------------------------------------------------------------*/
+extern void TWID_Initialize( Twid *pTwid, Twi *pTwi ) ;
+
+extern void TWID_Handler( Twid *pTwid ) ;
+
+extern uint8_t TWID_Read(
+    Twid *pTwid,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t *pData,
+    uint32_t num,
+    Async *pAsync);
+
+extern uint8_t TWID_Write(
+    Twid *pTwid,
+    uint8_t address,
+    uint32_t iaddress,
+    uint8_t isize,
+    uint8_t *pData,
+    uint32_t num,
+    Async *pAsync);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //#ifndef TWID_H
+

hardware/tools/libchip_sam3s/include/usart.h

@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \par Purpose
+ *
+ * This module provides several definitions and methods for using an USART
+ * peripheral.
+ *
+ * \par Usage
+ *
+ * -# Enable the USART peripheral clock in the PMC.
+ * -# Enable the required USART PIOs (see pio.h).
+ * -# Configure the UART by calling USART_Configure.
+ * -# Enable the transmitter and/or the receiver of the USART using
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ * -# Send data through the USART using the USART_Write and
+ *    USART_WriteBuffer methods.
+ * -# Receive data from the USART using the USART_Read and
+ *    USART_ReadBuffer functions; the availability of data can be polled
+ *    with USART_IsDataAvailable.
+ * -# Disable the transmitter and/or the receiver of the USART with
+ *    USART_SetTransmitterEnabled and USART_SetReceiverEnabled.
+ */
+
+#ifndef _USART_
+#define _USART_
+
+/*------------------------------------------------------------------------------
+ *         Headers
+ *------------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ *         Definitions
+ *------------------------------------------------------------------------------*/
+
+/** \section USART_mode USART modes
+ * This section lists several common operating modes for an USART peripheral.
+ *
+ * \b Modes
+ * - USART_MODE_ASYNCHRONOUS
+ * - USART_MODE_IRDA
+ */
+
+/** Basic asynchronous mode, i.e. 8 bits no parity.*/
+#define USART_MODE_ASYNCHRONOUS        (US_MR_CHRL_8_BIT | US_MR_PAR_NO)
+
+/** IRDA mode*/
+#define USART_MODE_IRDA                (AT91C_US_USMODE_IRDA | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_FILTER)
+
+/** SPI mode*/
+#define AT91C_US_USMODE_SPIM     0xE
+#define US_SPI_CPOL_0           (0x0<<16)
+#define US_SPI_CPHA_0            (0x0<<8)
+#define US_SPI_CPOL_1            (0x1<<16)
+#define US_SPI_CPHA_1            (0x1<<8)
+#define US_SPI_BPMODE_0    (US_SPI_CPOL_0|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_1    (US_SPI_CPOL_0|US_SPI_CPHA_0)
+#define US_SPI_BPMODE_2    (US_SPI_CPOL_1|US_SPI_CPHA_1)
+#define US_SPI_BPMODE_3    (US_SPI_CPOL_1|US_SPI_CPHA_0)
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------*/
+/*         Exported functions                                                   */
+/*------------------------------------------------------------------------------*/
+
+extern void USART_Configure( Usart *usart, uint32_t mode, uint32_t baudrate, uint32_t masterClock ) ;
+extern uint32_t USART_GetStatus( Usart *usart ) ;
+extern void USART_EnableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_DisableIt( Usart *usart,uint32_t mode ) ;
+extern void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ;
+
+extern void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_WriteBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ;
+
+extern uint8_t USART_ReadBuffer( Usart *usart, void *buffer, uint32_t size ) ;
+
+extern uint8_t USART_IsDataAvailable( Usart *usart ) ;
+
+extern void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter);
+
+extern void USART_PutChar( Usart *usart, uint8_t c ) ;
+
+extern uint32_t USART_IsRxReady( Usart *usart ) ;
+
+extern uint8_t USART_GetChar( Usart *usart ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _USART_ */
+

hardware/tools/libchip_sam3s/include/wdt.h

@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * \section Purpose
+ * Interface for Watchdog Timer (WDT) controller.
+ *
+ * \section Usage
+ * -# Enable watchdog with given mode using \ref WDT_Enable().
+ * -# Disable watchdog using \ref WDT_Disable()
+ * -# Restart the watchdog using \ref WDT_Restart().
+ * -# Get watchdog status using \ref  WDT_GetStatus().
+ * -# Caculate watchdog period value using \ref WDT_GetPeriod().
+ */
+
+#ifndef _WDT_
+#define _WDT_
+
+#include "chip.h"
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ;
+
+extern void WDT_Disable( Wdt* pWDT ) ;
+
+extern void WDT_Restart( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetStatus( Wdt* pWDT ) ;
+
+extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _WDT_ */
+

hardware/tools/libchip_sam3s/lib/libchip_sam3s4_gcc_dbg.a.txt

@@ -0,0 +1,345 @@
+
+acc.o:
+00000000 T ACC_Configure
+00000000 T ACC_GetComparisionResult
+00000000 T ACC_SetComparisionPair
+00000030 r __FUNCTION__.5686
+         U __assert_func
+
+adc.o:
+00000000 T ADC_CfgChannelMode
+00000000 T ADC_CfgLowRes
+00000000 T ADC_CfgPowerSave
+00000000 T ADC_CfgTiming
+00000000 T ADC_CfgTrigering
+00000000 T ADC_GetConvertedData
+00000000 T ADC_Initialize
+00000000 T ADC_IsChannelInterruptStatusSet
+00000000 T ADC_IsInterruptMasked
+00000000 T ADC_IsStatusSet
+00000000 T ADC_ReadBuffer
+00000000 T ADC_SetCompareChannel
+00000000 T ADC_SetCompareMode
+00000000 T ADC_SetComparisonWindow
+00000000 T ADC_cfgFrequency
+00000098 r __FUNCTION__.5707
+00000080 r __FUNCTION__.5713
+00000068 r __FUNCTION__.5718
+         U __assert_func
+00000000 d adwValue.5706
+00000000 t calcul_startup
+
+async.o:
+00000000 T ASYNC_IsFinished
+
+crccu.o:
+00000000 T CRCCU_ComputeCrc
+00000000 T CRCCU_Configure
+00000000 T CRCCU_ResetCrcValue
+
+dacc.o:
+00000000 T DACC_Initialize
+00000000 T DACC_SetConversionData
+00000000 T DACC_WriteBuffer
+00000034 r __FUNCTION__.5690
+         U __assert_func
+
+efc.o:
+00000000 T EFC_ComputeAddress
+00000000 T EFC_DisableFrdyIt
+00000000 T EFC_EnableFrdyIt
+00000000 T EFC_GetResult
+00000000 T EFC_GetStatus
+00000000 T EFC_PerformCommand
+00000000 T EFC_SetWaitState
+00000000 T EFC_StartCommand
+00000000 T EFC_TranslateAddress
+00000000 b IAP_PerformCommand.6331
+00000134 r __FUNCTION__.6293
+00000120 r __FUNCTION__.6301
+0000010c r __FUNCTION__.6313
+         U __assert_func
+
+exceptions.o:
+
+flashd.o:
+00000000 t ComputeLockRange
+         U EFC_ComputeAddress
+         U EFC_DisableFrdyIt
+         U EFC_GetResult
+         U EFC_PerformCommand
+         U EFC_SetWaitState
+         U EFC_StartCommand
+         U EFC_TranslateAddress
+00000000 T FLASHD_ClearGPNVM
+00000000 T FLASHD_Erase
+00000000 T FLASHD_Initialize
+00000000 T FLASHD_IsGPNVMSet
+00000000 T FLASHD_IsLocked
+00000000 T FLASHD_Lock
+00000000 T FLASHD_ReadUniqueID
+00000000 T FLASHD_SetGPNVM
+00000000 T FLASHD_Unlock
+00000000 T FLASHD_Write
+00000198 r __FUNCTION__.6049
+00000188 r __FUNCTION__.6065
+00000178 r __FUNCTION__.6117
+00000164 r __FUNCTION__.6126
+00000154 r __FUNCTION__.6130
+00000140 r __FUNCTION__.6134
+0000012c r __FUNCTION__.6139
+         U __assert_func
+00000000 b _adwPageBuffer
+00000000 d _aucPageBuffer
+00000100 b _dwUseIAP
+         U memcpy
+
+pio.o:
+00000000 T PIO_Clear
+00000000 T PIO_Configure
+00000000 T PIO_DisableInterrupt
+00000000 T PIO_Get
+00000000 T PIO_GetOutputDataStatus
+00000000 T PIO_PullUp
+00000000 T PIO_Set
+00000000 T PIO_SetDebounceFilter
+00000000 T PIO_SetInput
+00000000 T PIO_SetOutput
+00000000 T PIO_SetPeripheral
+         U PMC_EnablePeripheral
+
+pio_capture.o:
+00000000 T PIO_CaptureDisable
+00000000 T PIO_CaptureDisableIt
+00000000 T PIO_CaptureEnable
+00000000 T PIO_CaptureEnableIt
+00000000 T PIO_CaptureHandler
+00000000 T PIO_CaptureInit
+         U PMC_EnablePeripheral
+00000000 b _PioCaptureCopy
+00000088 r __FUNCTION__.6287
+         U __assert_func
+
+pmc.o:
+00000000 T PMC_DisableAllPeripherals
+00000000 T PMC_DisablePeripheral
+00000000 T PMC_EnableAllPeripherals
+00000000 T PMC_EnablePeripheral
+00000000 T PMC_IsPeriphEnabled
+00000048 r __FUNCTION__.5680
+00000030 r __FUNCTION__.5684
+0000001c r __FUNCTION__.5706
+         U __assert_func
+
+pwmc.o:
+00000284 r C.2.6943
+00000000 t FindClockConfiguration
+00000000 T PWMC_ConfigureChannel
+00000000 T PWMC_ConfigureChannelExt
+00000000 T PWMC_ConfigureClocks
+00000000 T PWMC_ConfigureComparisonUnit
+00000000 T PWMC_ConfigureEventLineMode
+00000000 T PWMC_ConfigureSyncChannel
+00000000 T PWMC_DisableChannel
+00000000 T PWMC_DisableChannelIt
+00000000 T PWMC_DisableIt
+00000000 T PWMC_DisableOverrideOutput
+00000000 T PWMC_EnableChannel
+00000000 T PWMC_EnableChannelIt
+00000000 T PWMC_EnableFaultProtection
+00000000 T PWMC_EnableIt
+00000000 T PWMC_EnableOverrideOutput
+00000000 T PWMC_FaultClear
+00000000 T PWMC_SetDeadTime
+00000000 T PWMC_SetDutyCycle
+00000000 T PWMC_SetFaultMode
+00000000 T PWMC_SetFaultProtectionValue
+00000000 T PWMC_SetOverrideValue
+00000000 T PWMC_SetPeriod
+00000000 T PWMC_SetSyncChannelUpdatePeriod
+00000000 T PWMC_SetSyncChannelUpdateUnlock
+00000000 T PWMC_WriteBuffer
+000002b0 r __FUNCTION__.5684
+0000026c r __FUNCTION__.5695
+00000250 r __FUNCTION__.5710
+00000238 r __FUNCTION__.5721
+00000224 r __FUNCTION__.5732
+00000210 r __FUNCTION__.5739
+000001f0 r __FUNCTION__.5821
+000001d4 r __FUNCTION__.5827
+         U __assert_func
+
+rtc.o:
+00000000 T RTC_ClearSCCR
+00000000 T RTC_DisableIt
+00000000 T RTC_EnableIt
+00000000 T RTC_GetDate
+00000000 T RTC_GetHourMode
+00000000 T RTC_GetSR
+00000000 T RTC_GetTime
+00000000 T RTC_SetDate
+00000000 T RTC_SetDateAlarm
+00000000 T RTC_SetHourMode
+00000000 T RTC_SetTime
+00000000 T RTC_SetTimeAlarm
+00000074 r __FUNCTION__.5681
+00000064 r __FUNCTION__.5690
+00000054 r __FUNCTION__.5695
+         U __assert_func
+
+rtt.o:
+00000000 T RTT_EnableIT
+00000000 T RTT_GetStatus
+00000000 T RTT_GetTime
+00000000 T RTT_SetAlarm
+00000000 T RTT_SetPrescaler
+00000048 r __FUNCTION__.5688
+00000038 r __FUNCTION__.5696
+         U __assert_func
+
+spi.o:
+         U PMC_EnablePeripheral
+00000000 T SPI_Configure
+00000000 T SPI_ConfigureNPCS
+00000000 T SPI_Disable
+00000000 T SPI_DisableIt
+00000000 T SPI_Enable
+00000000 T SPI_EnableIt
+00000000 T SPI_GetStatus
+00000000 T SPI_IsFinished
+00000000 T SPI_PdcDisableRx
+00000000 T SPI_PdcDisableTx
+00000000 T SPI_PdcEnableRx
+00000000 T SPI_PdcEnableTx
+00000000 T SPI_PdcSetRx
+00000000 T SPI_PdcSetTx
+00000000 T SPI_Read
+00000000 T SPI_ReadBuffer
+00000000 T SPI_Write
+00000000 T SPI_WriteBuffer
+
+spi_pdc.o:
+         U PMC_DisablePeripheral
+         U PMC_EnablePeripheral
+00000000 T SPID_Configure
+00000000 T SPID_ConfigureCS
+00000000 T SPID_Handler
+00000000 T SPID_IsBusy
+00000000 T SPID_SendCommand
+         U SPI_Configure
+         U SPI_ConfigureNPCS
+         U SPI_DisableIt
+         U SPI_Enable
+         U SPI_EnableIt
+         U SPI_PdcDisableRx
+         U SPI_PdcDisableTx
+         U SPI_PdcEnableRx
+         U SPI_PdcEnableTx
+         U SPI_PdcSetRx
+         U SPI_PdcSetTx
+
+ssc.o:
+00000000 T SSC_Configure
+00000000 T SSC_ConfigureReceiver
+00000000 T SSC_ConfigureTransmitter
+00000000 T SSC_DisableInterrupts
+00000000 T SSC_DisableReceiver
+00000000 T SSC_DisableTransmitter
+00000000 T SSC_EnableInterrupts
+00000000 T SSC_EnableReceiver
+00000000 T SSC_EnableTransmitter
+00000000 T SSC_Read
+00000000 T SSC_ReadBuffer
+00000000 T SSC_Write
+00000000 T SSC_WriteBuffer
+
+tc.o:
+00000000 T TC_Configure
+00000000 T TC_FindMckDivisor
+00000000 T TC_Start
+00000000 T TC_Stop
+0000006c r __FUNCTION__.5683
+00000060 r __FUNCTION__.5689
+00000058 r __FUNCTION__.5695
+         U __assert_func
+
+twi.o:
+00000000 T TWI_ByteReceived
+00000000 T TWI_ByteSent
+00000000 T TWI_ConfigureMaster
+00000000 T TWI_ConfigureSlave
+00000000 T TWI_DisableIt
+00000000 T TWI_EnableIt
+00000000 T TWI_GetMaskedStatus
+00000000 T TWI_GetStatus
+00000000 T TWI_ReadByte
+00000000 T TWI_SendSTOPCondition
+00000000 T TWI_StartRead
+00000000 T TWI_StartWrite
+00000000 T TWI_Stop
+00000000 T TWI_TransferComplete
+00000000 T TWI_WriteByte
+00000180 r __FUNCTION__.6275
+0000016c r __FUNCTION__.6290
+00000160 r __FUNCTION__.6294
+00000150 r __FUNCTION__.6301
+00000140 r __FUNCTION__.6305
+00000130 r __FUNCTION__.6310
+00000120 r __FUNCTION__.6318
+00000110 r __FUNCTION__.6332
+00000100 r __FUNCTION__.6337
+000000f0 r __FUNCTION__.6341
+000000dc r __FUNCTION__.6346
+000000c4 r __FUNCTION__.6350
+         U __assert_func
+
+twid.o:
+00000000 T TWID_Handler
+00000000 T TWID_Initialize
+00000000 T TWID_Read
+00000000 T TWID_Write
+         U TWI_ByteReceived
+         U TWI_ByteSent
+         U TWI_DisableIt
+         U TWI_EnableIt
+         U TWI_GetMaskedStatus
+         U TWI_ReadByte
+         U TWI_SendSTOPCondition
+         U TWI_StartRead
+         U TWI_StartWrite
+         U TWI_Stop
+         U TWI_TransferComplete
+         U TWI_WriteByte
+000000b4 r __FUNCTION__.6280
+000000a4 r __FUNCTION__.6287
+00000098 r __FUNCTION__.6300
+0000008c r __FUNCTION__.6322
+         U __assert_func
+
+usart.o:
+00000000 T USART_Configure
+00000000 T USART_DisableIt
+00000000 T USART_EnableIt
+00000000 T USART_GetChar
+00000000 T USART_GetStatus
+00000000 T USART_IsDataAvailable
+00000000 T USART_IsRxReady
+00000000 T USART_PutChar
+00000000 T USART_Read
+00000000 T USART_ReadBuffer
+00000000 T USART_SetIrdaFilter
+00000000 T USART_SetReceiverEnabled
+00000000 T USART_SetTransmitterEnabled
+00000000 T USART_Write
+00000000 T USART_WriteBuffer
+00000024 r __FUNCTION__.6074
+         U __assert_func
+
+wdt.o:
+00000000 T WDT_Disable
+00000000 T WDT_Enable
+00000000 T WDT_GetPeriod
+00000000 T WDT_GetStatus
+00000000 T WDT_Restart
+
+core_cm3.o:

hardware/tools/libchip_sam3s/lib/libchip_sam3s4_gcc_rel.a.txt

@@ -0,0 +1,340 @@
+
+acc.o:
+00000000 T ACC_Configure
+00000000 T ACC_GetComparisionResult
+00000000 T ACC_SetComparisionPair
+00000000 r __FUNCTION__.5686
+         U __assert_func
+
+adc.o:
+00000000 T ADC_CfgChannelMode
+00000000 T ADC_CfgLowRes
+00000000 T ADC_CfgPowerSave
+00000000 T ADC_CfgTiming
+00000000 T ADC_CfgTrigering
+00000000 T ADC_GetConvertedData
+00000000 T ADC_Initialize
+00000000 T ADC_IsChannelInterruptStatusSet
+00000000 T ADC_IsInterruptMasked
+00000000 T ADC_IsStatusSet
+00000000 T ADC_ReadBuffer
+00000000 T ADC_SetCompareChannel
+00000000 T ADC_SetCompareMode
+00000000 T ADC_SetComparisonWindow
+00000000 T ADC_cfgFrequency
+00000000 r __FUNCTION__.5713
+00000015 r __FUNCTION__.5718
+         U __assert_func
+
+async.o:
+00000000 T ASYNC_IsFinished
+
+crccu.o:
+00000000 T CRCCU_ComputeCrc
+00000000 T CRCCU_Configure
+00000000 T CRCCU_ResetCrcValue
+
+dacc.o:
+00000000 T DACC_Initialize
+00000000 T DACC_SetConversionData
+00000000 T DACC_WriteBuffer
+00000000 r __FUNCTION__.5690
+         U __assert_func
+
+efc.o:
+00000000 T EFC_ComputeAddress
+00000000 T EFC_DisableFrdyIt
+00000000 T EFC_EnableFrdyIt
+00000000 T EFC_GetResult
+00000000 T EFC_GetStatus
+00000000 T EFC_PerformCommand
+00000000 T EFC_SetWaitState
+00000000 T EFC_StartCommand
+00000000 T EFC_TranslateAddress
+00000000 b IAP_PerformCommand.6322
+00000000 r __FUNCTION__.6284
+00000015 r __FUNCTION__.6292
+00000028 r __FUNCTION__.6304
+         U __assert_func
+
+exceptions.o:
+
+flashd.o:
+00000000 t ComputeLockRange
+         U EFC_ComputeAddress
+         U EFC_DisableFrdyIt
+         U EFC_GetResult
+         U EFC_PerformCommand
+         U EFC_SetWaitState
+         U EFC_StartCommand
+         U EFC_TranslateAddress
+00000000 T FLASHD_ClearGPNVM
+00000000 T FLASHD_Erase
+00000000 T FLASHD_Initialize
+00000000 T FLASHD_IsGPNVMSet
+00000000 T FLASHD_IsLocked
+00000000 T FLASHD_Lock
+00000000 T FLASHD_ReadUniqueID
+00000000 T FLASHD_SetGPNVM
+00000000 T FLASHD_Unlock
+00000000 T FLASHD_Write
+00000000 r __FUNCTION__.6056
+0000000d r __FUNCTION__.6108
+0000001d r __FUNCTION__.6117
+0000002f r __FUNCTION__.6121
+0000003f r __FUNCTION__.6125
+00000051 r __FUNCTION__.6130
+         U __assert_func
+00000004 b _adwPageBuffer
+00000000 b _dwUseIAP
+         U memcpy
+
+pio.o:
+00000000 T PIO_Clear
+00000000 T PIO_Configure
+00000000 T PIO_DisableInterrupt
+00000000 T PIO_Get
+00000000 T PIO_GetOutputDataStatus
+00000000 T PIO_PullUp
+00000000 T PIO_Set
+00000000 T PIO_SetDebounceFilter
+00000000 T PIO_SetInput
+00000000 T PIO_SetOutput
+00000000 T PIO_SetPeripheral
+         U PMC_EnablePeripheral
+
+pio_capture.o:
+00000000 T PIO_CaptureDisable
+00000000 T PIO_CaptureDisableIt
+00000000 T PIO_CaptureEnable
+00000000 T PIO_CaptureEnableIt
+00000000 T PIO_CaptureHandler
+00000000 T PIO_CaptureInit
+         U PMC_EnablePeripheral
+00000000 b _PioCaptureCopy
+00000000 r __FUNCTION__.6278
+         U __assert_func
+
+pmc.o:
+00000000 T PMC_DisableAllPeripherals
+00000000 T PMC_DisablePeripheral
+00000000 T PMC_EnableAllPeripherals
+00000000 T PMC_EnablePeripheral
+00000000 T PMC_IsPeriphEnabled
+00000000 r __FUNCTION__.5680
+00000015 r __FUNCTION__.5684
+0000002b r __FUNCTION__.5706
+         U __assert_func
+
+pwmc.o:
+00000000 r C.1.6861
+00000000 t FindClockConfiguration
+00000000 T PWMC_ConfigureChannel
+00000000 T PWMC_ConfigureChannelExt
+00000000 T PWMC_ConfigureClocks
+00000000 T PWMC_ConfigureComparisonUnit
+00000000 T PWMC_ConfigureEventLineMode
+00000000 T PWMC_ConfigureSyncChannel
+00000000 T PWMC_DisableChannel
+00000000 T PWMC_DisableChannelIt
+00000000 T PWMC_DisableIt
+00000000 T PWMC_DisableOverrideOutput
+00000000 T PWMC_EnableChannel
+00000000 T PWMC_EnableChannelIt
+00000000 T PWMC_EnableFaultProtection
+00000000 T PWMC_EnableIt
+00000000 T PWMC_EnableOverrideOutput
+00000000 T PWMC_FaultClear
+00000000 T PWMC_SetDeadTime
+00000000 T PWMC_SetDutyCycle
+00000000 T PWMC_SetFaultMode
+00000000 T PWMC_SetFaultProtectionValue
+00000000 T PWMC_SetOverrideValue
+00000000 T PWMC_SetPeriod
+00000000 T PWMC_SetSyncChannelUpdatePeriod
+00000000 T PWMC_SetSyncChannelUpdateUnlock
+00000000 T PWMC_WriteBuffer
+0000002c r __FUNCTION__.5684
+00000043 r __FUNCTION__.5695
+00000059 r __FUNCTION__.5710
+00000072 r __FUNCTION__.5721
+00000087 r __FUNCTION__.5732
+00000099 r __FUNCTION__.5739
+000000aa r __FUNCTION__.5821
+000000c7 r __FUNCTION__.5827
+         U __assert_func
+
+rtc.o:
+00000000 T RTC_ClearSCCR
+00000000 T RTC_DisableIt
+00000000 T RTC_EnableIt
+00000000 T RTC_GetDate
+00000000 T RTC_GetHourMode
+00000000 T RTC_GetSR
+00000000 T RTC_GetTime
+00000000 T RTC_SetDate
+00000000 T RTC_SetDateAlarm
+00000000 T RTC_SetHourMode
+00000000 T RTC_SetTime
+00000000 T RTC_SetTimeAlarm
+00000000 r __FUNCTION__.5681
+00000010 r __FUNCTION__.5690
+0000001d r __FUNCTION__.5695
+         U __assert_func
+
+rtt.o:
+00000000 T RTT_EnableIT
+00000000 T RTT_GetStatus
+00000000 T RTT_GetTime
+00000000 T RTT_SetAlarm
+00000000 T RTT_SetPrescaler
+00000000 r __FUNCTION__.5688
+0000000d r __FUNCTION__.5696
+         U __assert_func
+
+spi.o:
+         U PMC_EnablePeripheral
+00000000 T SPI_Configure
+00000000 T SPI_ConfigureNPCS
+00000000 T SPI_Disable
+00000000 T SPI_DisableIt
+00000000 T SPI_Enable
+00000000 T SPI_EnableIt
+00000000 T SPI_GetStatus
+00000000 T SPI_IsFinished
+00000000 T SPI_PdcDisableRx
+00000000 T SPI_PdcDisableTx
+00000000 T SPI_PdcEnableRx
+00000000 T SPI_PdcEnableTx
+00000000 T SPI_PdcSetRx
+00000000 T SPI_PdcSetTx
+00000000 T SPI_Read
+00000000 T SPI_ReadBuffer
+00000000 T SPI_Write
+00000000 T SPI_WriteBuffer
+
+spi_pdc.o:
+         U PMC_DisablePeripheral
+         U PMC_EnablePeripheral
+00000000 T SPID_Configure
+00000000 T SPID_ConfigureCS
+00000000 T SPID_Handler
+00000000 T SPID_IsBusy
+00000000 T SPID_SendCommand
+         U SPI_Configure
+         U SPI_ConfigureNPCS
+         U SPI_DisableIt
+         U SPI_Enable
+         U SPI_EnableIt
+         U SPI_PdcDisableRx
+         U SPI_PdcDisableTx
+         U SPI_PdcEnableRx
+         U SPI_PdcEnableTx
+         U SPI_PdcSetRx
+         U SPI_PdcSetTx
+
+ssc.o:
+00000000 T SSC_Configure
+00000000 T SSC_ConfigureReceiver
+00000000 T SSC_ConfigureTransmitter
+00000000 T SSC_DisableInterrupts
+00000000 T SSC_DisableReceiver
+00000000 T SSC_DisableTransmitter
+00000000 T SSC_EnableInterrupts
+00000000 T SSC_EnableReceiver
+00000000 T SSC_EnableTransmitter
+00000000 T SSC_Read
+00000000 T SSC_ReadBuffer
+00000000 T SSC_Write
+00000000 T SSC_WriteBuffer
+
+tc.o:
+00000000 T TC_Configure
+00000000 T TC_FindMckDivisor
+00000000 T TC_Start
+00000000 T TC_Stop
+00000000 r __FUNCTION__.5683
+0000000d r __FUNCTION__.5689
+00000016 r __FUNCTION__.5695
+         U __assert_func
+
+twi.o:
+00000000 T TWI_ByteReceived
+00000000 T TWI_ByteSent
+00000000 T TWI_ConfigureMaster
+00000000 T TWI_ConfigureSlave
+00000000 T TWI_DisableIt
+00000000 T TWI_EnableIt
+00000000 T TWI_GetMaskedStatus
+00000000 T TWI_GetStatus
+00000000 T TWI_ReadByte
+00000000 T TWI_SendSTOPCondition
+00000000 T TWI_StartRead
+00000000 T TWI_StartWrite
+00000000 T TWI_Stop
+00000000 T TWI_TransferComplete
+00000000 T TWI_WriteByte
+00000000 r __FUNCTION__.6266
+00000014 r __FUNCTION__.6281
+00000027 r __FUNCTION__.6285
+00000030 r __FUNCTION__.6292
+0000003e r __FUNCTION__.6296
+0000004b r __FUNCTION__.6301
+00000059 r __FUNCTION__.6309
+00000068 r __FUNCTION__.6323
+00000075 r __FUNCTION__.6328
+00000083 r __FUNCTION__.6332
+00000091 r __FUNCTION__.6337
+000000a5 r __FUNCTION__.6341
+         U __assert_func
+
+twid.o:
+00000000 T TWID_Handler
+00000000 T TWID_Initialize
+00000000 T TWID_Read
+00000000 T TWID_Write
+         U TWI_ByteReceived
+         U TWI_ByteSent
+         U TWI_DisableIt
+         U TWI_EnableIt
+         U TWI_GetMaskedStatus
+         U TWI_ReadByte
+         U TWI_SendSTOPCondition
+         U TWI_StartRead
+         U TWI_StartWrite
+         U TWI_Stop
+         U TWI_TransferComplete
+         U TWI_WriteByte
+00000000 r __FUNCTION__.6271
+00000010 r __FUNCTION__.6278
+0000001d r __FUNCTION__.6291
+00000027 r __FUNCTION__.6313
+         U __assert_func
+
+usart.o:
+00000000 T USART_Configure
+00000000 T USART_DisableIt
+00000000 T USART_EnableIt
+00000000 T USART_GetChar
+00000000 T USART_GetStatus
+00000000 T USART_IsDataAvailable
+00000000 T USART_IsRxReady
+00000000 T USART_PutChar
+00000000 T USART_Read
+00000000 T USART_ReadBuffer
+00000000 T USART_SetIrdaFilter
+00000000 T USART_SetReceiverEnabled
+00000000 T USART_SetTransmitterEnabled
+00000000 T USART_Write
+00000000 T USART_WriteBuffer
+00000000 r __FUNCTION__.6065
+         U __assert_func
+
+wdt.o:
+00000000 T WDT_Disable
+00000000 T WDT_Enable
+00000000 T WDT_GetPeriod
+00000000 T WDT_GetStatus
+00000000 T WDT_Restart
+
+core_cm3.o:

hardware/tools/libchip_sam3s/source/acc.c

@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup acc_module Working with ACC
+ * The ACC driver provides the interface to configure and use the ACC peripheral.\n
+ *
+ * It applies comparison on two inputs and gives a compare output.
+ *
+ * To Enable a ACC Comparison,the user has to follow these few steps:
+ * <ul>
+ * <li> Enable ACC peripheral clock by setting the corresponding bit in PMC_PCER1
+ *      (PMC Peripheral Clock Enable Register 1)
+ * </li>
+ * <li> Reset the controller by asserting ACC_CR_SWRST in ACC_CR(ACC Control Register)
+ </li>
+ * <li> Configure the mode as following steps:  </li>
+ * -#   Select inputs for SELMINUS and SELPLUS in ACC_MR (ACC Mode Register).
+ * -#   Enable Analog Comparator by setting ACEN in ACC_MR.
+ * -#   Configure Edge Type to detect different compare output.
+ * </li>
+ * <li> Wait until the automatic mask period expires by polling MASK bit in
+ *      ACC_ISR.
+ * </ul>
+ *
+ * For more accurate information, please look at the ACC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref acc.c\n
+ * \ref acc.h\n
+ */
+/*@{*/
+/*@}*/
+/**
+ * \file
+ *
+ * Implementation of Analog Comparator Controller (ACC).
+ *
+ */
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Initialize the ACC controller
+ *
+ * \param pAcc Pointer to an Acc instance.
+ * \param idAcc ACC identifier
+ * \param ucSelplus input connected to inp, 0~7
+ * \param ucSelminus input connected to inm,0~7
+ * \param wAc_en Analog comprator enabled/disabled
+ * \param wEdge CF flag triggering mode
+ * \param wInvert INVert comparator output,use pattern defined in the device header file
+ */
+extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, uint8_t ucSelminus,
+                           uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert )
+{
+    /* Enable peripheral clock*/
+    PMC->PMC_PCER1 = 1 << (idAcc - 32) ;
+
+    /*  Reset the controller */
+    pAcc->ACC_CR |= ACC_CR_SWRST ;
+
+    /*  Write to the MR register */
+    ACC_CfgModeReg( pAcc,
+                    ( (ucSelplus<<ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk ) |
+                    ( (ucSelminus<<ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk ) |
+                    ( (wAc_en<<8) & ACC_MR_ACEN ) |
+                    ( (wEdge<<ACC_MR_EDGETYP_Pos) & ACC_MR_EDGETYP_Msk ) |
+                    ( (wInvert<<12) & ACC_MR_INV ) ) ;
+    /* set hysteresis and current option*/
+    pAcc->ACC_ACR = (ACC_ACR_ISEL_HISP | ((0x01 << ACC_ACR_HYST_Pos) & ACC_ACR_HYST_Msk));
+
+    /* Automatic Output Masking Period*/
+    while ( pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK ) ;
+}
+
+/**
+ * Return the Channel Converted Data
+ * \param pAcc Pointer to an Acc instance.
+ * \param selplus input applied on ACC SELPLUS
+ * \param selminus input applied on ACC SELMINUS
+ */
+extern void ACC_SetComparisionPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus )
+{
+    uint32_t dwTemp ;
+
+    assert( ucSelplus < 8 && ucSelminus < 8 ) ;
+
+    dwTemp = pAcc->ACC_MR ;
+
+    pAcc->ACC_MR = dwTemp & (uint32_t) ((~ACC_MR_SELMINUS_Msk) & (~ACC_MR_SELPLUS_Msk));
+
+    pAcc->ACC_MR |= ( ((ucSelplus << ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk) |
+                      ((ucSelminus << ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk) ) ;
+
+}
+/**
+ * Return Comparison Result
+ * \param pAcc Pointer to an Acc instance.
+ * \param status value of ACC_ISR
+ */
+extern uint32_t ACC_GetComparisionResult( Acc *pAcc, uint32_t dwStatus )
+{
+    uint32_t dwTemp = pAcc->ACC_MR ;
+
+    if ( (dwTemp & ACC_MR_INV) == ACC_MR_INV )
+    {
+        if ( dwStatus & ACC_ISR_SCO )
+        {
+            return 0 ; /* inn>inp*/
+        }
+        else
+        {
+            return 1 ;/* inp>inn*/
+        }
+    }
+    else
+    {
+        if ( dwStatus & ACC_ISR_SCO )
+        {
+            return 1 ; /* inp>inn*/
+        }
+        else
+        {
+            return 0 ;/* inn>inp*/
+        }
+    }
+}
+

hardware/tools/libchip_sam3s/source/adc.c

@@ -0,0 +1,320 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup adc_module Working with ADC
+ * The ADC driver provides the interface to configure and use the ADC peripheral.
+ * \n
+ *
+ * It converts the analog input to digital format. The converted result could be
+ * 12bit or 10bit. The ADC supports up to 16 analog lines.
+ *
+ * To Enable a ADC conversion,the user has to follow these few steps:
+ * <ul>
+ * <li> Select an appropriate reference voltage on ADVREF   </li>
+ * <li> Configure the ADC according to its requirements and special needs,which
+ * could be  broken down into several parts:
+ * -#   Select the resolution by setting or clearing ADC_MR_LOWRES bit in
+ *      ADC_MR (Mode Register)
+ * -#   Set ADC clock by setting ADC_MR_PRESCAL bits in ADC_MR, the clock is
+ *      calculated with ADCClock = MCK / ( (PRESCAL+1) * 2 )
+ * -#   Set Startup Time,Tracking Clock cycles and Transfer Clock respectively
+ *      in ADC_MR.
+ </li>
+ * <li> Start conversion by setting ADC_CR_START in ADC_CR. </li>
+ * </ul>
+ *
+ * For more accurate information, please look at the ADC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref adc.c\n
+ * \ref adc.h\n
+ */
+/*@{*/
+/*@}*/
+/**
+ * \file
+ *
+ * Implementation of Analog-to-Digital Converter (ADC).
+ *
+ */
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Initialize the ADC controller
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param idAdc ADC Index
+ * \param trgEn trigger mode, software or Hardware
+ * \param trgSel hardware trigger selection
+ * \param sleepMode sleep mode selection
+ * \param resolution resolution selection 10 bits or 12 bits
+ * \param mckClock value of MCK in Hz
+ * \param adcClock value of the ADC clock in Hz
+ * \param startup value of the start up time (in ADCClock) (see datasheet)
+ * \param tracking Tracking Time (in ADCClock cycle)
+ */
+extern void ADC_Initialize( Adc* pAdc, uint32_t idAdc )
+{
+    /* Enable peripheral clock*/
+    PMC->PMC_PCER0 = 1 << idAdc;
+
+    /*  Reset the controller */
+    pAdc->ADC_CR = ADC_CR_SWRST;
+
+    /* Reset Mode Register set to default */
+    /* TrackTime set to 0 */
+    /* Transfer set to 1 */
+    /* settling set to 3 */
+    pAdc->ADC_MR = ADC_MR_TRANSFER(1) | ADC_MR_TRACKTIM(0) | ADC_MR_SETTLING(3);
+}
+
+/**
+ * \brief Initialize the ADC Timing
+ */
+extern void ADC_CfgTiming( Adc* pAdc, uint32_t tracking, uint32_t settling, uint32_t transfer )
+{
+    pAdc->ADC_MR = ADC_MR_TRANSFER( transfer )
+                 | ADC_MR_SETTLING( settling )
+                 | ADC_MR_TRACKTIM( tracking ) ;
+}
+
+/**
+ * \brief Initialize the ADC Timing
+ */
+extern void ADC_cfgFrequency( Adc* pAdc, uint32_t startup, uint32_t prescal )
+{
+    pAdc->ADC_MR |= ADC_MR_PRESCAL( prescal )
+                 | ( (startup<<ADC_MR_STARTUP_Pos) & ADC_MR_STARTUP_Msk);
+}
+
+/**
+ * \brief Initialize the ADC Trigering
+ */
+extern void ADC_CfgTrigering( Adc* pAdc, uint32_t trgEn, uint32_t trgSel, uint32_t freeRun )
+{
+    pAdc->ADC_MR |= ((trgEn<<0) & ADC_MR_TRGEN)
+                    | ((trgSel<<ADC_MR_TRGSEL_Pos) & ADC_MR_TRGSEL_Msk)
+                    | ((freeRun<<7) & ADC_MR_FREERUN) ;
+}
+
+/**
+ * \brief Initialize the ADC Low Res
+ */
+extern void ADC_CfgLowRes( Adc* pAdc, uint32_t resolution )
+{
+    pAdc->ADC_MR |= (resolution<<4) & ADC_MR_LOWRES;
+}
+
+/**
+ * \brief Initialize the ADC PowerSave
+ */
+extern void ADC_CfgPowerSave( Adc* pAdc, uint32_t sleep, uint32_t fwup )
+{
+    pAdc->ADC_MR |= ( ((sleep<<5) & ADC_MR_SLEEP)
+                    | ((fwup<<6) & ADC_MR_FWUP) );
+}
+
+/**
+ * \brief Initialize the ADC Channel Mode
+ */
+extern void ADC_CfgChannelMode( Adc* pAdc, uint32_t useq, uint32_t anach )
+{
+    pAdc->ADC_MR |= ( ((anach<<23) & ADC_MR_ANACH)
+                    | ((useq <<31) & (uint32_t)ADC_MR_USEQ) );
+}
+
+
+/**
+ * \brief calcul_startup
+ */
+static uint32_t calcul_startup( uint32_t dwStartup )
+{
+    static uint32_t adwValue[16]={ 0, 8, 16, 24, 64, 80, 96, 112, 512, 576, 640, 704, 768, 832, 896, 960 } ;
+
+    assert( dwStartup < sizeof( adwValue )/sizeof( adwValue[0] ) ) ;
+
+    return adwValue[dwStartup] ;
+}
+
+/**
+ * Return the Channel Converted Data
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param channel channel to get converted value
+ */
+extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel )
+{
+    uint32_t dwData = 0;
+
+    assert( dwChannel < 16 ) ;
+
+    if ( 15 >= dwChannel )
+    {
+		dwData=*(pAdc->ADC_CDR+dwChannel) ;
+    }
+
+    return dwData ;
+}
+/**
+ * Set compare channel
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param channel channel number to be set,16 for all channels
+ */
+extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel )
+{
+    assert( dwChannel <= 16 ) ;
+
+    if ( dwChannel < 16 )
+	{
+        pAdc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPALL);
+        pAdc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPSEL_Msk);
+        pAdc->ADC_EMR |= (dwChannel << ADC_EMR_CMPSEL_Pos);
+    }
+	else
+	{
+        pAdc->ADC_EMR |= ADC_EMR_CMPALL;
+    }
+}
+/**
+ * Set compare mode
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param mode compare mode
+ */
+extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode )
+{
+    pAdc->ADC_EMR &= (uint32_t)~(ADC_EMR_CMPMODE_Msk);
+    pAdc->ADC_EMR |= (dwMode & ADC_EMR_CMPMODE_Msk) ;
+}
+/**
+ * Set comparsion window,one thereshold each time
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param hi_lo Comparison Window
+ */
+extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo )
+{
+    pAdc->ADC_CWR = dwHi_Lo ;
+}
+
+/**----------------------------------------------------------------------------
+ * Test if ADC Interrupt is Masked
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param flag flag to be tested
+ *
+ * \return 1 if interrupt is masked, otherwise 0
+ */
+uint32_t ADC_IsInterruptMasked( Adc* pAdc, uint32_t dwFlag )
+{
+    return (ADC_GetInterruptMaskStatus( pAdc ) & dwFlag) ;
+}
+
+/**----------------------------------------------------------------------------
+ * Test if ADC Status is Set
+ *
+ * \param pAdc Pointer to an Adc instance.
+ * \param flag flag to be tested
+ *
+ * \return 1 if the staus is set; 0 otherwise
+ */
+extern uint32_t ADC_IsStatusSet( Adc* pAdc, uint32_t dwFlag )
+{
+    return (ADC_GetStatus( pAdc ) & dwFlag) ;
+}
+
+/**----------------------------------------------------------------------------
+ * Test if ADC channel interrupt Status is Set
+ *
+ * \param adc_sr Value of SR register
+ * \param channel Channel to be tested
+ *
+ * \return 1 if interrupt status is set, otherwise 0
+ */
+extern uint32_t ADC_IsChannelInterruptStatusSet( uint32_t dwAdc_sr, uint32_t dwChannel )
+{
+    uint32_t dwStatus ;
+
+    if ( (dwAdc_sr & ((uint32_t)1 << dwChannel)) == ((uint32_t)1 << dwChannel) )
+    {
+        dwStatus = 1 ;
+    }
+    else
+    {
+        dwStatus = 0 ;
+    }
+
+    return dwStatus ;
+}
+
+/**
+ * \brief Read converted data through PDC channel
+ *
+ * \param pADC the pointer of adc peripheral
+ * \param pBuffer the destination buffer
+ * \param dwSize the size of the buffer
+ */
+extern uint32_t ADC_ReadBuffer( Adc* pADC, int16_t *pwBuffer, uint32_t dwSize )
+{
+    /* Check if the first PDC bank is free*/
+    if ( (pADC->ADC_RCR == 0) && (pADC->ADC_RNCR == 0) )
+    {
+        pADC->ADC_RPR = (uint32_t)pwBuffer ;
+        pADC->ADC_RCR = dwSize ;
+        pADC->ADC_PTCR = ADC_PTCR_RXTEN;
+
+        return 1;
+    }
+    /* Check if the second PDC bank is free*/
+    else
+    {
+        if ( pADC->ADC_RNCR == 0 )
+        {
+            pADC->ADC_RNPR = (uint32_t)pwBuffer ;
+            pADC->ADC_RNCR = dwSize ;
+
+            return 1 ;
+        }
+        else
+        {
+            return 0 ;
+        }
+    }
+}
+

hardware/tools/libchip_sam3s/source/async.c

@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ *
+ * Provide a routine for asynchronos transfer.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Global functions
+ *----------------------------------------------------------------------------*/
+ /**
+ * \brief Returns 1 if the given transfer has ended; otherwise returns 0.
+ * \param pAsync  Pointer to an Async instance.
+ */
+uint32_t ASYNC_IsFinished( Async* pAsync )
+{
+    return (pAsync->status != ASYNC_STATUS_PENDING) ;
+}
+

hardware/tools/libchip_sam3s/source/crccu.c

@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup crccu_module Working with CRCCU
+ * The CRCCU driver provides the interface to configure and use the CRCCU
+ * peripheral.
+ *
+ * It performs a CRC computation on a Memory Area. CRC computation is performed
+ * from the LSB to MSB bit. Three different polynomials are available:
+ * CCIT802.3, CASTAGNOLI and CCIT16.
+ *
+ * To computes CRC of a buffer, the user has to follow these few steps:
+ * <ul>
+ * <li>Reset initial CRC by setting RESET bit in CRCCU_CRC_CR,</li>
+ * <li>Configure CRC descriptor and working mode,</li>
+ * <li>Start to compute CRC by setting DMAEN in CRCCU_DMA_EN,</li>
+ * <li>Get CRC value in CRCCU_CRC_SR.</li>
+ * </ul>
+ *
+ * For more accurate information, please look at the CRCCU section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref crccu.c\n
+ * \ref crccu.h.\n
+*/
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Cyclic Redundancy Check Calculation Unit (CRCCU).
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Definitions
+ *----------------------------------------------------------------------------*/
+#define CRCCU_TIMEOUT    0xFFFFFFFF
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+/**
+ * \brief Reset initial CRC to 0xFFFFFFFF.
+ */
+extern void CRCCU_ResetCrcValue( Crccu* pCrccu )
+{
+    pCrccu->CRCCU_CR = CRCCU_CR_RESET;
+}
+
+/**
+ * \brief Configure the CRCCU.
+ *
+ * \param dscrAddr CRC decscriptor address.
+ * \param mode     CRC work mode
+ */
+extern void CRCCU_Configure( Crccu* pCrccu, uint32_t dwDscrAddr, uint32_t dwMode )
+{
+    pCrccu->CRCCU_DSCR = dwDscrAddr ;
+    pCrccu->CRCCU_MR = dwMode ;
+}
+
+/**
+ * \brief Start to compute the CRC of a buffer.
+ *
+ * \return The CRC of the buffer.
+ */
+extern uint32_t CRCCU_ComputeCrc( Crccu* pCrccu )
+{
+    uint32_t dwTimeout = 0 ;
+
+    pCrccu->CRCCU_DMA_EN = CRCCU_DMA_EN_DMAEN ;
+
+    while ( ((pCrccu->CRCCU_DMA_SR & CRCCU_DMA_SR_DMASR) == CRCCU_DMA_SR_DMASR) &&
+            (dwTimeout++ < CRCCU_TIMEOUT) ) ;
+
+    return (pCrccu->CRCCU_SR) ;
+}
+

hardware/tools/libchip_sam3s/source/dacc.c

@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup dacc_module Working with DACC
+ * The DACC driver provides the interface to configure and use the DACC peripheral.\n
+ *
+ * The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output.
+ * The data to be converted are sent in a common register for all channels. It offers up to 2
+ * analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF.
+ *
+ * To Enable a DACC conversion,the user has to follow these few steps:
+ * <ul>
+ * <li> Select an appropriate reference voltage on ADVREF   </li>
+ * <li> Configure the DACC according to its requirements and special needs,which could be
+        broken down into several parts:
+ * -#   Enable DACC in free running mode by clearing TRGEN in DACC_MR;
+ * -#   Configure Startup Time and Refresh Period through setting STARTUP and REFRESH fields
+ *      in DACC_MR; The refresh mechanism is used to protect the output analog value from
+ *      decreasing.
+ * -#   Enable channels and write digital code to DACC_CDR,in free running mode, the conversion
+ *      is started right after at least one channel is enabled and data is written .
+   </li>
+ * </ul>
+ *
+ * For more accurate information, please look at the DACC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref DACC.c\n
+ * \ref DACC.h\n
+*/
+/*@{*/
+/*@}*/
+/**
+ * \file
+ *
+ * Implementation of Digital-to-Analog Converter Controller (DACC).
+ *
+ */
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+  * \brief Initialize the DACC controller
+  * \param pDACC Pointer to an DACC instance.
+  * \param idDACC identifier of DAC peripheral
+  * \param trgEn trigger mode, free running mode or external Hardware trigger
+  * \param word transfer size,word or half word
+  * \param trgSel hardware trigger selection
+  * \param sleepMode sleep mode selection
+  * \param mck value of MCK in Hz
+  * \param refresh refresh period
+  * \param user_sel user channel selection ,0 or 1
+  * \param tag_mode tag for channel number
+  * \param startup value of the start up time (in DACCClock) (see datasheet)
+*/
+extern void DACC_Initialize( Dacc* pDACC,
+                             uint8_t idDACC,
+                             uint8_t trgEn,
+                             uint8_t trgSel,
+                             uint8_t word,
+                             uint8_t sleepMode,
+                             uint32_t mck,
+                             uint8_t refresh,    /* refresh period */
+                             uint8_t user_sel,   /* user channel selection */
+                             uint32_t tag_mode,  /* using tag for channel number */
+                             uint32_t startup
+                            )
+{
+    assert( 1024*refresh*1000/(mck>>1) < 20 ) ;
+
+    /* Enable peripheral clock*/
+    PMC->PMC_PCER0 = 1 << idDACC;
+
+    /*  Reset the controller */
+    DACC_SoftReset(pDACC);
+
+    /*  Write to the MR register */
+    DACC_CfgModeReg( pDACC,
+          ( (trgEn<<0) & DACC_MR_TRGEN)
+        |   DACC_MR_TRGSEL(trgSel)
+        | ( (word<<4) & DACC_MR_WORD)
+        | ( (sleepMode<<5) & DACC_MR_SLEEP)
+        |   DACC_MR_REFRESH(refresh)
+        | ( (user_sel<<DACC_MR_USER_SEL_Pos)& DACC_MR_USER_SEL_Msk)
+        | ( (tag_mode<<20) &  DACC_MR_TAG)
+        | ( (startup<<DACC_MR_STARTUP_Pos) & DACC_MR_STARTUP_Msk));
+}
+
+
+/**
+ * Set the Conversion Data
+ * \param pDACC Pointer to an Dacc instance.
+ * \param data  date to be converted.
+ */
+extern void DACC_SetConversionData( Dacc* pDACC, uint32_t dwData )
+{
+    uint32_t dwMR = pDACC->DACC_MR ;
+
+    if ( dwMR & DACC_MR_WORD )
+    {
+    	pDACC->DACC_CDR = dwData ;
+    }
+    else
+    {
+    	pDACC->DACC_CDR = (dwData&0xFFFF) ;
+    }
+}
+
+
+/**
+  * \brief Write converted data through PDC channel
+  * \param pDACC the pointer of DACC peripheral
+  * \param pBuffer the destination buffer
+  * \param size the size of the buffer
+*/
+extern uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t *pwBuffer, uint32_t dwSize )
+{
+
+    /* Check if the first PDC bank is free*/
+    if ( (pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0) )
+	{
+        pDACC->DACC_TPR = (uint32_t)pwBuffer ;
+        pDACC->DACC_TCR = dwSize ;
+        pDACC->DACC_PTCR = DACC_PTCR_TXTEN ;
+
+        return 1 ;
+    }
+    /* Check if the second PDC bank is free*/
+    else
+	{
+	    if (pDACC->DACC_TNCR == 0)
+	    {
+            pDACC->DACC_TNPR = (uint32_t)pwBuffer ;
+            pDACC->DACC_TNCR = dwSize ;
+
+            return 1 ;
+        }
+        else
+		{
+            return 0 ;
+		}
+    }
+
+}
+
+

hardware/tools/libchip_sam3s/source/efc.c

@@ -0,0 +1,289 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup efc_module Working with EEFC
+ * The EEFC driver provides the interface to configure and use the EEFC
+ * peripheral.
+ *
+ * The user needs to set the number of wait states depending on the frequency used.\n
+ * Configure number of cycles for flash read/write operations in the FWS field of EEFC_FMR.
+ *
+ * It offers a function to send flash command to EEFC and waits for the
+ * flash to be ready.
+ *
+ * To send flash command, the user could do in either of following way:
+ * <ul>
+ * <li>Write a correct key, command and argument in EEFC_FCR. </li>
+ * <li>Or, Use IAP (In Application Programming) function which is executed from
+ * ROM directly, this allows flash programming to be done by code running in flash.</li>
+ * <li>Once the command is achieved, it can be detected even by polling EEFC_FSR or interrupt.
+ * </ul>
+ *
+ * The command argument could be a page number,GPNVM number or nothing, it depends on
+ * the command itself. Some useful functions in this driver could help user tranlate physical
+ * flash address into a page number and vice verse.
+ *
+ * For more accurate information, please look at the EEFC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref efc.c\n
+ * \ref efc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * Implementation of Enhanced Embedded Flash Controller (EEFC).
+ *
+ */
+
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <assert.h>
+#include <stdlib.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables the flash ready interrupt source on the EEFC peripheral.
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+extern void EFC_EnableFrdyIt( Efc* efc )
+{
+    efc->EEFC_FMR |= EEFC_FMR_FRDY ;
+}
+
+/**
+ * \brief Disables the flash ready interrupt source on the EEFC peripheral.
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+
+extern void EFC_DisableFrdyIt( Efc* efc )
+{
+    efc->EEFC_FMR &= ~((uint32_t)EEFC_FMR_FRDY) ;
+}
+
+
+/**
+ * \brief Set read/write wait state on the EEFC perpherial.
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param cycles  the number of wait states in cycle.
+ */
+
+extern void EFC_SetWaitState( Efc* efc, uint8_t ucCycles )
+{
+    uint32_t dwValue ;
+
+    dwValue = efc->EEFC_FMR ;
+    dwValue &= ~((uint32_t)EEFC_FMR_FWS_Msk) ;
+    dwValue |= EEFC_FMR_FWS(ucCycles);
+    efc->EEFC_FMR = dwValue ;
+}
+
+/**
+ * \brief Returns the current status of the EEFC.
+ *
+ * \note Keep in mind that this function clears the value of some status bits (LOCKE, PROGE).
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+extern uint32_t EFC_GetStatus( Efc* efc )
+{
+    return efc->EEFC_FSR ;
+}
+
+/**
+ * \brief Returns the result of the last executed command.
+ *
+ * \param efc  Pointer to a Efc instance
+ */
+extern uint32_t EFC_GetResult( Efc* efc )
+{
+    return efc->EEFC_FRR ;
+}
+
+/**
+ * \brief Translates the given address page and offset values.
+ * \note The resulting values are stored in the provided variables if they are not null.
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param address  Address to translate.
+ * \param pPage  First page accessed.
+ * \param pOffset  Byte offset in first page.
+ */
+extern void EFC_TranslateAddress( Efc** ppEfc, uint32_t dwAddress, uint16_t* pwPage, uint16_t* pwOffset )
+{
+    Efc *pEfc ;
+    uint16_t wPage ;
+    uint16_t wOffset ;
+
+    assert( dwAddress >= IFLASH_ADDR ) ;
+    assert( dwAddress <= (IFLASH_ADDR + IFLASH_SIZE) ) ;
+
+    pEfc = EFC ;
+    wPage = (dwAddress - IFLASH_ADDR) / IFLASH_PAGE_SIZE;
+    wOffset = (dwAddress - IFLASH_ADDR) % IFLASH_PAGE_SIZE;
+
+    /* Store values */
+    if ( pEfc )
+    {
+        *ppEfc = pEfc ;
+    }
+
+    if ( pwPage )
+    {
+        *pwPage = wPage ;
+    }
+
+    if ( pwOffset )
+    {
+        *pwOffset = wOffset ;
+    }
+}
+
+/**
+ * \brief Computes the address of a flash access given the page and offset.
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param page  Page number.
+ * \param offset  Byte offset inside page.
+ * \param pAddress  Computed address (optional).
+ */
+extern void EFC_ComputeAddress( Efc *efc, uint16_t wPage, uint16_t wOffset, uint32_t *pdwAddress )
+{
+    uint32_t dwAddress ;
+	
+    assert( efc ) ;
+    assert( wPage <= IFLASH_NB_OF_PAGES ) ;
+    assert( wOffset < IFLASH_PAGE_SIZE ) ;
+	
+    /* Compute address */
+    dwAddress = IFLASH_ADDR + wPage * IFLASH_PAGE_SIZE + wOffset ;
+	
+    /* Store result */
+    if ( pdwAddress != NULL )
+	{
+        *pdwAddress = dwAddress ;
+    }
+}
+
+/**
+ * \brief Starts the executing the given command on the EEFC and returns as soon as the command is started.
+ *
+ * \note It does NOT set the FMCN field automatically.
+ * \param efc  Pointer to a Efc instance
+ * \param command  Command to execute.
+ * \param argument  Command argument (should be 0 if not used).
+ */
+extern void EFC_StartCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument )
+{
+    /* Check command & argument */
+    switch ( dwCommand )
+    {
+        case EFC_FCMD_WP:
+        case EFC_FCMD_WPL:
+        case EFC_FCMD_EWP:
+        case EFC_FCMD_EWPL:
+        case EFC_FCMD_SLB:
+        case EFC_FCMD_CLB:
+            assert( dwArgument < IFLASH_NB_OF_PAGES ) ;
+        break ;
+
+        case EFC_FCMD_SFB:
+        case EFC_FCMD_CFB:
+            assert( dwArgument < 2 ) ;
+        break;
+
+        case EFC_FCMD_GETD:
+        case EFC_FCMD_EA:
+        case EFC_FCMD_GLB:
+        case EFC_FCMD_GFB:
+        case EFC_FCMD_STUI:
+            assert( dwArgument == 0 ) ;
+        break;
+
+        default: assert( 0 ) ;
+    }
+
+    /* Start command Embedded flash */
+    assert( (efc->EEFC_FSR & EEFC_FMR_FRDY) == EEFC_FMR_FRDY ) ;
+    efc->EEFC_FCR = EEFC_FCR_FKEY(0x5A) | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ;
+}
+
+/**
+ * \brief Performs the given command and wait until its completion (or an error).
+ *
+ * \param efc  Pointer to a Efc instance
+ * \param command  Command to perform.
+ * \param argument  Optional command argument.
+ *
+ * \return 0 if successful, otherwise returns an error code.
+ */
+
+extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, uint32_t dwArgument, uint32_t dwUseIAP )
+{
+    if ( dwUseIAP != 0 )
+    {
+        /* Pointer on IAP function in ROM */
+        static uint32_t (*IAP_PerformCommand)( uint32_t, uint32_t ) ;
+
+        IAP_PerformCommand = (uint32_t (*)( uint32_t, uint32_t )) *((uint32_t*)CHIP_FLASH_IAP_ADDRESS ) ;
+        IAP_PerformCommand( 0, EEFC_FCR_FKEY(0x5A) | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ) ;
+
+        return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE)) ;
+    }
+    else
+    {
+        uint32_t dwStatus ;
+
+        efc->EEFC_FCR = EEFC_FCR_FKEY(0x5A) | EEFC_FCR_FARG(dwArgument) | EEFC_FCR_FCMD(dwCommand) ;
+        do
+        {
+            dwStatus = efc->EEFC_FSR ;
+        }
+        while ( (dwStatus & EEFC_FSR_FRDY) != EEFC_FSR_FRDY ) ;
+
+        return ( dwStatus & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE) ) ;
+    }
+}
+
+

hardware/tools/libchip_sam3s/source/exceptions.c

@@ -0,0 +1,49 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/**
+ * \file
+ * This file contains the default exception handlers.
+ *
+ * \note
+ * The exception handler has weak aliases.
+ * As they are weak aliases, any function with the same name will override
+ * this definition.
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+

hardware/tools/libchip_sam3s/source/flashd.c

@@ -0,0 +1,511 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup flashd_module Flash Memory Interface
+ * The flash driver manages the programming, erasing, locking and unlocking sequences
+ * with dedicated commands.
+ *
+ * To implement flash programing operation, the user has to follow these few steps :
+ * <ul>
+ * <li>Configue flash wait states to initializes the flash. </li>
+ * <li>Checks whether a region to be programmed is locked. </li>
+ * <li>Unlocks the user region to be programmed if the region have locked before.</li>
+ * <li>Erases the user page before program (optional).</li>
+ * <li>Writes the user page from the page buffer.</li>
+ * <li>Locks the region of programmed area if any.</li>
+ * </ul>
+ *
+ * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
+ * A check of this validity and padding for 32-bit alignment should be done in write algorithm.
+
+ * Lock/unlock range associated with the user address range is automatically translated.
+ *
+ * This security bit can be enabled through the command "Set General Purpose NVM Bit 0".
+ *
+ * A 128-bit factory programmed unique ID could be read to serve several purposes.
+ *
+ * The driver accesses the flash memory by calling the lowlevel module provided in \ref efc_module.
+ * For more accurate information, please look at the EEFC section of the Datasheet.
+ *
+ * Related files :\n
+ * \ref flashd.c\n
+ * \ref flashd.h.\n
+ * \ref efc.c\n
+ * \ref efc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * The flash driver provides the unified interface for flash program operations.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <string.h>
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local variables
+ *----------------------------------------------------------------------------*/
+
+//static NO_INIT uint8_t _aucPageBuffer[IFLASH_PAGE_SIZE] ;
+static NO_INIT uint32_t _adwPageBuffer[IFLASH_PAGE_SIZE/4] ;
+static uint8_t* _aucPageBuffer = (uint8_t*)_adwPageBuffer;
+static NO_INIT uint32_t _dwUseIAP ;
+
+/*----------------------------------------------------------------------------
+ *        Local macros
+ *----------------------------------------------------------------------------*/
+
+#define min( a, b ) (((a) < (b)) ? (a) : (b))
+
+/*----------------------------------------------------------------------------
+ *        Local functions
+ *----------------------------------------------------------------------------*/
+
+
+/**
+ * \brief Computes the lock range associated with the given address range.
+ *
+ * \param dwStart  Start address of lock range.
+ * \param dwEnd  End address of lock range.
+ * \param pdwActualStart  Actual start address of lock range.
+ * \param pdwActualEnd  Actual end address of lock range.
+ */
+static void ComputeLockRange( uint32_t dwStart, uint32_t dwEnd, uint32_t *pdwActualStart, uint32_t *pdwActualEnd )
+{
+    Efc* pStartEfc ;
+    Efc* pEndEfc ;
+    uint16_t wStartPage ;
+    uint16_t wEndPage ;
+    uint16_t wNumPagesInRegion ;
+    uint16_t wActualStartPage ;
+    uint16_t wActualEndPage ;
+
+    // Convert start and end address in page numbers
+    EFC_TranslateAddress( &pStartEfc, dwStart, &wStartPage, 0 ) ;
+    EFC_TranslateAddress( &pEndEfc, dwEnd, &wEndPage, 0 ) ;
+
+    // Find out the first page of the first region to lock
+    wNumPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ;
+    wActualStartPage = wStartPage - (wStartPage % wNumPagesInRegion) ;
+    wActualEndPage = wEndPage ;
+
+    if ( (wEndPage % wNumPagesInRegion) != 0 )
+    {
+        wActualEndPage += wNumPagesInRegion - (wEndPage % wNumPagesInRegion) ;
+    }
+    // Store actual page numbers
+    EFC_ComputeAddress( pStartEfc, wActualStartPage, 0, pdwActualStart ) ;
+    EFC_ComputeAddress( pEndEfc, wActualEndPage, 0, pdwActualEnd ) ;
+}
+
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Initializes the flash driver.
+ *
+ * \param mck  Master clock frequency in Hz.
+ */
+
+extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP )
+{
+    EFC_DisableFrdyIt( EFC ) ;
+	
+    if ( (dwMCk/1000000) >= 64 )
+	{
+        EFC_SetWaitState( EFC, 2 ) ;
+    }
+    else
+	{
+	    if ( (dwMCk/1000000) >= 50 )
+	    {
+            EFC_SetWaitState( EFC, 1 ) ;
+        }
+        else
+	    {
+            EFC_SetWaitState( EFC, 0 ) ;
+        }
+	}
+
+    _dwUseIAP=dwUseIAP ;
+}
+
+/**
+ * \brief Erases the entire flash.
+ *
+ * \param address  Flash start address.
+ * \return 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Erase( uint32_t dwAddress )
+{
+    Efc* pEfc ;
+    uint16_t wPage ;
+    uint16_t wOffset ;
+    uint32_t dwError ;
+
+    assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ;
+
+    // Translate write address
+    EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ;
+    dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EA, 0, _dwUseIAP ) ;
+	
+    return dwError ;
+}
+
+/**
+ * \brief Writes a data buffer in the internal flash
+ *
+ * \note This function works in polling mode, and thus only returns when the
+ * data has been effectively written.
+ * \param address  Write address.
+ * \param pBuffer  Data buffer.
+ * \param size  Size of data buffer in bytes.
+ * \return 0 if successful, otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, uint32_t dwSize )
+{
+    Efc* pEfc ;
+    uint16_t page ;
+    uint16_t offset ;
+    uint32_t writeSize ;
+    uint32_t pageAddress ;
+    uint16_t padding ;
+    uint32_t dwError ;
+    uint32_t sizeTmp ;
+    uint32_t *pAlignedDestination ;
+    uint32_t *pAlignedSource ;
+
+    assert( pvBuffer ) ;
+    assert( dwAddress >=IFLASH_ADDR ) ;
+    assert( (dwAddress + dwSize) <= (IFLASH_ADDR + IFLASH_SIZE) ) ;
+
+    /* Translate write address */
+    EFC_TranslateAddress( &pEfc, dwAddress, &page, &offset ) ;
+
+    /* Write all pages */
+    while ( dwSize > 0 )
+    {
+        /* Copy data in temporary buffer to avoid alignment problems */
+        writeSize = min((uint32_t)IFLASH_PAGE_SIZE - offset, dwSize ) ;
+        EFC_ComputeAddress(pEfc, page, 0, &pageAddress ) ;
+        padding = IFLASH_PAGE_SIZE - offset - writeSize ;
+
+        /* Pre-buffer data */
+        memcpy( _aucPageBuffer, (void *) pageAddress, offset);
+
+        /* Buffer data */
+        memcpy( _aucPageBuffer + offset, pvBuffer, writeSize);
+
+        /* Post-buffer data */
+        memcpy( _aucPageBuffer + offset + writeSize, (void *) (pageAddress + offset + writeSize), padding);
+
+        /* Write page
+         * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption
+         */
+        pAlignedDestination = (uint32_t*)pageAddress ;
+        pAlignedSource = (uint32_t*)_adwPageBuffer ;
+        sizeTmp = IFLASH_PAGE_SIZE ;
+
+        while ( sizeTmp >= 4 )
+        {
+            *pAlignedDestination++ = *pAlignedSource++;
+            sizeTmp -= 4;
+        }
+
+        /* Send writing command */
+        dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EWP, page, _dwUseIAP ) ;
+        if ( dwError )
+        {
+            return dwError ;
+        }
+
+        /* Progression */
+        dwAddress += IFLASH_PAGE_SIZE ;
+        pvBuffer = (void *)((uint32_t) pvBuffer + writeSize) ;
+        dwSize -= writeSize ;
+        page++;
+        offset = 0;
+    }
+
+    return 0 ;
+}
+/**
+ * \brief Locks all the regions in the given address range. The actual lock range is
+ * reported through two output parameters.
+ *
+ * \param start  Start address of lock range.
+ * \param end    End address of lock range.
+ * \param pActualStart  Start address of the actual lock range (optional).
+ * \param pActualEnd  End address of the actual lock range (optional).
+ * \return 0 if successful, otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Lock( uint32_t start, uint32_t end, uint32_t *pActualStart, uint32_t *pActualEnd )
+{
+    Efc *pEfc ;
+    uint32_t actualStart, actualEnd ;
+    uint16_t startPage, endPage ;
+    uint32_t dwError ;
+    uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE;
+
+    /* Compute actual lock range and store it */
+    ComputeLockRange( start, end, &actualStart, &actualEnd ) ;
+    if ( pActualStart != NULL )
+    {
+        *pActualStart = actualStart ;
+    }
+    if ( pActualEnd != NULL )
+    {
+        *pActualEnd = actualEnd;
+    }
+
+    /* Compute page numbers */
+    EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ;
+    EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ;
+
+    /* Lock all pages */
+    while ( startPage < endPage )
+    {
+        dwError = EFC_PerformCommand( pEfc, EFC_FCMD_SLB, startPage, _dwUseIAP ) ;
+        if ( dwError )
+        {
+            return dwError ;
+        }
+        startPage += numPagesInRegion;
+    }
+
+    return 0 ;
+}
+
+/**
+ * \brief Unlocks all the regions in the given address range. The actual unlock range is
+ * reported through two output parameters.
+ * \param start  Start address of unlock range.
+ * \param end  End address of unlock range.
+ * \param pActualStart  Start address of the actual unlock range (optional).
+ * \param pActualEnd  End address of the actual unlock range (optional).
+ * \return 0 if successful, otherwise returns an error code.
+ */
+extern uint32_t FLASHD_Unlock( uint32_t start, uint32_t end, uint32_t *pActualStart, uint32_t *pActualEnd )
+{
+    Efc* pEfc ;
+    uint32_t actualStart, actualEnd ;
+    uint16_t startPage, endPage ;
+    uint32_t dwError ;
+    uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE;
+
+    // Compute actual unlock range and store it
+    ComputeLockRange(start, end, &actualStart, &actualEnd);
+    if ( pActualStart != NULL )
+    {
+        *pActualStart = actualStart ;
+    }
+    if ( pActualEnd != NULL )
+    {
+        *pActualEnd = actualEnd ;
+    }
+
+    // Compute page numbers
+    EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ;
+    EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ;
+
+    // Unlock all pages
+    while ( startPage < endPage )
+    {
+        dwError = EFC_PerformCommand( pEfc, EFC_FCMD_CLB, startPage, _dwUseIAP ) ;
+        if ( dwError )
+        {
+            return dwError ;
+        }
+        startPage += numPagesInRegion ;
+    }
+    return 0 ;
+}
+
+/**
+ * \brief Returns the number of locked regions inside the given address range.
+ *
+ * \param start  Start address of range
+ * \param end    End address of range.
+ */
+extern uint32_t FLASHD_IsLocked( uint32_t start, uint32_t end )
+{
+    Efc *pEfc ;
+    uint16_t startPage, endPage ;
+    uint8_t startRegion, endRegion ;
+    uint32_t numPagesInRegion ;
+    uint32_t status ;
+    uint32_t dwError ;
+    uint32_t numLockedRegions = 0 ;
+
+    assert( end >= start ) ;
+    assert( (start >=IFLASH_ADDR) && (end <= IFLASH_ADDR + IFLASH_SIZE) ) ;
+
+    // Compute page numbers
+    EFC_TranslateAddress( &pEfc, start, &startPage, 0 ) ;
+    EFC_TranslateAddress( 0, end, &endPage, 0 ) ;
+
+    // Compute region numbers
+    numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ;
+    startRegion = startPage / numPagesInRegion ;
+    endRegion = endPage / numPagesInRegion ;
+    if ((endPage % numPagesInRegion) != 0)
+    {
+        endRegion++ ;
+    }
+
+    // Retrieve lock status
+    dwError = EFC_PerformCommand( pEfc, EFC_FCMD_GLB, 0, _dwUseIAP ) ;
+    assert( !dwError ) ;
+    status = EFC_GetResult( pEfc ) ;
+
+    // Check status of each involved region
+    while ( startRegion < endRegion )
+    {
+        if ( (status & (1 << startRegion)) != 0 )
+        {
+            numLockedRegions++ ;
+        }
+        startRegion++ ;
+    }
+
+    return numLockedRegions ;
+}
+
+/**
+ * \brief Check if the given GPNVM bit is set or not.
+ *
+ * \param gpnvm  GPNVM bit index.
+ * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0.
+ */
+extern uint32_t FLASHD_IsGPNVMSet( uint8_t ucGPNVM )
+{
+    uint32_t dwError ;
+    uint32_t dwStatus ;
+
+    assert( ucGPNVM < 2 ) ;
+
+    /* Get GPNVMs status */
+    dwError = EFC_PerformCommand( EFC, EFC_FCMD_GFB, 0, _dwUseIAP ) ;
+    assert( !dwError ) ;
+    dwStatus = EFC_GetResult( EFC ) ;
+
+    /* Check if GPNVM is set */
+    if ( (dwStatus & (1 << ucGPNVM)) != 0 )
+    {
+        return 1 ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/**
+ * \brief Sets the selected GPNVM bit.
+ *
+ * \param gpnvm  GPNVM bit index.
+ * \returns 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_SetGPNVM( uint8_t ucGPNVM )
+{
+    assert( ucGPNVM < 2 ) ;
+
+    if ( !FLASHD_IsGPNVMSet( ucGPNVM ) )
+    {
+        return EFC_PerformCommand( EFC, EFC_FCMD_SFB, ucGPNVM, _dwUseIAP ) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/**
+ * \brief Clears the selected GPNVM bit.
+ *
+ * \param gpnvm  GPNVM bit index.
+ * \returns 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_ClearGPNVM( uint8_t ucGPNVM )
+{
+    assert( ucGPNVM < 2 ) ;
+
+    if ( FLASHD_IsGPNVMSet( ucGPNVM ) )
+    {
+        return EFC_PerformCommand( EFC, EFC_FCMD_CFB, ucGPNVM, _dwUseIAP ) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+/**
+ * \brief Read the unique ID.
+ *
+ * \param uniqueID pointer on a 4bytes char containing the unique ID value.
+ * \returns 0 if successful; otherwise returns an error code.
+ */
+extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID )
+{
+    uint32_t dwError ;
+
+    assert( pdwUniqueID != NULL ) ;
+
+    pdwUniqueID[0] = 0 ;
+    pdwUniqueID[1] = 0 ;
+    pdwUniqueID[2] = 0 ;
+    pdwUniqueID[3] = 0 ;
+
+    EFC_StartCommand( EFC, EFC_FCMD_STUI, 0 ) ;
+
+    pdwUniqueID[0] = *(uint32_t*) IFLASH_ADDR;
+    pdwUniqueID[1] = *(uint32_t*)(IFLASH_ADDR + 4) ;
+    pdwUniqueID[2] = *(uint32_t*)(IFLASH_ADDR + 8) ;
+    pdwUniqueID[3] = *(uint32_t*)(IFLASH_ADDR + 12) ;
+
+    dwError = EFC_PerformCommand( EFC, EFC_FCMD_SPUI, 0, _dwUseIAP ) ;
+    if ( dwError )
+    {
+        return dwError ;
+    }
+
+    return 0 ;
+}

hardware/tools/libchip_sam3s/source/pio.c

@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \file */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+/**
+ * \brief Configures Pio pin internal pull-up.
+ *
+ * \param pPio            Pointer to a PIO controller.
+ * \param dwMask          Bitmask of one or more pin(s) to configure.
+ * \param dwPullUpEnable  Indicates if the pin(s) internal pull-up shall be configured.
+ */
+extern void PIO_DisableInterrupt( Pio *pPio, const uint32_t dwMask )
+{
+    /* Disable interrupts on the pin */
+    pPio->PIO_IDR = dwMask ;
+}
+
+/**
+ * \brief Configures Pio pin internal pull-up.
+ *
+ * \param pPio            Pointer to a PIO controller.
+ * \param dwMask          Bitmask of one or more pin(s) to configure.
+ * \param dwPullUpEnable  Indicates if the pin(s) internal pull-up shall be configured.
+ */
+extern void PIO_PullUp( Pio *pPio, const uint32_t dwMask, const uint32_t dwPullUpEnable )
+{
+    /* Disable interrupts on the pin(s) */
+    pPio->PIO_IDR = dwMask ;
+
+    /* Enable the pull-up(s) if necessary */
+    if ( dwPullUpEnable )
+    {
+        pPio->PIO_PUER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_PUDR = dwMask ;
+    }
+}
+
+/**
+ * \brief Configures Glitch or Debouncing filter for input.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ * \param cuttoff  Cutt off frequency for debounce filter.
+ */
+extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff )
+{
+    pPio->PIO_IFSCER = dwMask ; /* set Debouncing, 0 bit field no effect */
+    pPio->PIO_SCDR = ((32678/(2*(dwCuttOff))) - 1) & 0x3FFF; /* the lowest 14 bits work */
+}
+
+/**
+ * \brief Sets a high output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+extern void PIO_Set( Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_SODR = dwMask ;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin instance currently have
+ * a high level; otherwise returns 0. This method returns the actual value that
+ * is being read on the pin. To return the supposed output value of a pin, use
+ * PIO_GetOutputDataStatus() instead.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that currently has
+ * a high level; otherwise 0.
+ */
+extern uint32_t PIO_Get( Pio* pPio, const EPioType dwType, const uint32_t dwMask )
+{
+    uint32_t dwReg ;
+
+    if ( (dwType == PIO_OUTPUT_0) || (dwType == PIO_OUTPUT_1) )
+    {
+        dwReg = pPio->PIO_ODSR ;
+    }
+    else
+    {
+        dwReg = pPio->PIO_PDSR ;
+    }
+
+    if ( (dwReg & dwMask) == 0 )
+    {
+        return 0 ;
+    }
+    else
+    {
+        return 1 ;
+    }
+}
+
+/**
+ * \brief Sets a low output level on all the PIOs defined in the given Pin instance.
+ * This has no immediate effects on PIOs that are not output, but the PIO
+ * controller will memorize the value they are changed to outputs.
+ *
+ * \param pin  Pointer to a Pin instance describing one or more pins.
+ */
+extern void PIO_Clear( Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_CODR = dwMask ;
+}
+
+/**
+ * \brief Configures one pin of a PIO controller as being controlled by specific peripheral.
+ *
+ * \param pPio    Pointer to a PIO controller.
+ * \param dwType  PIO type.
+ * \param dwMask  Bitmask of one or more pin(s) to configure.
+ */
+extern void PIO_SetPeripheral( Pio* pPio, EPioType dwType, uint32_t dwMask )
+{
+    uint32_t dwABCDSR ;
+
+    /* Disable interrupts on the pin(s) */
+    pPio->PIO_IDR = dwMask ;
+
+    switch ( dwType )
+    {
+        case PIO_PERIPH_A :
+            dwABCDSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] &= (~dwMask & dwABCDSR) ;
+
+            dwABCDSR = pPio->PIO_ABCDSR[1];
+            pPio->PIO_ABCDSR[1] &= (~dwMask & dwABCDSR) ;
+        break ;
+
+        case PIO_PERIPH_B :
+            dwABCDSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] = (dwMask | dwABCDSR) ;
+
+            dwABCDSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] &= (~dwMask & dwABCDSR) ;
+        break ;
+
+        case PIO_PERIPH_C :
+            dwABCDSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] &= (~dwMask & dwABCDSR) ;
+
+            dwABCDSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] = (dwMask | dwABCDSR) ;
+        break ;
+
+        case PIO_PERIPH_D :
+            dwABCDSR = pPio->PIO_ABCDSR[0] ;
+            pPio->PIO_ABCDSR[0] = (dwMask | dwABCDSR) ;
+
+            dwABCDSR = pPio->PIO_ABCDSR[1] ;
+            pPio->PIO_ABCDSR[1] = (dwMask | dwABCDSR) ;
+        break ;
+
+        // other types are invalid in this function
+        case PIO_INPUT :
+        case PIO_OUTPUT_0 :
+        case PIO_OUTPUT_1 :
+        case PIO_NOT_A_PIN :
+        return ;
+    }
+
+    // Remove the pins from under the control of PIO
+    pPio->PIO_PDR = dwMask ;
+}
+
+/**
+ * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally,
+ * the corresponding internal pull-up(s) and glitch filter(s) can be enabled.
+ *
+ * \param pPio        Pointer to a PIO controller.
+ * \param dwMask      Bitmask indicating which pin(s) to configure as input(s).
+ * \param dwAttribute .
+ */
+extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute )
+{
+    PIO_DisableInterrupt( pPio, dwMask ) ;
+    PIO_PullUp( pPio, dwMask, dwAttribute & PIO_PULLUP ) ;
+
+    /* Enable Input Filter if necessary */
+    if ( dwAttribute & (PIO_DEGLITCH | PIO_DEBOUNCE) )
+    {
+        pPio->PIO_IFER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_IFDR = dwMask ;
+    }
+
+    /* Enable de-glitch or de-bounce if necessary */
+    if ( dwAttribute & PIO_DEGLITCH )
+    {
+        pPio->PIO_IFSCDR = dwMask ;
+    }
+    else
+    {
+        if ( dwAttribute & PIO_DEBOUNCE )
+        {
+            pPio->PIO_IFSCER = dwMask ;
+        }
+    }
+
+    /* Configure pin as input */
+    pPio->PIO_ODR = dwMask ;
+    pPio->PIO_PER = dwMask ;
+}
+
+/**
+ * \brief Configures one or more pin(s) of a PIO controller as outputs, with the
+ * given default value. Optionally, the multi-drive feature can be enabled
+ * on the pin(s).
+ *
+ * \param pPio              Pointer to a PIO controller.
+ * \param dwMask            Bitmask indicating which pin(s) to configure.
+ * \param defaultValue      Default level on the pin(s).
+ * \param enableMultiDrive  Indicates if the pin(s) shall be configured as open-drain.
+ * \param enablePullUp      Indicates if the pin shall have its pull-up activated.
+ */
+extern void PIO_SetOutput( Pio* pPio, uint32_t dwMask, uint32_t dwDefaultValue,
+                                      uint32_t dwMultiDriveEnable, uint32_t dwPullUpEnable )
+{
+    PIO_DisableInterrupt( pPio, dwMask ) ;
+    PIO_PullUp( pPio, dwMask, dwPullUpEnable ) ;
+
+    /* Enable multi-drive if necessary */
+    if ( dwMultiDriveEnable )
+    {
+        pPio->PIO_MDER = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_MDDR = dwMask ;
+    }
+
+    /* Set default value */
+    if ( dwDefaultValue )
+    {
+        pPio->PIO_SODR = dwMask ;
+    }
+    else
+    {
+        pPio->PIO_CODR = dwMask ;
+    }
+
+    /* Configure pin(s) as output(s) */
+    pPio->PIO_OER = dwMask ;
+    pPio->PIO_PER = dwMask ;
+}
+
+/**
+ *
+ * \return 1 if the pins have been configured properly; otherwise 0.
+ */
+extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t dwMask, const uint32_t dwAttribute )
+{
+    /* Configure pins */
+    switch ( dwType )
+    {
+        case PIO_PERIPH_A :
+        case PIO_PERIPH_B :
+        case PIO_PERIPH_C :
+        case PIO_PERIPH_D :
+            PIO_SetPeripheral( pPio, dwType, dwMask ) ;
+            PIO_PullUp( pPio, dwMask, (dwAttribute & PIO_PULLUP) ) ;
+        break;
+
+        case PIO_INPUT :
+            switch ( (uint32_t)pPio )
+            {
+                case (uint32_t)PIOA :
+                    PMC_EnablePeripheral( ID_PIOA ) ;
+                break ;
+
+                case (uint32_t)PIOB :
+                    PMC_EnablePeripheral( ID_PIOB ) ;
+                break ;
+
+                case (uint32_t)PIOC :
+                    PMC_EnablePeripheral( ID_PIOC ) ;
+                break ;
+            }
+            PIO_SetInput( pPio, dwMask, dwAttribute ) ;
+        break;
+
+        case PIO_OUTPUT_0 :
+        case PIO_OUTPUT_1 :
+            PIO_SetOutput( pPio, dwMask, (dwType == PIO_OUTPUT_1),
+                          (dwAttribute & PIO_OPENDRAIN) ? 1 : 0,
+                          (dwAttribute & PIO_PULLUP) ? 1 : 0);
+        break ;
+
+        default :
+        return 0 ;
+    }
+
+    return 1 ;
+}
+
+/**
+ * \brief Returns 1 if one or more PIO of the given Pin are configured to output a
+ * high level (even if they are not output).
+ * To get the actual value of the pin, use PIO_Get() instead.
+ *
+ * \param pPio  Pointer to a Pin instance describing one or more pins.
+ *
+ * \return 1 if the Pin instance contains at least one PIO that is configured
+ * to output a high level; otherwise 0.
+ */
+extern uint32_t PIO_GetOutputDataStatus( const Pio* pPio, const uint32_t dwMask )
+{
+    if ( (pPio->PIO_ODSR & dwMask) == 0 )
+    {
+        return 0 ;
+    }
+    else
+    {
+        return 1 ;
+    }
+}
+

hardware/tools/libchip_sam3s/source/pio_capture.c

@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2010, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup pio_capture_module Working with PIO Parallel Capture Mode
+ * The PIO Parallel Capture Mode driver provides the interface to configure and use the
+ * PIO Parallel Capture Mode peripheral.\n
+ *
+ * The PIO Controller integrates an interface able to read data from a CMOS digital
+ * image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous
+ * mode, etc.... For better understanding and to ease reading, the following
+ * description uses an example with a CMOS digital image sensor
+ *
+ * To use the PIO Parallel Capture, the user has to follow these few steps:
+ * <ul>
+ *   <li> Enable PIOA peripheral clock </li>
+ *   <li> Configure the PDC </li>
+ *   <li> Configure the PIO Capture interrupt </li>
+ *   <li> Enable the PDC </li>
+ *   <li> Enable the PIO Capture </li>
+ *   <li> Wait for interrupt </li>
+ *   <li> Disable the interrupt </li>
+ *   <li> Read the DATA </li>
+ * </ul>
+ *
+ * For more accurate information, please look at the PIO Parallel Capture Mode section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref pio_capture.c\n
+ * \ref pio_capture.h\n
+ */
+/*@{*/
+/*@}*/
+/**
+ * \file
+ *
+ * Implementation of PIO Parallel Capture.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdlib.h>
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local Functions
+ *----------------------------------------------------------------------------*/
+/** Copy the API structure for interrupt handler */
+static SPioCaptureInit* _PioCaptureCopy ;
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief The PIO_CaptureHandler must be called by the PIO Capture Interrupt
+ * Service Routine with the corresponding PIO Capture instance.
+ */
+/*----------------------------------------------------------------------------*/
+extern void PIO_CaptureHandler( void )
+{
+    volatile uint32_t pio_captureSr;
+
+    /* Read the status register*/
+    pio_captureSr = PIOA->PIO_PCISR ;
+    pio_captureSr &= PIOA->PIO_PCIMR ;
+
+    if (pio_captureSr & PIO_PCISR_DRDY)
+    {
+        /* Parallel Capture Mode Data Ready */
+        if ( _PioCaptureCopy->CbkDataReady != NULL )
+        {
+            _PioCaptureCopy->CbkDataReady( _PioCaptureCopy );
+        }
+        else
+        {
+//            TRACE_DEBUG("IT PIO Capture Data Ready received (no callback)\n\r");
+        }
+    }
+
+    if (pio_captureSr & PIO_PCISR_OVRE)
+    {
+        /* Parallel Capture Mode Overrun Error */
+        if ( _PioCaptureCopy->CbkOverrun != NULL )
+        {
+            _PioCaptureCopy->CbkOverrun( _PioCaptureCopy );
+        }
+        else
+        {
+//            TRACE_DEBUG("IT PIO Capture Overrun Error received (no callback)\n\r");
+        }
+    }
+
+    if (pio_captureSr & PIO_PCISR_RXBUFF)
+    {
+        /* Reception Buffer Full */
+        if ( _PioCaptureCopy->CbkBuffFull != NULL )
+        {
+            _PioCaptureCopy->CbkBuffFull( _PioCaptureCopy );
+        }
+        else
+        {
+//            TRACE_DEBUG("IT PIO Capture Reception Buffer Full received (no callback)\n\r");
+        }
+    }
+
+    if (pio_captureSr & PIO_PCISR_ENDRX)
+    {
+        /* End of Reception Transfer */
+        if ( _PioCaptureCopy->CbkEndReception != NULL )
+        {
+            _PioCaptureCopy->CbkEndReception( _PioCaptureCopy );
+        }
+        else
+        {
+//            TRACE_DEBUG("IT PIO Capture End of Reception Transfer received (no callback)\n\r");
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Disable Interupt of the PIO Capture
+ * \param itToDisable : Interrupt to disable
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureDisableIt( uint32_t itToDisable )
+{
+    /* Parallel capture mode is enabled */
+    PIOA->PIO_PCIDR = itToDisable;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Enable Interupt of the PIO Capture
+ * \param itToEnable : Interrupt to enable
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureEnableIt( uint32_t itToEnable )
+{
+    /* Parallel capture mode is enabled */
+    PIOA->PIO_PCIER = itToEnable;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Enable the PIO Capture
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureEnable( void )
+{
+    /* PDC: Receive Pointer Register */
+    PIOA->PIO_RPR = (uint32_t)_PioCaptureCopy->pData ;
+    /* PDC: Receive Counter Register */
+    /* Starts peripheral data transfer if corresponding channel is active */
+    PIOA->PIO_RCR = PIO_RCR_RXCTR(_PioCaptureCopy->dPDCsize) ;
+
+    /* Parallel capture mode is enabled */
+    PIOA->PIO_PCMR |= PIO_PCMR_PCEN ;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Disable the PIO Capture
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureDisable( void )
+{
+    /* Parallel capture mode is disabled */
+    PIOA->PIO_PCMR &= (uint32_t)(~PIO_PCMR_PCEN) ;
+}
+
+/*----------------------------------------------------------------------------*/
+/**
+ * \brief Initialize the PIO Capture
+ * Be careful to configure the PDC before enable interrupt on pio capture.
+ * Otherway, the pdc will go in interrupt handler continuously.
+ * \param dsize :
+ *  0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit).
+ *  1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit).
+ * 2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit).
+ * \param alwaysSampling: ALWYS: Parallel Capture Mode Always Sampling
+ * 0 = The parallel capture mode samples the data when both data enables are active.
+ * 1 = The parallel capture mode samples the data whatever the data enables are.
+ * \param halfSampling: HALFS: Parallel Capture Mode Half Sampling
+ * 0 = The parallel capture mode samples all the data.
+ * 1 = The parallel capture mode samples the data only one time out of two.
+ * \param modeFirstSample: FRSTS: Parallel Capture Mode First Sample
+ * This bit is useful only if the HALFS bit is set to 1. If data are numbered
+ * in the order that they are received with an index from 0 to n:
+ * 0 = Only data with an even index are sampled.
+ * 1 = Only data with an odd index are sampled.
+ */
+/*----------------------------------------------------------------------------*/
+void PIO_CaptureInit( SPioCaptureInit *pInit )
+{
+    PMC_EnablePeripheral( ID_PIOA );
+
+    assert( (pInit->dsize < 0x4) ) ;
+    assert( (pInit->dPDCsize <= PIO_RPR_RXPTR_Msk) ) ;
+    assert( (pInit->alwaysSampling < 2)  );
+    assert( (pInit->halfSampling < 2) );
+    assert( (pInit->modeFirstSample < 2) );
+
+    /* PDC: Transfer Control Register */
+    /* Disables the PDC transmitter channel requests */
+    PIOA->PIO_PTCR = PIO_PTCR_RXTDIS;
+    /* PDC: Receive Pointer Register */
+    PIOA->PIO_RPR = (uint32_t)pInit->pData;
+    /* PDC: Receive Counter Register */
+    /* Starts peripheral data transfer if corresponding channel is active */
+    PIOA->PIO_RCR = PIO_RCR_RXCTR(pInit->dPDCsize);
+
+    /* PDC: Transfer Control Register */
+    /* Enables PDC receiver channel requests if RXTDIS is not set */
+    PIOA->PIO_PTCR = PIO_PTCR_RXTEN ;
+
+
+    /* Copy the API structure for interrupt handler */
+    _PioCaptureCopy = pInit;
+    /* PIO Parallel Capture Mode */
+    PIOA->PIO_PCMR =  PIO_PCMR_DSIZE(pInit->dsize)
+                    | ((pInit->alwaysSampling<<9) & PIO_PCMR_ALWYS)
+                    | ((pInit->halfSampling<<10) & PIO_PCMR_HALFS)
+                    | ((pInit->modeFirstSample<<11) & PIO_PCMR_FRSTS);
+
+    if ( pInit->CbkDataReady != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_DRDY;
+    }
+
+    if ( pInit->CbkOverrun != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_OVRE;
+    }
+
+    if ( pInit->CbkEndReception != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_ENDRX;
+    }
+
+    if ( pInit->CbkBuffFull != NULL )
+    {
+        PIOA->PIO_PCIER = PIO_PCISR_RXBUFF;
+    }
+//    else
+//    {
+//        TRACE_INFO("No interruption, no callback\n\r");
+//    }
+
+}
+

hardware/tools/libchip_sam3s/source/pio_it.c

@@ -0,0 +1,251 @@
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+/* Maximum number of interrupt sources that can be defined. This
+ * constant can be increased, but the current value is the smallest possible
+ * that will be compatible with all existing projects. */
+#define MAX_INTERRUPT_SOURCES       7
+
+/*----------------------------------------------------------------------------
+ *        Local types
+ *----------------------------------------------------------------------------*/
+
+/**
+ * Describes a PIO interrupt source, including the PIO instance triggering the
+ * interrupt and the associated interrupt handler.
+ */
+typedef struct _InterruptSource
+{
+    /* Pointer to the source pin instance. */
+    const Pin *pPin ;
+
+    /* Interrupt handler. */
+    void (*handler)( const Pin* ) ;
+} InterruptSource ;
+
+/*----------------------------------------------------------------------------
+ *        Local variables
+ *----------------------------------------------------------------------------*/
+
+/* List of interrupt sources. */
+static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ;
+
+/* Number of currently defined interrupt sources. */
+static uint32_t _dwNumSources = 0;
+
+/*----------------------------------------------------------------------------
+ *        Local Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Handles all interrupts on the given PIO controller.
+ * \param id  PIO controller ID.
+ * \param pPio  PIO controller base address.
+ */
+extern void PioInterruptHandler( uint32_t id, Pio *pPio )
+{
+    uint32_t status;
+    uint32_t i;
+
+    /* Read PIO controller status */
+    status = pPio->PIO_ISR;
+    status &= pPio->PIO_IMR;
+
+    /* Check pending events */
+    if ( status != 0 )
+    {
+        TRACE_DEBUG( "PIO interrupt on PIO controller #%d\n\r", id ) ;
+
+        /* Find triggering source */
+        i = 0;
+        while ( status != 0 )
+        {
+            /* There cannot be an unconfigured source enabled. */
+            assert(i < _dwNumSources);
+
+            /* Source is configured on the same controller */
+            if (_aIntSources[i].pPin->id == id)
+            {
+                /* Source has PIOs whose statuses have changed */
+                if ( (status & _aIntSources[i].pPin->mask) != 0 )
+                {
+                    TRACE_DEBUG( "Interrupt source #%d triggered\n\r", i ) ;
+
+                    _aIntSources[i].handler(_aIntSources[i].pPin);
+                    status &= ~(_aIntSources[i].pPin->mask);
+                }
+            }
+            i++;
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *        Global Functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Parallel IO Controller A interrupt handler
+ * \Redefined PIOA interrupt handler for NVIC interrupt table.
+ */
+extern void PIOA_IrqHandler( void )
+{
+    if ( PIOA->PIO_PCISR != 0 )
+    {
+        PIO_CaptureHandler() ;
+    }
+
+    PioInterruptHandler( ID_PIOA, PIOA ) ;
+}
+
+/**
+ * \brief Parallel IO Controller B interrupt handler
+ * \Redefined PIOB interrupt handler for NVIC interrupt table.
+ */
+extern void PIOB_IrqHandler( void )
+{
+    PioInterruptHandler( ID_PIOB, PIOB ) ;
+}
+
+/**
+ * \brief Parallel IO Controller C interrupt handler
+ * \Redefined PIOC interrupt handler for NVIC interrupt table.
+ */
+extern void PIOC_IrqHandler( void )
+{
+    PioInterruptHandler( ID_PIOC, PIOC ) ;
+}
+
+/**
+ * \brief Initializes the PIO interrupt management logic
+ *
+ * The desired priority of PIO interrupts must be provided.
+ * Calling this function multiple times result in the reset of currently
+ * configured interrupts.
+ *
+ * \param priority  PIO controller interrupts priority.
+ */
+extern void PIO_InitializeInterrupts( uint32_t dwPriority )
+{
+    TRACE_DEBUG( "PIO_Initialize()\n\r" ) ;
+
+    /* Reset sources */
+    _dwNumSources = 0 ;
+
+    /* Configure PIO interrupt sources */
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOA ) ;
+    PIOA->PIO_ISR ;
+    PIOA->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOA_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOA_IRQn ) ;
+    NVIC_SetPriority( PIOA_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOA_IRQn ) ;
+
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOB ) ;
+    PIOB->PIO_ISR ;
+    PIOB->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOB_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOB_IRQn ) ;
+    NVIC_SetPriority( PIOB_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOB_IRQn ) ;
+
+    TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ;
+    PMC_EnablePeripheral( ID_PIOC ) ;
+    PIOC->PIO_ISR ;
+    PIOC->PIO_IDR = 0xFFFFFFFF ;
+    NVIC_DisableIRQ( PIOC_IRQn ) ;
+    NVIC_ClearPendingIRQ( PIOC_IRQn ) ;
+    NVIC_SetPriority( PIOC_IRQn, dwPriority ) ;
+    NVIC_EnableIRQ( PIOC_IRQn ) ;
+}
+
+/**
+ * Configures a PIO or a group of PIO to generate an interrupt on status
+ * change. The provided interrupt handler will be called with the triggering
+ * pin as its parameter (enabling different pin instances to share the same
+ * handler).
+ * \param pPin  Pointer to a Pin instance.
+ * \param handler  Interrupt handler function pointer.
+ */
+extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) )
+{
+    Pio* pio ;
+    InterruptSource* pSource ;
+
+    TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ;
+
+    assert( pPin ) ;
+    pio = pPin->pio ;
+    assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ;
+
+    /* Define new source */
+    TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%d.\n\r",  _dwNumSources ) ;
+
+    pSource = &(_aIntSources[_dwNumSources]) ;
+    pSource->pPin = pPin ;
+    pSource->handler = handler ;
+    _dwNumSources++ ;
+
+    /* PIO3 with additional interrupt support
+     * Configure additional interrupt mode registers */
+    if ( pPin->attribute & PIO_IT_AIME )
+    {
+        // enable additional interrupt mode
+        pio->PIO_AIMER       = pPin->mask ;
+
+        // if bit field of selected pin is 1, set as Rising Edge/High level detection event
+        if ( pPin->attribute & PIO_IT_RE_OR_HL )
+        {
+            pio->PIO_REHLSR    = pPin->mask ;
+        }
+        else
+        {
+            pio->PIO_FELLSR     = pPin->mask;
+        }
+
+        /* if bit field of selected pin is 1, set as edge detection source */
+        if (pPin->attribute & PIO_IT_EDGE)
+            pio->PIO_ESR     = pPin->mask;
+        else
+            pio->PIO_LSR     = pPin->mask;
+    }
+    else
+    {
+        /* disable additional interrupt mode */
+        pio->PIO_AIMDR       = pPin->mask;
+    }
+}
+
+/**
+ * Enables the given interrupt source if it has been configured. The status
+ * register of the corresponding PIO controller is cleared prior to enabling
+ * the interrupt.
+ * \param pPin  Interrupt source to enable.
+ */
+extern void PIO_EnableIt( const Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_ISR ;
+    pPio->PIO_IER = dwMask ;
+}
+
+/**
+ * Disables a given interrupt source, with no added side effects.
+ *
+ * \param pPin  Interrupt source to disable.
+ */
+extern void PIO_DisableIt( const Pio* pPio, const uint32_t dwMask )
+{
+    pPio->PIO_IDR = dwMask ;
+}
+

hardware/tools/libchip_sam3s/source/pmc.c

@@ -0,0 +1,167 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Local definitions
+ *----------------------------------------------------------------------------*/
+
+#define MASK_STATUS0 0xFFFFFFFC
+#define MASK_STATUS1 0xFFFFFFFF
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Enables the clock of a peripheral. The peripheral ID is used
+ * to identify which peripheral is targetted.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern void PMC_EnablePeripheral( uint32_t dwId )
+{
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
+        {
+//            TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral"  " %u is already enabled\n\r", dwId ) ;
+        }
+        else
+        {
+            PMC->PMC_PCER0 = 1 << dwId ;
+        }
+    }
+    else
+    {
+        dwId -= 32;
+        if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId))
+        {
+//            TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral"  " %u is already enabled\n\r", dwId + 32 ) ;
+        }
+        else
+        {
+            PMC->PMC_PCER1 = 1 << dwId ;
+        }
+    }
+}
+
+/**
+ * \brief Disables the clock of a peripheral. The peripheral ID is used
+ * to identify which peripheral is targetted.
+ *
+ * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern void PMC_DisablePeripheral( uint32_t dwId )
+{
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
+        {
+//            TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", dwId ) ;
+        }
+        else
+        {
+            PMC->PMC_PCDR0 = 1 << dwId ;
+        }
+    }
+    else
+    {
+        dwId -= 32 ;
+        if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
+        {
+//            TRACE_DEBUG( "PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", dwId + 32 ) ;
+        }
+        else
+        {
+            PMC->PMC_PCDR1 = 1 << dwId ;
+        }
+    }
+}
+
+/**
+ * \brief Enable all the periph clock via PMC.
+ */
+extern void PMC_EnableAllPeripherals( void )
+{
+    PMC->PMC_PCER0 = MASK_STATUS0 ;
+    while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0 ) ;
+
+    PMC->PMC_PCER1 = MASK_STATUS1 ;
+    while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1 ) ;
+
+//    TRACE_DEBUG( "Enable all periph clocks\n\r" ) ;
+}
+
+/**
+ * \brief Disable all the periph clock via PMC.
+ */
+extern void PMC_DisableAllPeripherals( void )
+{
+    PMC->PMC_PCDR0 = MASK_STATUS0 ;
+    while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != 0 ) ;
+
+    PMC->PMC_PCDR1 = MASK_STATUS1 ;
+    while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != 0 ) ;
+
+//    TRACE_DEBUG( "Disable all periph clocks\n\r" ) ;
+}
+
+/**
+ * \brief Get Periph Status for the given peripheral ID.
+ *
+ * \param id  Peripheral ID (ID_xxx).
+ */
+extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId )
+{
+    assert( dwId < 35 ) ;
+
+    if ( dwId < 32 )
+    {
+        return ( PMC->PMC_PCSR0 & (1 << dwId) ) ;
+    }
+    else {
+        return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ;
+    }
+}

hardware/tools/libchip_sam3s/source/pwmc.c

@@ -0,0 +1,608 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup pwm_module Working with PWM
+ * The PWM driver provides the interface to configure and use the PWM
+ * peripheral.
+ *
+ * The PWM macrocell controls square output waveforms of 4 channels.
+ * Characteristics of output waveforms such as period, duty-cycle,
+ * dead-time can be configured.\n
+ * Some of PWM channels can be linked together as synchronous channel and
+ * duty-cycle of synchronous channels can be updated by PDC automaticly.
+ *
+ * Before enabling the channels, they must have been configured first.
+ * The main settings include:
+ * <ul>
+ * <li>Configuration of the clock generator.</li>
+ * <li>Selection of the clock for each channel.</li>
+ * <li>Configuration of output waveform characteristics, such as period, duty-cycle etc.</li>
+ * <li>Configuration for synchronous channels if needed.</li>
+ *    - Selection of the synchronous channels.
+ *    - Selection of the moment when the WRDY flag and the corresponding PDC
+ *      transfer request are set (PTRM and PTRCS in the PWM_SCM register).
+ *    - Configuration of the update mode (UPDM in the PWM_SCM register).
+ *    - Configuration of the update period (UPR in the PWM_SCUP register).
+ * </ul>
+ *
+ * After the channels is enabled, the user must use respective update registers
+ * to change the wave characteristics to prevent unexpected output waveform.
+ * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle
+ * when the channel is enabled.
+ *
+ * For more accurate information, please look at the PWM section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref pwmc.c\n
+ * \ref pwmc.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of the Pulse Width Modulation Controller (PWM) peripheral.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *         Local functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Finds a prescaler/divisor couple to generate the desired frequency
+ * from MCK.
+ *
+ * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be
+ * met.
+ *
+ * \param frequency  Desired frequency in Hz.
+ * \param mck  Master clock frequency in Hz.
+ */
+static uint16_t FindClockConfiguration(
+    uint32_t frequency,
+    uint32_t mck)
+{
+    uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024};
+    uint8_t divisor = 0;
+    uint32_t prescaler;
+
+    assert(frequency < mck);
+
+    /* Find prescaler and divisor values */
+    prescaler = (mck / divisors[divisor]) / frequency;
+    while ((prescaler > 255) && (divisor < 11)) {
+
+        divisor++;
+        prescaler = (mck / divisors[divisor]) / frequency;
+    }
+
+    /* Return result */
+    if ( divisor < 11 )
+    {
+//        TRACE_DEBUG( "Found divisor=%u and prescaler=%u for freq=%uHz\n\r", divisors[divisor], prescaler, frequency ) ;
+
+        return prescaler | (divisor << 8) ;
+    }
+    else
+    {
+        return 0 ;
+    }
+}
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Configures PWM a channel with the given parameters, basic configure function.
+ *
+ * The PWM controller must have been clocked in the PMC prior to calling this
+ * function.
+ * Beware: this function disables the channel. It waits until disable is effective.
+ *
+ * \param channel  Channel number.
+ * \param prescaler  Channel prescaler.
+ * \param alignment  Channel alignment.
+ * \param polarity  Channel polarity.
+ */
+void PWMC_ConfigureChannel(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity)
+{
+    pPwm->PWM_CH_NUM[0].PWM_CMR = 1;
+
+//    assert(prescaler < PWM_CMR0_CPRE_MCKB);
+    assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
+    assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
+
+    /* Disable channel (effective at the end of the current period) */
+    if ((pPwm->PWM_SR & (1 << channel)) != 0) {
+        pPwm->PWM_DIS = 1 << channel;
+        while ((pPwm->PWM_SR & (1 << channel)) != 0);
+    }
+
+    /* Configure channel */
+    pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity;
+}
+
+/**
+ * \brief Configures PWM a channel with the given parameters, extend configure function.
+ *
+ * The PWM controller must have been clocked in the PMC prior to calling this
+ * function.
+ * Beware: this function disables the channel. It waits until disable is effective.
+ *
+ * \param channel            Channel number.
+ * \param prescaler          Channel prescaler.
+ * \param alignment          Channel alignment.
+ * \param polarity           Channel polarity.
+ * \param countEventSelect   Channel counter event selection.
+ * \param DTEnable           Channel dead time generator enable.
+ * \param DTHInverte         Channel Dead-Time PWMHx output Inverted.
+ * \param DTLInverte         Channel Dead-Time PWMHx output Inverted.
+ */
+void PWMC_ConfigureChannelExt(
+    Pwm* pPwm,
+    uint8_t channel,
+    uint32_t prescaler,
+    uint32_t alignment,
+    uint32_t polarity,
+    uint32_t countEventSelect,
+    uint32_t DTEnable,
+    uint32_t DTHInverte,
+    uint32_t DTLInverte)
+{
+//    assert(prescaler < PWM_CMR0_CPRE_MCKB);
+    assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0);
+    assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0);
+    assert((countEventSelect & (uint32_t)~PWM_CMR_CES) == 0);
+    assert((DTEnable & (uint32_t)~PWM_CMR_DTE) == 0);
+    assert((DTHInverte & (uint32_t)~PWM_CMR_DTHI) == 0);
+    assert((DTLInverte & (uint32_t)~PWM_CMR_DTLI) == 0);
+
+    /* Disable channel (effective at the end of the current period) */
+    if ((pPwm->PWM_SR & (1 << channel)) != 0) {
+        pPwm->PWM_DIS = 1 << channel;
+        while ((pPwm->PWM_SR & (1 << channel)) != 0);
+    }
+
+    /* Configure channel */
+    pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity |
+        countEventSelect | DTEnable | DTHInverte | DTLInverte;
+}
+
+/**
+ * \brief Configures PWM clocks A & B to run at the given frequencies.
+ *
+ * This function finds the best MCK divisor and prescaler values automatically.
+ *
+ * \param clka  Desired clock A frequency (0 if not used).
+ * \param clkb  Desired clock B frequency (0 if not used).
+ * \param mck  Master clock frequency.
+ */
+void PWMC_ConfigureClocks(uint32_t clka, uint32_t clkb, uint32_t mck)
+{
+    uint32_t mode = 0;
+    uint32_t result;
+
+    /* Clock A */
+    if (clka != 0) {
+
+        result = FindClockConfiguration(clka, mck);
+        assert( result != 0 ) ;
+        mode |= result;
+    }
+
+    /* Clock B */
+    if (clkb != 0) {
+
+        result = FindClockConfiguration(clkb, mck);
+        assert( result != 0 ) ;
+        mode |= (result << 16);
+    }
+
+    /* Configure clocks */
+//    TRACE_DEBUG( "Setting PWM_CLK = 0x%08X\n\r", mode ) ;
+    PWM->PWM_CLK = mode;
+}
+
+/**
+ * \brief Sets the period value used by a PWM channel.
+ *
+ * This function writes directly to the CPRD register if the channel is disabled;
+ * otherwise, it uses the update register CPRDUPD.
+ *
+ * \param channel Channel number.
+ * \param period  Period value.
+ */
+void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period)
+{
+    /* If channel is disabled, write to CPRD */
+    if ((pPwm->PWM_SR & (1 << channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CPRD = period;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period;
+    }
+}
+
+/**
+ * \brief Sets the duty cycle used by a PWM channel.
+ * This function writes directly to the CDTY register if the channel is disabled;
+ * otherwise it uses the update register CDTYUPD.
+ * Note that the duty cycle must always be inferior or equal to the channel
+ * period.
+ *
+ * \param channel  Channel number.
+ * \param duty     Duty cycle value.
+ */
+void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty)
+{
+    assert(duty <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
+
+    /* If channel is disabled, write to CDTY */
+    if ((pPwm->PWM_SR & (1 << channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CDTY = duty;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_CH_NUM[channel].PWM_CDTYUPD = duty;
+    }
+}
+
+/**
+ * \brief Sets the dead time used by a PWM channel.
+ * This function writes directly to the DT register if the channel is disabled;
+ * otherwise it uses the update register DTUPD.
+ * Note that the dead time must always be inferior or equal to the channel
+ * period.
+ *
+ * \param channel  Channel number.
+ * \param timeH    Dead time value for PWMHx output.
+ * \param timeL    Dead time value for PWMLx output.
+ */
+void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL)
+{
+    assert(timeH <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
+    assert(timeL <= pPwm->PWM_CH_NUM[channel].PWM_CPRD);
+
+    /* If channel is disabled, write to DT */
+    if ((pPwm->PWM_SR & (1 << channel)) == 0) {
+
+        pPwm->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16);
+    }
+    /* Otherwise use update register */
+    else {
+        pPwm->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16);
+    }
+}
+
+/**
+ * \brief Configures Syncronous channel with the given parameters.
+ * Beware: At this time, the channels should be disabled.
+ *
+ * \param channels                 Bitwise OR of Syncronous channels.
+ * \param updateMode               Syncronous channel update mode.
+ * \param requestMode              PDC transfer request mode.
+ * \param requestComparisonSelect  PDC transfer request comparison selection.
+ */
+void PWMC_ConfigureSyncChannel( Pwm* pPwm,
+    uint32_t channels,
+    uint32_t updateMode,
+    uint32_t requestMode,
+    uint32_t requestComparisonSelect)
+{
+    pPwm->PWM_SCM = channels | updateMode | requestMode | requestComparisonSelect;
+}
+
+/**
+ * \brief Sets the update period of the synchronous channels.
+ * This function writes directly to the SCUP register if the channel #0 is disabled;
+ * otherwise it uses the update register SCUPUPD.
+ *
+ * \param period   update period.
+ */
+void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period)
+{
+    /* If channel is disabled, write to SCUP */
+    if ((pPwm->PWM_SR & (1 << 0)) == 0) {
+
+        pPwm->PWM_SCUP = period;
+    }
+    /* Otherwise use update register */
+    else {
+
+        pPwm->PWM_SCUPUPD = period;
+    }
+}
+
+/**
+ * \brief Sets synchronous channels update unlock.
+ *
+ * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1
+ * triggers the update of the period value, the duty-cycle and
+ * the dead-time values of synchronous channels at the beginning
+ * of the next PWM period. If the field UPDM is set to 1 or 2,
+ * writing the UPDULOCK bit to 1 triggers only the update of
+ * the period value and of the dead-time values of synchronous channels.
+ * This bit is automatically reset when the update is done.
+ */
+void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm )
+{
+    pPwm->PWM_SCUC = PWM_SCUC_UPDULOCK;
+}
+
+/**
+ * \brief Enables the given PWM channel.
+ *
+ * This does NOT enable the corresponding pin;this must be done in the user code.
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_ENA = 1 << channel;
+}
+
+/**
+ * \brief Disables the given PWM channel.
+ *
+ * Beware, channel will be effectively disabled at the end of the current period.
+ * Application can check channel is disabled using the following wait loop:
+ * while ((PWM->PWM_SR & (1 << channel)) != 0);
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_DIS = 1 << channel;
+}
+
+/**
+ * \brief Enables the period interrupt for the given PWM channel.
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_IER1 = 1 << channel;
+}
+
+/**
+ * \brief Disables the period interrupt for the given PWM channel.
+ *
+ * \param channel  Channel number.
+ */
+void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel)
+{
+    pPwm->PWM_IDR1 = 1 << channel;
+}
+
+/**
+ * \brief Enables the selected interrupts sources on a PWMC peripheral.
+ *
+ * \param sources1  Bitwise OR of selected interrupt sources of PWM_IER1.
+ * \param sources2  Bitwise OR of selected interrupt sources of PWM_IER2.
+ */
+void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
+{
+    pPwm->PWM_IER1 = sources1;
+    pPwm->PWM_IER2 = sources2;
+}
+
+/**
+ * \brief Disables the selected interrupts sources on a PWMC peripheral.
+ *
+ * \param sources1  Bitwise OR of selected interrupt sources of PWM_IDR1.
+ * \param sources2  Bitwise OR of selected interrupt sources of PWM_IDR2.
+ */
+void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2)
+{
+    pPwm->PWM_IDR1 = sources1;
+    pPwm->PWM_IDR2 = sources2;
+}
+
+/**
+ * \brief Sends the contents of buffer through a PWMC peripheral, using the PDC to
+ * take care of the transfer.
+ *
+ * Note: Duty cycle of syncronous channels can update by PDC
+ *       when the field UPDM (Update Mode) in the PWM_SCM register is set to 2.
+ *
+ * \param pwmc    Pointer to an Pwm instance.
+ * \param buffer  Data buffer to send.
+ * \param length  Length of the data buffer.
+ */
+uint8_t PWMC_WriteBuffer(Pwm *pwmc,
+    void *buffer,
+    uint32_t length)
+{
+    /* Check if first bank is free */
+    if (pwmc->PWM_TCR == 0) {
+
+        pwmc->PWM_TPR = (uint32_t) buffer;
+        pwmc->PWM_TCR = length;
+        pwmc->PWM_PTCR = PERIPH_PTCR_TXTEN;
+        return 1;
+    }
+    /* Check if second bank is free */
+    else if (pwmc->PWM_TNCR == 0) {
+
+        pwmc->PWM_TNPR = (uint32_t) buffer;
+        pwmc->PWM_TNCR = length;
+        return 1;
+    }
+
+    /* No free banks */
+    return 0;
+}
+
+/**
+ * \brief Set PWM output override value.
+ *
+ * \param value  Bitwise OR of output override value.
+ */
+void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_OOV = value;
+}
+
+/**
+ * \brief Enalbe override output.
+ *
+ * \param value  Bitwise OR of output selection.
+ * \param sync   0: enable the output asyncronously, 1: enable it syncronously
+ */
+void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)
+{
+    if (sync) {
+
+        pPwm->PWM_OSSUPD = value;
+    } else {
+
+        pPwm->PWM_OSS = value;
+    }
+}
+
+/**
+ * \brief Disalbe override output.
+ *
+ * \param value  Bitwise OR of output selection.
+ * \param sync   0: enable the output asyncronously, 1: enable it syncronously
+ */
+void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync)
+{
+    if (sync) {
+
+        pPwm->PWM_OSCUPD = value;
+    } else {
+
+        pPwm->PWM_OSC = value;
+    }
+}
+
+/**
+ * \brief Set PWM fault mode.
+ *
+ * \param mode  Bitwise OR of fault mode.
+ */
+void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode)
+{
+    pPwm->PWM_FMR = mode;
+}
+
+/**
+ * \brief PWM fault clear.
+ *
+ * \param fault  Bitwise OR of fault to clear.
+ */
+void PWMC_FaultClear( Pwm* pPwm, uint32_t fault)
+{
+    pPwm->PWM_FCR = fault;
+}
+
+/**
+ * \brief Set PWM fault protection value.
+ *
+ * \param value  Bitwise OR of fault protection value.
+ */
+void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_FPV = value;
+}
+
+/**
+ * \brief Enable PWM fault protection.
+ *
+ * \param value  Bitwise OR of FPEx[y].
+ */
+void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value)
+{
+    pPwm->PWM_FPE = value;
+}
+
+/**
+ * \brief Configure comparison unit.
+ *
+ * \param x     comparison x index
+ * \param value comparison x value.
+ * \param mode  comparison x mode
+ */
+void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode)
+{
+    assert(x < 8);
+
+    /* If channel is disabled, write to CMPxM & CMPxV */
+    if ((pPwm->PWM_SR & (1 << 0)) == 0) {
+        pPwm->PWM_CMP[x].PWM_CMPxM = mode;
+        pPwm->PWM_CMP[x].PWM_CMPxV = value;
+    }
+    /* Otherwise use update register */
+    else {
+        pPwm->PWM_CMP[x].PWM_CMPxMUPD = mode;
+        pPwm->PWM_CMP[x].PWM_CMPxVUPD = value;
+    }
+}
+
+/**
+ * \brief Configure event line mode.
+ *
+ * \param x    Line x
+ * \param mode Bitwise OR of line mode selection
+ */
+void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode)
+{
+    assert(x < 2);
+
+    if (x == 0) {
+        pPwm->PWM_ELxMR[0] = mode;
+    } else if (x == 1) {
+        pPwm->PWM_ELxMR[1] = mode;
+    }
+}

hardware/tools/libchip_sam3s/source/rtc.c

@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup rtc_module Working with RTC
+ * The RTC driver provides the interface to configure and use the RTC
+ * peripheral.
+ *
+ * It manages date, time, and alarms.\n
+ * This timer is clocked by the 32kHz system clock, and is not impacted by
+ * power management settings (PMC). To be accurate, it is better to use an
+ * external 32kHz crystal instead of the internal 32kHz RC.\n
+ *
+ * It uses BCD format, and time can be set in AM/PM or 24h mode through a
+ * configuration bit in the mode register.\n
+ *
+ * To update date or time, the user has to follow these few steps :
+ * <ul>
+ * <li>Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,</li>
+ * <li>Polling or IRQ on the ACKUPD bit of RTC_CR,</li>
+ * <li>Clear ACKUPD bit in RTC_SCCR,</li>
+ * <li>Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),</li>
+ * <li>Clear UPDTIM and/or UPDCAL bit in RTC_CR.</li>
+ * </ul>
+ * An alarm can be set to happen on month, date, hours, minutes or seconds,
+ * by setting the proper "Enable" bit of each of these fields in the Time and
+ * Calendar registers.
+ * This allows a large number of configurations to be available for the user.
+ * Alarm occurence can be detected even by polling or interrupt.
+ *
+ * A check of the validity of the date and time format and values written by the user is automatically done.
+ * Errors are reported through the Valid Entry Register.
+ *
+ * For more accurate information, please look at the RTC section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref rtc.c\n
+ * \ref rtc.h.\n
+*/
+/*@{*/
+/*@}*/
+
+
+/**
+ * \file
+ *
+ * Implementation of Real Time Clock (RTC) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+#include <stdint.h>
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Sets the RTC in either 12 or 24 hour mode.
+ *
+ * \param mode  Hour mode.
+ */
+extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode )
+{
+    assert((dwMode & 0xFFFFFFFE) == 0);
+
+    pRtc->RTC_MR = dwMode ;
+}
+
+/**
+ * \brief Gets the RTC mode.
+ *
+ * \return Hour mode.
+ */
+extern uint32_t RTC_GetHourMode( Rtc* pRtc )
+{
+    uint32_t dwMode ;
+
+    dwMode = pRtc->RTC_MR;
+    dwMode &= 0xFFFFFFFE;
+
+    return dwMode ;
+}
+
+/**
+ * \brief Enables the selected interrupt sources of the RTC.
+ *
+ * \param sources  Interrupt sources to enable.
+ */
+extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources )
+{
+    assert((dwSources & (uint32_t)(~0x1F)) == 0);
+
+    pRtc->RTC_IER = dwSources ;
+}
+
+/**
+* \brief Disables the selected interrupt sources of the RTC.
+*
+* \param sources  Interrupt sources to disable.
+*/
+extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources )
+{
+    assert((dwSources & (uint32_t)(~0x1F)) == 0);
+
+    pRtc->RTC_IDR = dwSources ;
+}
+
+/**
+ * \brief Sets the current time in the RTC.
+ *
+ * \note In successive update operations, the user must wait at least one second
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these
+ * bits again. Please look at the RTC section of the datasheet for detail.
+ *
+ * \param ucHour    Current hour in 12 or 24 hour mode.
+ * \param ucMinute  Current minute.
+ * \param ucSecond  Current second.
+ *
+ * \return 0 sucess, 1 fail to set
+ */
+extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond )
+{
+    uint32_t dwTime=0 ;
+    uint8_t ucHour_bcd ;
+    uint8_t ucMin_bcd ;
+    uint8_t ucSec_bcd ;
+
+    /* if 12-hour mode, set AMPM bit */
+    if ( (pRtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD )
+    {
+        if ( ucHour > 12 )
+        {
+            ucHour -= 12 ;
+            dwTime |= RTC_TIMR_AMPM ;
+        }
+    }
+    ucHour_bcd = (ucHour%10)   | ((ucHour/10)<<4) ;
+    ucMin_bcd  = (ucMinute%10) | ((ucMinute/10)<<4) ;
+    ucSec_bcd  = (ucSecond%10) | ((ucSecond/10)<<4) ;
+
+    /* value overflow */
+    if ( (ucHour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) |
+         (ucMin_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) |
+         (ucSec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK)))
+    {
+        return 1 ;
+    }
+
+    dwTime = ucSec_bcd | (ucMin_bcd << 8) | (ucHour_bcd<<16) ;
+
+    pRtc->RTC_CR |= RTC_CR_UPDTIM ;
+    while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+    pRtc->RTC_SCCR = RTC_SCCR_ACKCLR ;
+    pRtc->RTC_TIMR = dwTime ;
+    pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ;
+    pRtc->RTC_SCCR |= RTC_SCCR_SECCLR ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVTIM) ;
+}
+
+/**
+ * \brief Retrieves the current time as stored in the RTC in several variables.
+ *
+ * \param pucHour    If not null, current hour is stored in this variable.
+ * \param pucMinute  If not null, current minute is stored in this variable.
+ * \param pucSecond  If not null, current second is stored in this variable.
+ */
+extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )
+{
+    uint32_t dwTime ;
+
+    /* Get current RTC time */
+    dwTime = pRtc->RTC_TIMR ;
+    while ( dwTime != pRtc->RTC_TIMR )
+    {
+        dwTime = pRtc->RTC_TIMR ;
+    }
+
+    /* Hour */
+    if ( pucHour )
+    {
+        *pucHour = ((dwTime & 0x00300000) >> 20) * 10
+                 + ((dwTime & 0x000F0000) >> 16);
+
+        if ( (dwTime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM )
+        {
+            *pucHour += 12 ;
+        }
+    }
+
+    /* Minute */
+    if ( pucMinute )
+    {
+        *pucMinute = ((dwTime & 0x00007000) >> 12) * 10
+                   + ((dwTime & 0x00000F00) >> 8);
+    }
+
+    /* Second */
+    if ( pucSecond )
+    {
+        *pucSecond = ((dwTime & 0x00000070) >> 4) * 10
+                   + (dwTime & 0x0000000F);
+    }
+}
+
+/**
+ * \brief Sets a time alarm on the RTC.
+ * The match is performed only on the provided variables;
+ * Setting all pointers to 0 disables the time alarm.
+ *
+ * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for
+ * AM (as expected in the time registers).
+ *
+ * \param pucHour    If not null, the time alarm will hour-match this value.
+ * \param pucMinute  If not null, the time alarm will minute-match this value.
+ * \param pucSecond  If not null, the time alarm will second-match this value.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, uint8_t *pucSecond )
+{
+    uint32_t dwAlarm=0 ;
+
+    /* Hour */
+    if ( pucHour )
+    {
+        dwAlarm |= RTC_TIMALR_HOUREN | ((*pucHour / 10) << 20) | ((*pucHour % 10) << 16);
+    }
+
+    /* Minute */
+    if ( pucMinute )
+    {
+        dwAlarm |= RTC_TIMALR_MINEN | ((*pucMinute / 10) << 12) | ((*pucMinute % 10) << 8);
+    }
+
+    /* Second */
+    if ( pucSecond )
+    {
+        dwAlarm |= RTC_TIMALR_SECEN | ((*pucSecond / 10) << 4) | (*pucSecond % 10);
+    }
+
+    pRtc->RTC_TIMALR = dwAlarm ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVTIMALR) ;
+}
+
+/**
+ * \brief Retrieves the current year, month and day from the RTC.
+ * Month, day and week values are numbered starting at 1.
+ *
+ * \param pYwear  Current year (optional).
+ * \param pucMonth  Current month (optional).
+ * \param pucDay  Current day (optional).
+ * \param pucWeek  Current day in current week (optional).
+ */
+extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, uint8_t *pucDay, uint8_t *pucWeek )
+{
+    uint32_t dwDate ;
+
+    /* Get current date (multiple reads are necessary to insure a stable value) */
+    do
+    {
+        dwDate = pRtc->RTC_CALR ;
+    }
+    while ( dwDate != pRtc->RTC_CALR ) ;
+
+    /* Retrieve year */
+    if ( pwYear )
+    {
+        *pwYear = (((dwDate  >> 4) & 0x7) * 1000)
+                 + ((dwDate & 0xF) * 100)
+                 + (((dwDate >> 12) & 0xF) * 10)
+                 + ((dwDate >> 8) & 0xF);
+    }
+
+    /* Retrieve month */
+    if ( pucMonth )
+    {
+        *pucMonth = (((dwDate >> 20) & 1) * 10) + ((dwDate >> 16) & 0xF);
+    }
+
+    /* Retrieve day */
+    if ( pucDay )
+    {
+        *pucDay = (((dwDate >> 28) & 0x3) * 10) + ((dwDate >> 24) & 0xF);
+    }
+
+    /* Retrieve week */
+    if ( pucWeek )
+    {
+        *pucWeek = ((dwDate >> 21) & 0x7);
+    }
+}
+
+/**
+ * \brief Sets the current year, month and day in the RTC.
+ * Month, day and week values must be numbered starting from 1.
+ *
+ * \note In successive update operations, the user must wait at least one second
+ * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these
+ * bits again. Please look at the RTC section of the datasheet for detail.
+ *
+ * \param wYear  Current year.
+ * \param ucMonth Current month.
+ * \param ucDay   Current day.
+ * \param ucWeek  Day number in current week.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, uint8_t ucDay, uint8_t ucWeek )
+{
+    uint32_t wDate ;
+    uint8_t ucCent_bcd ;
+    uint8_t ucYear_bcd ;
+    uint8_t ucMonth_bcd ;
+    uint8_t ucDay_bcd ;
+    uint8_t ucWeek_bcd ;
+
+    ucCent_bcd  = ((wYear/100)%10) | ((wYear/1000)<<4);
+    ucYear_bcd  = (wYear%10) | (((wYear/10)%10)<<4);
+    ucMonth_bcd = ((ucMonth%10) | (ucMonth/10)<<4);
+    ucDay_bcd   = ((ucDay%10) | (ucDay/10)<<4);
+    ucWeek_bcd  = ((ucWeek%10) | (ucWeek/10)<<4);
+
+    /* value over flow */
+    if ( (ucCent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) |
+         (ucYear_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) |
+         (ucMonth_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) |
+         (ucWeek_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) |
+         (ucDay_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK))
+       )
+    {
+        return 1 ;
+    }
+
+
+    /* Convert values to date register value */
+    wDate = ucCent_bcd |
+            (ucYear_bcd << 8) |
+            (ucMonth_bcd << 16) |
+            (ucWeek_bcd << 21) |
+            (ucDay_bcd << 24);
+
+    /* Update calendar register  */
+    pRtc->RTC_CR |= RTC_CR_UPDCAL ;
+    while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ;
+
+    pRtc->RTC_SCCR = RTC_SCCR_ACKCLR;
+    pRtc->RTC_CALR = wDate ;
+    pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ;
+    pRtc->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVCAL) ;
+}
+
+/**
+ * \brief Sets a date alarm in the RTC.
+ * The alarm will match only the provided values;
+ * Passing a null-pointer disables the corresponding field match.
+ *
+ * \param pucMonth If not null, the RTC alarm will month-match this value.
+ * \param pucDay   If not null, the RTC alarm will day-match this value.
+ *
+ * \return 0 success, 1 fail to set
+ */
+extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay )
+{
+    uint32_t dwAlarm ;
+
+    dwAlarm = ((pucMonth) || (pucDay)) ? (0) : (0x01010000);
+
+    /* Compute alarm field value */
+    if ( pucMonth )
+    {
+        dwAlarm |= RTC_CALALR_MTHEN | ((*pucMonth / 10) << 20) | ((*pucMonth % 10) << 16);
+    }
+
+    if ( pucDay )
+    {
+        dwAlarm |= RTC_CALALR_DATEEN | ((*pucDay / 10) << 28) | ((*pucDay % 10) << 24);
+    }
+
+    /* Set alarm */
+    pRtc->RTC_CALALR = dwAlarm ;
+
+    return (int)(pRtc->RTC_VER & RTC_VER_NVCALALR) ;
+}
+
+/**
+ * \brief Clear flag bits of status clear command register in the RTC.
+ *
+ * \param mask Bits mask of cleared events
+ */
+extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask )
+{
+    /* Clear all flag bits in status clear command register */
+    dwMask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR | RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR ;
+
+    pRtc->RTC_SCCR = dwMask ;
+}
+
+/**
+ * \brief Get flag bits of status register in the RTC.
+ *
+ * \param mask Bits mask of Status Register
+ *
+ * \return Status register & mask
+ */
+extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask )
+{
+    uint32_t dwEvent ;
+
+    dwEvent = pRtc->RTC_SR ;
+
+    return (dwEvent & dwMask) ;
+}
+

hardware/tools/libchip_sam3s/source/rtt.c

@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------------
+ *         ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/** \addtogroup rtt_module Working with RTT
+ * The RTT driver provides the interface to configure and use the RTT
+ * peripheral.
+ *
+ * The Real-time Timer is used to count elapsed seconds.\n
+ * This timer is clocked by the 32kHz system clock divided by a programmable
+ * 16-bit balue. To be accurate, it is better to use an
+ * external 32kHz crystal instead of the internal 32kHz RC.\n
+ *
+ * To count elapsed seconds, the user could follow these few steps:
+ * <ul>
+ * <li>Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.</li>
+ * <li>Writing the bit RTTRST in RTT_MR to restart the timer with new settings.</li>
+ * </ul>
+ *
+ * An alarm can be set to happen on second by setting alarm value in RTT_AR.
+ * Alarm occurence can be detected by polling or interrupt.
+ *
+ * For more accurate information, please look at the RTT section of the
+ * Datasheet.
+ *
+ * Related files :\n
+ * \ref rtt.c\n
+ * \ref rtt.h.\n
+ */
+/*@{*/
+/*@}*/
+
+/**
+ * \file
+ *
+ * Implementation of Real Time Timer (RTT) controller.
+ *
+ */
+
+/*----------------------------------------------------------------------------
+ *        Headers
+ *----------------------------------------------------------------------------*/
+#include "chip.h"
+
+#include <assert.h>
+
+/*----------------------------------------------------------------------------
+ *        Exported functions
+ *----------------------------------------------------------------------------*/
+
+/**
+ * \brief Changes the prescaler value of the given RTT and restarts it.
+ *
+ * \note This function disables RTT interrupt sources.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ * \param prescaler  Prescaler value for the RTT.
+ */
+void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler)
+{
+    rtt->RTT_MR = (prescaler |  RTT_MR_RTTRST);
+}
+
+/**
+ * \brief Returns the current value of the RTT timer value.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ */
+uint32_t RTT_GetTime(Rtt *rtt)
+{
+    return rtt->RTT_VR;
+}
+
+/**
+ * \brief Enables the specified RTT interrupt sources.
+ *
+ * \param rtt  Pointer to a Rtt instance.
+ * \param sources  Bitmask of interrupts to enable.
+ */
+void RTT_EnableIT(Rtt *rtt, uint32_t sources)
+{
+    assert( (sources & 0x0004FFFF) == 0 ) ;
+    rtt->RTT_MR |= sources;
+}
+
+/**
+ * \brief Returns the status register value of the given RTT.
+ *
+ * \param rtt  Pointer to an Rtt instance.
+ */
+uint32_t RTT_GetStatus(Rtt *rtt)
+{
+    return rtt->RTT_SR;
+}
+
+/**
+ * \brief Configures the RTT to generate an alarm at the given time.
+ *
+ * \param pRtt  Pointer to an Rtt instance.
+ * \param time  Alarm time.
+ */
+void RTT_SetAlarm(Rtt *pRtt, uint32_t time)
+{
+    assert(time > 0);
+
+    pRtt->RTT_AR = time - 1;
+}