Improve how TXCn bit is cleared in USCRnA register
Preserve values of configuration bits MPCMn and U2Xn. Avoid setting other read-only bits for datasheet conformance. See #3745
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@ -97,8 +97,10 @@ void HardwareSerial::_tx_udr_empty_irq(void)
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// location". This makes sure flush() won't return until the bytes
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// location". This makes sure flush() won't return until the bytes
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// actually got written
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// actually got written. Other r/w bits are preserved, and zeroes
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sbi(*_ucsra, TXC0);
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// written to the rest.
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*_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << MPCM0))) | (1 << TXC0);
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if (_tx_buffer_head == _tx_buffer_tail) {
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if (_tx_buffer_head == _tx_buffer_tail) {
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// Buffer empty, so disable interrupts
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// Buffer empty, so disable interrupts
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@ -225,7 +227,7 @@ size_t HardwareSerial::write(uint8_t c)
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// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
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// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
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if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) {
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if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) {
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*_udr = c;
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*_udr = c;
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sbi(*_ucsra, TXC0);
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*_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << MPCM0))) | (1 << TXC0);
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return 1;
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return 1;
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}
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}
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tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE;
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tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE;
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