Fixing millis() overflow: changing millis() and the timer 0 overflow handler so that the millis count is updated in the interrupt, and so we don't need to do a conversion inside millis(). Updated to do list.
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@ -24,26 +24,29 @@
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#include "wiring_private.h"
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// The number of times timer 0 has overflowed since the program started.
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// Must be volatile or gcc will optimize away some uses of it.
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volatile unsigned long timer0_overflow_count;
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volatile unsigned long timer0_clock_cycles = 0;
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volatile unsigned long timer0_millis = 0;
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SIGNAL(SIG_OVERFLOW0)
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{
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timer0_overflow_count++;
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// timer 0 prescale factor is 64 and the timer overflows at 256
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timer0_clock_cycles += 64UL * 256UL;
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while (timer0_clock_cycles > clockCyclesPerMicrosecond() * 1000UL) {
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timer0_clock_cycles -= clockCyclesPerMicrosecond() * 1000UL;
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timer0_millis++;
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}
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}
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unsigned long millis()
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{
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// timer 0 increments every 64 cycles, and overflows when it reaches
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// 256. we would calculate the total number of clock cycles, then
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// divide by the number of clock cycles per millisecond, but this
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// overflows too often.
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//return timer0_overflow_count * 64UL * 256UL / (F_CPU / 1000UL);
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unsigned long m;
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uint8_t oldSREG = SREG;
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// instead find 1/128th the number of clock cycles and divide by
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// 1/128th the number of clock cycles per millisecond
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return timer0_overflow_count * 64UL * 2UL / (F_CPU / 128000UL);
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cli();
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m = timer0_millis;
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SREG = oldSREG;
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return m;
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}
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void delay(unsigned long ms)
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@ -122,8 +125,6 @@ void init()
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// work there
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sei();
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// timer 0 is used for millis() and delay()
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timer0_overflow_count = 0;
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// on the ATmega168, timer 0 is also used for fast hardware pwm
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// (using phase-correct PWM would mean that timer 0 overflowed half as often
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// resulting in different millis() behavior on the ATmega8 and ATmega168)
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