396 lines
11 KiB
C++
396 lines
11 KiB
C++
/*
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HardwareSerial.cpp - Hardware serial library for Wiring
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Copyright (c) 2006 Nicholas Zambetti. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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Modified 23 November 2006 by David A. Mellis
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Modified 28 September 2010 by Mark Sproul
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Modified 14 August 2012 by Alarus
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "Arduino.h"
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#include "wiring_private.h"
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#include "HardwareSerial.h"
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// this next line disables the entire HardwareSerial.cpp,
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// this is so I can support Attiny series and any other chip without a uart
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#if defined(HAVE_HWSERIAL0) || defined(HAVE_HWSERIAL1) || defined(HAVE_HWSERIAL2) || defined(HAVE_HWSERIAL3)
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// Ensure that the various bit positions we use are available with a 0
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// postfix, so we can always use the values for UART0 for all UARTs. The
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// alternative, passing the various values for each UART to the
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// HardwareSerial constructor also works, but makes the code bigger and
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// slower.
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#if !defined(TXC0)
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#if defined(TXC)
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// On ATmega8, the uart and its bits are not numbered, so there is no TXC0 etc.
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#define TXC0 TXC
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#define RXEN0 RXEN
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#define TXEN0 TXEN
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#define RXCIE0 RXCIE
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#define UDRIE0 UDRIE
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#define U2X0 U2X
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#define UPE0 UPE
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#define UDRE0 UDRE
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#elif defined(TXC1)
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// Some devices have uart1 but no uart0
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#define TXC0 TXC1
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#define RXEN0 RXEN1
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#define TXEN0 TXEN1
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#define RXCIE0 RXCIE1
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#define UDRIE0 UDRIE1
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#define U2X0 U2X1
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#define UPE0 UPE1
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#define UDRE0 UDRE1
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#else
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#error No UART found in HardwareSerial.cpp
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#endif
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#endif // !defined TXC0
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// Check at compiletime that it is really ok to use the bit positions of
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// UART0 for the other UARTs as well, in case these values ever get
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// changed for future hardware.
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#if defined(TXC1) && (TXC1 != TXC0 || RXEN1 != RXEN0 || RXCIE1 != RXCIE0 || \
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UDRIE1 != UDRIE0 || U2X1 != U2X0 || UPE1 != UPE0 || \
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UDRE1 != UDRE0)
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#error "Not all bit positions for UART1 are the same as for UART0"
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#endif
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#if defined(TXC2) && (TXC2 != TXC0 || RXEN2 != RXEN0 || RXCIE2 != RXCIE0 || \
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UDRIE2 != UDRIE0 || U2X2 != U2X0 || UPE2 != UPE0 || \
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UDRE2 != UDRE0)
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#error "Not all bit positions for UART2 are the same as for UART0"
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#endif
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#if defined(TXC3) && (TXC3 != TXC0 || RXEN3 != RXEN0 || RXCIE3 != RXCIE0 || \
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UDRIE3 != UDRIE0 || U3X3 != U3X0 || UPE3 != UPE0 || \
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UDRE3 != UDRE0)
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#error "Not all bit positions for UART3 are the same as for UART0"
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#endif
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#if defined(HAVE_HWSERIAL0)
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void serialEvent() __attribute__((weak));
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void serialEvent() {}
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#if defined(USART_RX_vect)
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ISR(USART_RX_vect)
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#elif defined(USART0_RX_vect)
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ISR(USART0_RX_vect)
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#elif defined(USART_RXC_vect)
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ISR(USART_RXC_vect) // ATmega8
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#else
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#error "Don't know what the Data Received vector is called for the first UART"
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#endif
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{
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Serial._rx_complete_irq();
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}
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#endif
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#if defined(HAVE_HWSERIAL1)
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void serialEvent1() __attribute__((weak));
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void serialEvent1() {}
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ISR(USART1_RX_vect)
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{
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Serial1._rx_complete_irq();
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}
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#endif
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#if defined(HAVE_HWSERIAL2)
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void serialEvent2() __attribute__((weak));
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void serialEvent2() {}
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ISR(USART2_RX_vect)
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{
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Serial2._rx_complete_irq();
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}
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#endif
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#if defined(HAVE_HWSERIAL3)
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void serialEvent3() __attribute__((weak));
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void serialEvent3() {}
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ISR(USART3_RX_vect)
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{
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Serial3._rx_complete_irq();
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}
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#endif
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void serialEventRun(void)
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{
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#if defined(HAVE_HWSERIAL0)
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if (Serial.available()) serialEvent();
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#endif
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#if defined(HAVE_HWSERIAL1)
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if (Serial1.available()) serialEvent1();
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#endif
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#if defined(HAVE_HWSERIAL2)
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if (Serial2.available()) serialEvent2();
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#endif
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#if defined(HAVE_HWSERIAL3)
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if (Serial3.available()) serialEvent3();
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#endif
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}
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#if defined(HAVE_HWSERIAL0)
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#if defined(UART0_UDRE_vect)
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ISR(UART0_UDRE_vect)
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#elif defined(UART_UDRE_vect)
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ISR(UART_UDRE_vect)
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#elif defined(USART0_UDRE_vect)
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ISR(USART0_UDRE_vect)
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#elif defined(USART_UDRE_vect)
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ISR(USART_UDRE_vect)
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#else
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#error "Don't know what the Data Register Empty vector is called for the first UART"
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#endif
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{
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Serial._tx_udr_empty_irq();
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}
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#endif
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#if defined(HAVE_HWSERIAL1)
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ISR(USART1_UDRE_vect)
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{
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Serial1._tx_udr_empty_irq();
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}
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#endif
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#if defined(HAVE_HWSERIAL2)
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ISR(USART2_UDRE_vect)
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{
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Serial2._tx_udr_empty_irq();
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}
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#endif
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#if defined(HAVE_HWSERIAL3)
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ISR(USART3_UDRE_vect)
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{
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Serial3._tx_udr_empty_irq();
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}
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#endif
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// Actual interrupt handlers //////////////////////////////////////////////////////////////
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void HardwareSerial::_rx_complete_irq(void)
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{
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if (bit_is_clear(*_ucsra, UPE0)) {
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// No Parity error, read byte and store it in the buffer if there is
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// room
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unsigned char c = *_udr;
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int i = (unsigned int)(_rx_buffer_head + 1) % SERIAL_BUFFER_SIZE;
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// if we should be storing the received character into the location
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// just before the tail (meaning that the head would advance to the
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// current location of the tail), we're about to overflow the buffer
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// and so we don't write the character or advance the head.
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if (i != _rx_buffer_tail) {
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_rx_buffer[_rx_buffer_head] = c;
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_rx_buffer_head = i;
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}
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} else {
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// Parity error, read byte but discard it
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unsigned char c = *_udr;
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};
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}
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void HardwareSerial::_tx_udr_empty_irq(void)
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{
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// If interrupts are enabled, there must be more data in the output
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// buffer. Send the next byte
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unsigned char c = _tx_buffer[_tx_buffer_tail];
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_tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_BUFFER_SIZE;
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*_udr = c;
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// clear the TXC bit -- "can be cleared by writing a one to its bit
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// location". This makes sure flush() won't return until the bytes
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// actually got written
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sbi(*_ucsra, TXC0);
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if (_tx_buffer_head == _tx_buffer_tail) {
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// Buffer empty, so disable interrupts
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cbi(*_ucsrb, UDRIE0);
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}
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}
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// Constructors ////////////////////////////////////////////////////////////////
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HardwareSerial::HardwareSerial(
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volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
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volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
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volatile uint8_t *ucsrc, volatile uint8_t *udr)
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{
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_tx_buffer_head = _tx_buffer_tail = 0;
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_rx_buffer_head = _rx_buffer_tail = 0;
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_ubrrh = ubrrh;
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_ubrrl = ubrrl;
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_ucsra = ucsra;
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_ucsrb = ucsrb;
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_ucsrc = ucsrc;
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_udr = udr;
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}
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// Public Methods //////////////////////////////////////////////////////////////
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void HardwareSerial::begin(unsigned long baud, byte config)
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{
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// Try u2x mode first
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uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2;
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*_ucsra = 1 << U2X0;
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// hardcoded exception for 57600 for compatibility with the bootloader
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// shipped with the Duemilanove and previous boards and the firmware
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// on the 8U2 on the Uno and Mega 2560. Also, The baud_setting cannot
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// be > 4095, so switch back to non-u2x mode if the baud rate is too
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// low.
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if (((F_CPU == 16000000UL) && (baud == 57600)) || (baud_setting >4095))
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{
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*_ucsra = 0;
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baud_setting = (F_CPU / 8 / baud - 1) / 2;
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}
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// assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
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*_ubrrh = baud_setting >> 8;
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*_ubrrl = baud_setting;
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_written = false;
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//set the data bits, parity, and stop bits
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#if defined(__AVR_ATmega8__)
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config |= 0x80; // select UCSRC register (shared with UBRRH)
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#endif
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*_ucsrc = config;
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sbi(*_ucsrb, RXEN0);
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sbi(*_ucsrb, TXEN0);
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sbi(*_ucsrb, RXCIE0);
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cbi(*_ucsrb, UDRIE0);
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}
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void HardwareSerial::end()
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{
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// wait for transmission of outgoing data
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while (_tx_buffer_head != _tx_buffer_tail)
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;
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cbi(*_ucsrb, RXEN0);
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cbi(*_ucsrb, TXEN0);
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cbi(*_ucsrb, RXCIE0);
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cbi(*_ucsrb, UDRIE0);
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// clear any received data
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_rx_buffer_head = _rx_buffer_tail;
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}
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int HardwareSerial::available(void)
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{
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return (unsigned int)(SERIAL_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail) % SERIAL_BUFFER_SIZE;
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}
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int HardwareSerial::peek(void)
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{
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if (_rx_buffer_head == _rx_buffer_tail) {
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return -1;
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} else {
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return _rx_buffer[_rx_buffer_tail];
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}
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}
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int HardwareSerial::read(void)
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{
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// if the head isn't ahead of the tail, we don't have any characters
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if (_rx_buffer_head == _rx_buffer_tail) {
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return -1;
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} else {
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unsigned char c = _rx_buffer[_rx_buffer_tail];
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_rx_buffer_tail = (unsigned int)(_rx_buffer_tail + 1) % SERIAL_BUFFER_SIZE;
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return c;
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}
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}
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void HardwareSerial::flush()
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{
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// If we have never written a byte, no need to flush. This special
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// case is needed since there is no way to force the TXC (transmit
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// complete) bit to 1 during initialization
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if (!_written)
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return;
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while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) {
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if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0))
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// Interrupts are globally disabled, but the DR empty
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// interrupt should be enabled, so poll the DR empty flag to
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// prevent deadlock
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if (bit_is_set(*_ucsra, UDRE0))
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_tx_udr_empty_irq();
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}
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// If we get here, nothing is queued anymore (DRIE is disabled) and
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// the hardware finished tranmission (TXC is set).
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}
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size_t HardwareSerial::write(uint8_t c)
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{
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int i = (_tx_buffer_head + 1) % SERIAL_BUFFER_SIZE;
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// If the output buffer is full, there's nothing for it other than to
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// wait for the interrupt handler to empty it a bit
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while (i == _tx_buffer_tail) {
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if (bit_is_clear(SREG, SREG_I)) {
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// Interrupts are disabled, so we'll have to poll the data
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// register empty flag ourselves. If it is set, pretend an
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// interrupt has happened and call the handler to free up
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// space for us.
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if(bit_is_set(*_ucsra, UDRE0))
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_tx_udr_empty_irq();
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} else {
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// nop, the interrupt handler will free up space for us
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}
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}
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_tx_buffer[_tx_buffer_head] = c;
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_tx_buffer_head = i;
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sbi(*_ucsrb, UDRIE0);
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_written = true;
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return 1;
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}
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// Preinstantiate Objects //////////////////////////////////////////////////////
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#if defined(HAVE_HWSERIAL0)
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#if defined(UBRRH) && defined(UBRRL)
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HardwareSerial Serial(&UBRRH, &UBRRL, &UCSRA, &UCSRB, &UCSRC, &UDR);
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#else
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HardwareSerial Serial(&UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UCSR0C, &UDR0);
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#endif
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#endif
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#if defined(HAVE_HWSERIAL1)
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HardwareSerial Serial1(&UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UCSR1C, &UDR1);
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#endif
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#if defined(HAVE_HWSERIAL2)
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HardwareSerial Serial2(&UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UCSR2C, &UDR2);
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#endif
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#if defined(HAVE_HWSERIAL3)
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HardwareSerial Serial3(&UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UCSR3C, &UDR3);
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#endif
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#endif // whole file
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