95 lines
3.6 KiB
C
95 lines
3.6 KiB
C
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/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2012 LeafLabs, LLC.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f2/include/series/dac.h
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* @brief STM32F2 DAC support
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*/
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#ifndef _LIBMAPLE_STM32F2_DAC_H_
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#define _LIBMAPLE_STM32F2_DAC_H_
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#ifdef __cplusplus
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extern "C"{
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#endif
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#include <libmaple/libmaple_types.h>
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/*
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* Register map type
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*/
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/** STM32F2 DAC register map type. */
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typedef struct dac_reg_map {
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__io uint32 CR; /**< Control register */
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__io uint32 SWTRIGR; /**< Software trigger register */
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__io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
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holding register */
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__io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
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holding register */
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__io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
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holding register */
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__io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
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holding register */
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__io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
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holding register */
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__io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
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holding register */
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__io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
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holding register */
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__io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
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holding register */
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__io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
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register */
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__io uint32 DOR1; /**< Channel 1 data output register */
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__io uint32 DOR2; /**< Channel 2 data output register */
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__io uint32 SR; /**< Status register */
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} dac_reg_map;
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/*
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* Register bit definitions
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*/
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/* Control register */
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#define DAC_CR_DMAUDRIE1 (1U << 13) /* Channel 1 DMA underrun
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* interrupt enable */
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#define DAC_CR_DMAUDRIE2 (1U << 29) /* Channel 2 DMA underrun
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* interrupt enable */
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/* Status register */
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#define DAC_SR_DMAUDR1 (1U << 13) /* Channel 1 DMA underrun
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* occurred */
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#define DAC_SR_DMAUDR2 (1U << 29) /* Channel 2 DMA underrun
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* ocurred */
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#ifdef __cplusplus
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}
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#endif
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#endif
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