2014-12-28 06:29:08 -08:00
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/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file gpio.h
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*
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* @brief General purpose I/O (GPIO) and Alternate Function I/O
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* (AFIO) prototypes, defines, and inlined access functions.
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*/
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2017-05-10 15:57:08 -07:00
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#ifndef _GPIO_DEF_H_
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#define _GPIO_DEF_H_
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2014-12-28 06:29:08 -08:00
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#include "libmaple.h"
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#include "rcc.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*
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* GPIO register maps and devices
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*/
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/** GPIO register map type */
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typedef struct gpio_reg_map {
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__io uint32 MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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__io uint32 OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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__io uint32 OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
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__io uint32 PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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__io uint32 IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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__io uint32 ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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__io uint16 BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
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__io uint16 BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
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__io uint32 LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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__io uint32 AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */
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} gpio_reg_map;
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/**
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* @brief External interrupt line port selector.
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*
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* Used to determine which GPIO port to map an external interrupt line
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* onto. */
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/* (See AFIO sections, below) */
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typedef enum afio_exti_port {
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AFIO_EXTI_PA, /**< Use port A (PAx) pin. */
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AFIO_EXTI_PB, /**< Use port B (PBx) pin. */
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AFIO_EXTI_PC, /**< Use port C (PCx) pin. */
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AFIO_EXTI_PD, /**< Use port D (PDx) pin. */
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#ifdef STM32_HIGH_DENSITY
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AFIO_EXTI_PE, /**< Use port E (PEx) pin. */
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#if 0 // not available on LQFP 100 package
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AFIO_EXTI_PF, /**< Use port F (PFx) pin. */
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AFIO_EXTI_PG, /**< Use port G (PGx) pin. */
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#endif // not available on LQFP 100 package
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#endif
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} afio_exti_port;
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2014-12-28 06:29:08 -08:00
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/** GPIO device type */
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typedef struct gpio_dev {
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gpio_reg_map *regs; /**< Register map */
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rcc_clk_id clk_id; /**< RCC clock information */
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afio_exti_port exti_port; /**< AFIO external interrupt port value */
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} gpio_dev;
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extern const gpio_dev GPIOA;
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extern const gpio_dev GPIOB;
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extern const gpio_dev GPIOC;
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extern const gpio_dev GPIOD;
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#ifdef STM32_HIGH_DENSITY
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extern const gpio_dev GPIOE;
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#if 0 // not available on LQFP 100 package
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extern gpio_dev gpiof;
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extern gpio_dev* const GPIOF;
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extern gpio_dev gpiog;
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extern gpio_dev* const GPIOG;
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#endif // not available on LQFP 100 package
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#endif
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/** GPIO port register map base pointer */
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#define GPIOA_BASE ((struct gpio_reg_map*)0x40020000)
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#define GPIOB_BASE ((struct gpio_reg_map*)0x40020400)
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#define GPIOC_BASE ((struct gpio_reg_map*)0x40020800)
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#define GPIOD_BASE ((struct gpio_reg_map*)0x40020C00)
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#ifdef STM32_HIGH_DENSITY
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#define GPIOE_BASE ((struct gpio_reg_map*)0x40021000)
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#if 0 // not available on LQFP 100 package
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#define GPIOF_BASE ((struct gpio_reg_map*)0x40021400)
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#define GPIOG_BASE ((struct gpio_reg_map*)0x40021800)
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#endif // not available on LQFP 100 package
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#endif
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/*
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* GPIO register bit definitions
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*/
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#define GPIO_MODE_INPUT 0
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#define GPIO_MODE_OUTPUT 1
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#define GPIO_MODE_AF 2
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#define GPIO_MODE_ANALOG 3
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#define GPIO_PUPD_NONE (0 << 2)
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#define GPIO_PUPD_PU (1 << 2)
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#define GPIO_PUPD_PD (2 << 2)
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#define GPIO_OSPEED_2MHZ (0 << 4)
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#define GPIO_OSPEED_25MHZ (1 << 4)
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#define GPIO_OSPEED_50MHZ (2 << 4)
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#define GPIO_OSPEED_100MHZ (3 << 4)
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#define GPIO_OTYPE_PP (0 << 6)
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#define GPIO_OTYPE_OD (1 << 6)
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/*
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MODER
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00: Input (reset state)
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01: General purpose output mode
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10: Alternate function mode
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11: Analog mode
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OTYPER
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0: Output push-pull (reset state)
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1: Output open-drain
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OSPEEDR
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00: 2 MHz Low speed
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01: 25 MHz Medium speed
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10: 50 MHz Fast speed
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11: 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF)
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PUPDR
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00: No pull-up, pull-down
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01: Pull-up
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10: Pull-down
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AFRL 4 bit AF00-AF15
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AFRH 4 bit AF00-AF15
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*/
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/**
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* @brief GPIO Pin modes.
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*
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* These only allow for 50MHZ max output speeds; if you want slower,
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* use direct register access.
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*/
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typedef enum gpio_pin_mode {
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GPIO_OUTPUT_PP = (GPIO_MODE_OUTPUT | GPIO_OTYPE_PP |
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GPIO_OSPEED_50MHZ), /**< Output push-pull. */
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GPIO_OUTPUT_OD = (GPIO_MODE_OUTPUT | GPIO_OTYPE_OD |
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GPIO_OSPEED_50MHZ), /**< Output open-drain. */
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GPIO_AF_OUTPUT_PP = (GPIO_MODE_AF | GPIO_OTYPE_PP |
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GPIO_OSPEED_50MHZ), /**< Alternate function
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output push-pull. */
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GPIO_AF_OUTPUT_PP_PU = (GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_PUPD_PU |
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GPIO_OSPEED_50MHZ), /**< Alternate function
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output push-pull. */
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GPIO_AF_OUTPUT_OD = (GPIO_MODE_AF | GPIO_OTYPE_OD |
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GPIO_OSPEED_50MHZ), /**< Alternate function
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output open drain. */
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GPIO_INPUT_ANALOG = (GPIO_MODE_ANALOG), /**< Analog input. */
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GPIO_INPUT_FLOATING = (GPIO_MODE_INPUT |
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GPIO_PUPD_NONE), /**< Input floating. */
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GPIO_INPUT_PU = (GPIO_MODE_INPUT | GPIO_PUPD_PU), /**< Input pull-up. */
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GPIO_INPUT_PD = (GPIO_MODE_INPUT | GPIO_PUPD_PD), /**< Input pull-down. */
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GPIO_AF_INPUT_PU = (GPIO_MODE_AF | GPIO_PUPD_PU), /**< Alternate input pull-up. */
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GPIO_AF_INPUT_PD = (GPIO_MODE_AF | GPIO_PUPD_PD), /**< Alternate input pull-down. */
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GPIO_BIGNUMBER = 0xfff
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} gpio_pin_mode;
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/*
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* AFIO register map
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*/
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/** AFIO register map */
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typedef struct syscfg_reg_map {
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__io uint32 MEMRM; /**< memory remap register */
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__io uint32 PMC; /**< peripheral mode configuration register */
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__io uint32 EXTICR1; /**< External interrupt configuration register 1. */
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__io uint32 EXTICR2; /**< External interrupt configuration register 2. */
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__io uint32 EXTICR3; /**< External interrupt configuration register 3. */
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__io uint32 EXTICR4; /**< External interrupt configuration register 4. */
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__io uint32 CMPCR; /**< Compensation cell control register */
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} syscfg_reg_map;
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/** AFIO register map base pointer. */
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#define SYSCFG_BASE ((struct syscfg_reg_map *)0x40013800)
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/*
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* AFIO register bit definitions
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*/
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/* Event control register */
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#define AFIO_EVCR_EVOE (0x1 << 7)
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#define AFIO_EVCR_PORT_PA (0x0 << 4)
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#define AFIO_EVCR_PORT_PB (0x1 << 4)
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#define AFIO_EVCR_PORT_PC (0x2 << 4)
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#define AFIO_EVCR_PORT_PD (0x3 << 4)
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#define AFIO_EVCR_PORT_PE (0x4 << 4)
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#define AFIO_EVCR_PIN_0 0x0
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#define AFIO_EVCR_PIN_1 0x1
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#define AFIO_EVCR_PIN_2 0x2
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#define AFIO_EVCR_PIN_3 0x3
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#define AFIO_EVCR_PIN_4 0x4
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#define AFIO_EVCR_PIN_5 0x5
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#define AFIO_EVCR_PIN_6 0x6
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#define AFIO_EVCR_PIN_7 0x7
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#define AFIO_EVCR_PIN_8 0x8
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#define AFIO_EVCR_PIN_9 0x9
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#define AFIO_EVCR_PIN_10 0xA
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#define AFIO_EVCR_PIN_11 0xB
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#define AFIO_EVCR_PIN_12 0xC
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#define AFIO_EVCR_PIN_13 0xD
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#define AFIO_EVCR_PIN_14 0xE
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#define AFIO_EVCR_PIN_15 0xF
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/* AF remap and debug I/O configuration register */
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#define AFIO_MAPR_SWJ_CFG (0x7 << 24)
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#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
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#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST (0x1 << 24)
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#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW (0x2 << 24)
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#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW (0x4 << 24)
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#define AFIO_MAPR_ADC2_ETRGREG_REMAP BIT(20)
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#define AFIO_MAPR_ADC2_ETRGINJ_REMAP BIT(19)
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#define AFIO_MAPR_ADC1_ETRGREG_REMAP BIT(18)
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#define AFIO_MAPR_ADC1_ETRGINJ_REMAP BIT(17)
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#define AFIO_MAPR_TIM5CH4_IREMAP BIT(16)
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#define AFIO_MAPR_PD01_REMAP BIT(15)
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#define AFIO_MAPR_CAN_REMAP (0x3 << 13)
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#define AFIO_MAPR_CAN_REMAP_NONE (0x0 << 13)
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#define AFIO_MAPR_CAN_REMAP_PB8_PB9 (0x2 << 13)
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#define AFIO_MAPR_CAN_REMAP_PD0_PD1 (0x3 << 13)
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#define AFIO_MAPR_TIM4_REMAP BIT(12)
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#define AFIO_MAPR_TIM3_REMAP (0x3 << 10)
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#define AFIO_MAPR_TIM3_REMAP_NONE (0x0 << 10)
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#define AFIO_MAPR_TIM3_REMAP_PARTIAL (0x2 << 10)
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#define AFIO_MAPR_TIM3_REMAP_FULL (0x3 << 10)
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#define AFIO_MAPR_TIM2_REMAP (0x3 << 8)
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#define AFIO_MAPR_TIM2_REMAP_NONE (0x0 << 8)
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#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 (0x1 << 8)
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#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
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#define AFIO_MAPR_TIM2_REMAP_FULL (0x3 << 8)
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#define AFIO_MAPR_TIM1_REMAP (0x3 << 6)
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#define AFIO_MAPR_TIM1_REMAP_NONE (0x0 << 6)
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#define AFIO_MAPR_TIM1_REMAP_PARTIAL (0x1 << 6)
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#define AFIO_MAPR_TIM1_REMAP_FULL (0x3 << 6)
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#define AFIO_MAPR_USART3_REMAP (0x3 << 4)
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#define AFIO_MAPR_USART3_REMAP_NONE (0x0 << 4)
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#define AFIO_MAPR_USART3_REMAP_PARTIAL (0x1 << 4)
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#define AFIO_MAPR_USART3_REMAP_FULL (0x3 << 4)
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#define AFIO_MAPR_USART2_REMAP BIT(3)
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#define AFIO_MAPR_USART1_REMAP BIT(2)
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#define AFIO_MAPR_I2C1_REMAP BIT(1)
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#define AFIO_MAPR_SPI1_REMAP BIT(0)
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/* External interrupt configuration register 1 */
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#define AFIO_EXTICR1_EXTI3 (0xF << 12)
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#define AFIO_EXTICR1_EXTI3_PA (0x0 << 12)
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#define AFIO_EXTICR1_EXTI3_PB (0x1 << 12)
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#define AFIO_EXTICR1_EXTI3_PC (0x2 << 12)
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#define AFIO_EXTICR1_EXTI3_PD (0x3 << 12)
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#define AFIO_EXTICR1_EXTI3_PE (0x4 << 12)
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#define AFIO_EXTICR1_EXTI3_PF (0x5 << 12)
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#define AFIO_EXTICR1_EXTI3_PG (0x6 << 12)
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#define AFIO_EXTICR1_EXTI2 (0xF << 8)
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#define AFIO_EXTICR1_EXTI2_PA (0x0 << 8)
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#define AFIO_EXTICR1_EXTI2_PB (0x1 << 8)
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#define AFIO_EXTICR1_EXTI2_PC (0x2 << 8)
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#define AFIO_EXTICR1_EXTI2_PD (0x3 << 8)
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#define AFIO_EXTICR1_EXTI2_PE (0x4 << 8)
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#define AFIO_EXTICR1_EXTI2_PF (0x5 << 8)
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#define AFIO_EXTICR1_EXTI2_PG (0x6 << 8)
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#define AFIO_EXTICR1_EXTI1 (0xF << 4)
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#define AFIO_EXTICR1_EXTI1_PA (0x0 << 4)
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#define AFIO_EXTICR1_EXTI1_PB (0x1 << 4)
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#define AFIO_EXTICR1_EXTI1_PC (0x2 << 4)
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#define AFIO_EXTICR1_EXTI1_PD (0x3 << 4)
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#define AFIO_EXTICR1_EXTI1_PE (0x4 << 4)
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#define AFIO_EXTICR1_EXTI1_PF (0x5 << 4)
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#define AFIO_EXTICR1_EXTI1_PG (0x6 << 4)
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#define AFIO_EXTICR1_EXTI0 0xF
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#define AFIO_EXTICR1_EXTI0_PA 0x0
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#define AFIO_EXTICR1_EXTI0_PB 0x1
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#define AFIO_EXTICR1_EXTI0_PC 0x2
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#define AFIO_EXTICR1_EXTI0_PD 0x3
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#define AFIO_EXTICR1_EXTI0_PE 0x4
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#define AFIO_EXTICR1_EXTI0_PF 0x5
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#define AFIO_EXTICR1_EXTI0_PG 0x6
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/* External interrupt configuration register 2 */
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#define AFIO_EXTICR2_EXTI7 (0xF << 12)
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#define AFIO_EXTICR2_EXTI7_PA (0x0 << 12)
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#define AFIO_EXTICR2_EXTI7_PB (0x1 << 12)
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#define AFIO_EXTICR2_EXTI7_PC (0x2 << 12)
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#define AFIO_EXTICR2_EXTI7_PD (0x3 << 12)
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#define AFIO_EXTICR2_EXTI7_PE (0x4 << 12)
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#define AFIO_EXTICR2_EXTI7_PF (0x5 << 12)
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#define AFIO_EXTICR2_EXTI7_PG (0x6 << 12)
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#define AFIO_EXTICR2_EXTI6 (0xF << 8)
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#define AFIO_EXTICR2_EXTI6_PA (0x0 << 8)
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#define AFIO_EXTICR2_EXTI6_PB (0x1 << 8)
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#define AFIO_EXTICR2_EXTI6_PC (0x2 << 8)
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#define AFIO_EXTICR2_EXTI6_PD (0x3 << 8)
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#define AFIO_EXTICR2_EXTI6_PE (0x4 << 8)
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#define AFIO_EXTICR2_EXTI6_PF (0x5 << 8)
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#define AFIO_EXTICR2_EXTI6_PG (0x6 << 8)
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#define AFIO_EXTICR2_EXTI5 (0xF << 4)
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#define AFIO_EXTICR2_EXTI5_PA (0x0 << 4)
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#define AFIO_EXTICR2_EXTI5_PB (0x1 << 4)
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#define AFIO_EXTICR2_EXTI5_PC (0x2 << 4)
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#define AFIO_EXTICR2_EXTI5_PD (0x3 << 4)
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#define AFIO_EXTICR2_EXTI5_PE (0x4 << 4)
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#define AFIO_EXTICR2_EXTI5_PF (0x5 << 4)
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#define AFIO_EXTICR2_EXTI5_PG (0x6 << 4)
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#define AFIO_EXTICR2_EXTI4 0xF
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#define AFIO_EXTICR2_EXTI4_PA 0x0
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#define AFIO_EXTICR2_EXTI4_PB 0x1
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#define AFIO_EXTICR2_EXTI4_PC 0x2
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#define AFIO_EXTICR2_EXTI4_PD 0x3
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#define AFIO_EXTICR2_EXTI4_PE 0x4
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#define AFIO_EXTICR2_EXTI4_PF 0x5
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#define AFIO_EXTICR2_EXTI4_PG 0x6
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/* AF remap and debug I/O configuration register 2 */
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#define AFIO_MAPR2_FSMC_NADV BIT(10)
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#define AFIO_MAPR2_TIM14_REMAP BIT(9)
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#define AFIO_MAPR2_TIM13_REMAP BIT(8)
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#define AFIO_MAPR2_TIM11_REMAP BIT(7)
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#define AFIO_MAPR2_TIM10_REMAP BIT(6)
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#define AFIO_MAPR2_TIM9_REMAP BIT(5)
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/*
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* AFIO convenience routines
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*/
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void afio_init(void);
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/**
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* External interrupt line numbers.
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*/
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typedef enum afio_exti_num {
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AFIO_EXTI_0, /**< External interrupt line 0. */
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AFIO_EXTI_1, /**< External interrupt line 1. */
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AFIO_EXTI_2, /**< External interrupt line 2. */
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AFIO_EXTI_3, /**< External interrupt line 3. */
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AFIO_EXTI_4, /**< External interrupt line 4. */
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AFIO_EXTI_5, /**< External interrupt line 5. */
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AFIO_EXTI_6, /**< External interrupt line 6. */
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AFIO_EXTI_7, /**< External interrupt line 7. */
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AFIO_EXTI_8, /**< External interrupt line 8. */
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AFIO_EXTI_9, /**< External interrupt line 9. */
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AFIO_EXTI_10, /**< External interrupt line 10. */
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AFIO_EXTI_11, /**< External interrupt line 11. */
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AFIO_EXTI_12, /**< External interrupt line 12. */
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AFIO_EXTI_13, /**< External interrupt line 13. */
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AFIO_EXTI_14, /**< External interrupt line 14. */
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AFIO_EXTI_15, /**< External interrupt line 15. */
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} afio_exti_num;
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void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
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/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
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* not used in either MAPR or MAPR2 */
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#define AFIO_REMAP_USE_MAPR2 (1 << 31)
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/**
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* @brief Available peripheral remaps.
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* @see afio_remap()
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*/
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typedef enum afio_remap_peripheral {
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AFIO_REMAP_ADC2_ETRGREG = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
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ADC 2 external trigger regular conversion remapping */
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AFIO_REMAP_ADC2_ETRGINJ = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
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ADC 2 external trigger injected conversion remapping */
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AFIO_REMAP_ADC1_ETRGREG = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
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ADC 1 external trigger regular conversion remapping */
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AFIO_REMAP_ADC1_ETRGINJ = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
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ADC 1 external trigger injected conversion remapping */
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AFIO_REMAP_TIM5CH4_I = AFIO_MAPR_TIM5CH4_IREMAP, /**<
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Timer 5 channel 4 internal remapping */
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AFIO_REMAP_PD01 = AFIO_MAPR_PD01_REMAP, /**<
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Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
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AFIO_REMAP_CAN_1 = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
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CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
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AFIO_REMAP_CAN_2 = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
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CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
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AFIO_REMAP_TIM4 = AFIO_MAPR_TIM4_REMAP, /**<
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Timer 4 remapping */
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AFIO_REMAP_TIM3_PARTIAL = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
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Timer 3 partial remapping */
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AFIO_REMAP_TIM3_FULL = AFIO_MAPR_TIM3_REMAP_FULL, /**<
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Timer 3 full remapping */
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AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
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Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
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on PA2, CH4 on PA3) */
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AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
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Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
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on PB10, CH4 on PB11) */
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AFIO_REMAP_TIM2_FULL = AFIO_MAPR_TIM2_REMAP_FULL, /**<
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Timer 2 full remapping */
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AFIO_REMAP_USART2 = AFIO_MAPR_USART2_REMAP, /**<
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USART 2 remapping */
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AFIO_REMAP_USART1 = AFIO_MAPR_USART1_REMAP, /**<
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USART 1 remapping */
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AFIO_REMAP_I2C1 = AFIO_MAPR_I2C1_REMAP, /**<
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I2C 1 remapping */
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AFIO_REMAP_SPI1 = AFIO_MAPR_SPI1_REMAP, /**<
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SPI 1 remapping */
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AFIO_REMAP_FSMC_NADV = (AFIO_MAPR2_FSMC_NADV |
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AFIO_REMAP_USE_MAPR2), /**<
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NADV signal not connected */
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AFIO_REMAP_TIM14 = (AFIO_MAPR2_TIM14_REMAP |
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AFIO_REMAP_USE_MAPR2), /**<
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Timer 14 remapping */
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AFIO_REMAP_TIM13 = (AFIO_MAPR2_TIM13_REMAP |
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AFIO_REMAP_USE_MAPR2), /**<
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Timer 13 remapping */
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AFIO_REMAP_TIM11 = (AFIO_MAPR2_TIM11_REMAP |
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AFIO_REMAP_USE_MAPR2), /**<
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Timer 11 remapping */
|
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AFIO_REMAP_TIM10 = (AFIO_MAPR2_TIM10_REMAP |
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AFIO_REMAP_USE_MAPR2), /**<
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Timer 10 remapping */
|
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AFIO_REMAP_TIM9 = (AFIO_MAPR2_TIM9_REMAP |
|
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|
AFIO_REMAP_USE_MAPR2) /**<
|
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|
Timer 9 */
|
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|
} afio_remap_peripheral;
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void afio_remap(afio_remap_peripheral p);
|
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/**
|
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|
|
* @brief Debug port configuration
|
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|
|
*
|
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|
|
* Used to configure the behavior of JTAG and Serial Wire (SW) debug
|
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|
|
* ports and their associated GPIO pins.
|
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|
|
*
|
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|
|
* @see afio_cfg_debug_ports()
|
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|
|
*/
|
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|
typedef enum afio_debug_cfg {
|
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|
AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
|
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|
|
Full Serial Wire and JTAG debug */
|
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|
|
AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
|
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|
|
Full Serial Wire and JTAG, but no NJTRST. */
|
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|
AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
|
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|
|
Serial Wire debug only (JTAG-DP disabled,
|
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|
|
SW-DP enabled) */
|
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|
|
AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
|
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|
|
No debug; all JTAG and SW pins are free
|
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|
|
for use as GPIOs. */
|
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|
|
} afio_debug_cfg;
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#ifdef __cplusplus
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}
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#endif
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#endif
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