271 lines
9.6 KiB
C
271 lines
9.6 KiB
C
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/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Michael Hope.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file dma.h
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*
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* @author Marti Bolivar <mbolivar@leaflabs.com>;
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* Original implementation by Michael Hope
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*
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* @brief Direct Memory Access peripheral support
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*/
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/*
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* See /notes/dma.txt for more information.
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*/
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#ifndef _DMA_H_
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#define _DMA_H_
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#include "libmaple_types.h"
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#include "rcc.h"
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#include "nvic.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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/*
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* Register maps
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*/
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/**
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* @brief DMA stream type.
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*
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*/
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typedef struct dma_stream_t {
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__io uint32 CR; /**< Stream configuration register */
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__io uint32 NDTR; /**< Stream number of data register */
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__io uint32 PAR; /**< Stream peripheral address register */
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__io uint32 M0AR; /**< Stream memory address register 0 */
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__io uint32 M1AR; /**< Stream memory address register 1 */
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__io uint32 FCR; /**< Stream FIFO configuration register */
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} dma_stream_t;
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/**
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* @brief DMA register map type.
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*
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*/
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typedef struct dma_reg_map {
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__io uint32 LISR; /**< Low interrupt status register */
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__io uint32 HISR; /**< High interrupt status register */
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__io uint32 LIFCR; /**< Low interrupt flag clear register */
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__io uint32 HIFCR; /**< High interrupt flag clear register */
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dma_stream_t STREAM[8];
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} dma_reg_map;
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/** DMA controller register map base pointers */
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#define DMA1_BASE ((struct dma_reg_map*)0x40026000)
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#define DMA2_BASE ((struct dma_reg_map*)0x40026400)
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/*
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* Register bit definitions
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*/
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/* Channel configuration register */
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#define DMA_CR_CH0 (0x0 << 25)
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#define DMA_CR_CH1 (0x1 << 25)
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#define DMA_CR_CH2 (0x2 << 25)
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#define DMA_CR_CH3 (0x3 << 25)
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#define DMA_CR_CH4 (0x4 << 25)
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#define DMA_CR_CH5 (0x5 << 25)
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#define DMA_CR_CH6 (0x6 << 25)
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#define DMA_CR_CH7 (0x7 << 25)
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#define DMA_CR_MBURST0 (0x0 << 23)
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#define DMA_CR_MBURST4 (0x1 << 23)
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#define DMA_CR_MBURST8 (0x2 << 23)
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#define DMA_CR_MBURST16 (0x3 << 23)
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#define DMA_CR_PBURST0 (0x0 << 21)
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#define DMA_CR_PBURST4 (0x1 << 21)
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#define DMA_CR_PBURST8 (0x2 << 21)
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#define DMA_CR_PBURST16 (0x3 << 21)
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#define DMA_CR_CT0 (0x0 << 19)
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#define DMA_CR_CT1 (0x1 << 19)
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#define DMA_CR_DBM (0x1 << 18)
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#define DMA_CR_PL_LOW (0x0 << 16)
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#define DMA_CR_PL_MEDIUM (0x1 << 16)
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#define DMA_CR_PL_HIGH (0x2 << 16)
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#define DMA_CR_PL_VERY_HIGH (0x3 << 16)
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#define DMA_CR_PL_MASK (0x3 << 16)
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#define DMA_CR_PINCOS (0x1 << 15)
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#define DMA_CR_MSIZE_8BITS (0x0 << 13)
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#define DMA_CR_MSIZE_16BITS (0x1 << 13)
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#define DMA_CR_MSIZE_32BITS (0x2 << 13)
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#define DMA_CR_PSIZE_8BITS (0x0 << 11)
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#define DMA_CR_PSIZE_16BITS (0x1 << 11)
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#define DMA_CR_PSIZE_32BITS (0x2 << 11)
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#define DMA_CR_MINC (0x1 << 10)
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#define DMA_CR_PINC (0x1 << 9)
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#define DMA_CR_CIRC (0x1 << 8)
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#define DMA_CR_DIR_P2M (0x0 << 6)
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#define DMA_CR_DIR_M2P (0x1 << 6)
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#define DMA_CR_DIR_M2M (0x2 << 6)
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#define DMA_CR_PFCTRL (0x1 << 5)
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#define DMA_CR_TCIE (0x1 << 4)
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#define DMA_CR_HTIE (0x1 << 3)
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#define DMA_CR_TEIE (0x1 << 2)
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#define DMA_CR_DMEIE (0x1 << 1)
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#define DMA_CR_EN (0x1)
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/*
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* Devices
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*/
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/** Encapsulates state related to a DMA channel interrupt. */
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typedef struct dma_handler_config {
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void (*handler)(void); /**< User-specified channel interrupt
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handler */
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nvic_irq_num irq_line; /**< Channel's NVIC interrupt number */
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} dma_handler_config;
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/** DMA device type */
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typedef struct dma_dev {
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dma_reg_map *regs; /**< Register map */
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rcc_clk_id clk_id; /**< Clock ID */
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dma_handler_config handlers[]; /**<
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* @brief IRQ handlers and NVIC numbers.
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*
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* @see dma_attach_interrupt()
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* @see dma_detach_interrupt()
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*/
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} dma_dev;
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extern dma_dev *DMA1;
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extern dma_dev *DMA2;
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/*
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* Convenience functions
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*/
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void dma_init(dma_dev *dev);
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/** Flags for DMA transfer configuration. */
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typedef enum dma_mode_flags {
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DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */
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DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */
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DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */
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DMA_CIRC_MODE = 1 << 5, /**< Circular mode */
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DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */
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DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */
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DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */
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DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */
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} dma_mode_flags;
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/** Source and destination transfer sizes. */
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typedef enum dma_xfer_size {
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DMA_SIZE_8BITS = 0, /**< 8-bit transfers */
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DMA_SIZE_16BITS = 1, /**< 16-bit transfers */
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DMA_SIZE_32BITS = 2 /**< 32-bit transfers */
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} dma_xfer_size;
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/** DMA channel */
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typedef enum dma_stream {
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DMA_STREAM0 = 0, /**< Stream 0 */
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DMA_STREAM1 = 1, /**< Stream 1 */
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DMA_STREAM2 = 2, /**< Stream 2 */
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DMA_STREAM3 = 3, /**< Stream 3 */
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DMA_STREAM4 = 4, /**< Stream 4 */
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DMA_STREAM5 = 5, /**< Stream 5 */
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DMA_STREAM6 = 6, /**< Stream 6 */
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DMA_STREAM7 = 7, /**< Stream 7 */
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} dma_stream;
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static inline void dma_setup_transfer(dma_dev *dev,
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dma_stream stream,
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__io void *peripheral_address,
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__io void *memory_address0,
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__io void *memory_address1,
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uint32 flags,
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uint32 fifo_flags) {
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dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
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dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
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dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
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dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
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dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
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dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
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}
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static inline void dma_set_num_transfers(dma_dev *dev,
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dma_stream stream,
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uint16 num_transfers) {
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dev->regs->STREAM[stream].NDTR = num_transfers;
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}
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void dma_attach_interrupt(dma_dev *dev,
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dma_stream stream,
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void (*handler)(void));
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void dma_detach_interrupt(dma_dev *dev, dma_stream stream);
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static inline void dma_enable(dma_dev *dev, dma_stream stream) {
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dev->regs->STREAM[stream].CR |= DMA_CR_EN;
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}
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static inline void dma_disable(dma_dev *dev, dma_stream stream) {
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dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
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}
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/**
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* @brief Check if a DMA stream is enabled
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* @param dev DMA device
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* @param stream Stream whose enabled bit to check.
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*/
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static inline uint8 dma_is_stream_enabled(dma_dev *dev, dma_stream stream) {
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return (uint8)(dev->regs->STREAM[stream].CR & DMA_CR_EN);
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}
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/**
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* @brief Get the ISR status bits for a DMA stream.
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*
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* The bits are returned right-aligned, in the following order:
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* transfer error flag, half-transfer flag, transfer complete flag,
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* global interrupt flag.
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*
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* @param dev DMA device
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* @param stream Stream whose ISR bits to return.
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*/
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uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream);
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/**
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* @brief Clear the ISR status bits for a given DMA stream.
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*
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* @param dev DMA device
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* @param stream Stream whose ISR bits to clear.
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*/
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void dma_clear_isr_bits(dma_dev *dev, dma_stream stream);
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif
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