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PIN_MAP moved to flash

This commit is contained in:
stevstrong 2017-05-07 15:09:15 +02:00
parent 483bbe17d3
commit 28fa836f4f
16 changed files with 286 additions and 374 deletions
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4
STM32F4/cores/maple/ext_interrupts.cpp
View File

@ -51,7 +51,7 @@ void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) {
exti_trigger_mode outMode = exti_out_mode(mode);
exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit),
exti_attach_interrupt((afio_exti_num)(pin&0x0F),
gpio_exti_port(PIN_MAP[pin].gpio_device),
handler,
outMode);
@ -66,7 +66,7 @@ void detachInterrupt(uint8 pin) {
return;
}
exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit));
exti_detach_interrupt((afio_exti_num)(pin&0x0F));
}
static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) {

21
STM32F4/cores/maple/libmaple/adc.c
View File

@ -41,27 +41,24 @@
#include "rcc.h"
#include "adc.h"
static adc_dev adc1 = {
/** ADC1 device. */
const adc_dev ADC1 = {
.regs = ADC1_BASE,
.clk_id = RCC_ADC1
};
/** ADC1 device. */
const adc_dev *ADC1 = &adc1;
static adc_dev adc2 = {
/** ADC2 device. */
const adc_dev ADC2 = {
.regs = ADC2_BASE,
.clk_id = RCC_ADC2
};
/** ADC2 device. */
const adc_dev *ADC2 = &adc2;
#ifdef STM32_HIGH_DENSITY
adc_dev adc3 = {
/** ADC3 device. */
const adc_dev ADC3 = {
.regs = ADC3_BASE,
.clk_id = RCC_ADC3
};
/** ADC3 device. */
const adc_dev *ADC3 = &adc3;
#endif
/**
@ -101,10 +98,10 @@ void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) {
* @param fn Function to call on each ADC device.
*/
void adc_foreach(void (*fn)(const adc_dev*)) {
fn(ADC1);
fn(ADC2);
fn(&ADC1);
fn(&ADC2);
#ifdef STM32_HIGH_DENSITY
fn(ADC3);
fn(&ADC3);
#endif
}

6
STM32F4/cores/maple/libmaple/adc.h
View File

@ -82,10 +82,10 @@ typedef struct adc_dev {
rcc_clk_id clk_id; /**< RCC clock information */
} adc_dev;
extern const adc_dev *ADC1;
extern const adc_dev *ADC2;
extern const adc_dev ADC1;
extern const adc_dev ADC2;
#ifdef STM32_HIGH_DENSITY
extern const adc_dev *ADC3;
extern const adc_dev ADC3;
#endif
/*

16
STM32F4/cores/maple/libmaple/gpio.h
View File

@ -46,7 +46,7 @@ extern "C"{
* @brief Get a GPIO port's corresponding afio_exti_port.
* @param dev GPIO device whose afio_exti_port to return.
*/
static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
static inline afio_exti_port gpio_exti_port(const gpio_dev *dev) {
return dev->exti_port;
}
@ -61,18 +61,18 @@ static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
*/
static inline void gpio_write_pin(uint8_t pin, uint8 val) {
if (val) {
(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(PIN_MAP[pin].gpio_bit);
(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
} else {
(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(PIN_MAP[pin].gpio_bit);
(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
}
}
static inline void gpio_set_pin(uint8_t pin) {
(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(PIN_MAP[pin].gpio_bit);
(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
}
static inline void gpio_clear_pin(uint8_t pin) {
(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(PIN_MAP[pin].gpio_bit);
(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
}
/**
@ -85,7 +85,7 @@ static inline void gpio_clear_pin(uint8_t pin) {
* @return True if the pin is set, false otherwise.
*/
static inline uint32 gpio_read_pin(uint8_t pin) {
return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(PIN_MAP[pin].gpio_bit);
return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(pin&0x0F);
}
/**
@ -94,14 +94,14 @@ static inline uint32 gpio_read_pin(uint8_t pin) {
* @param pin Pin on dev to toggle.
*/
static inline void gpio_toggle_pin(uint8_t pin) {
(PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(PIN_MAP[pin].gpio_bit);
(PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(pin&0x0F);
}
/*
* GPIO Convenience routines
*/
extern void gpio_init(gpio_dev *dev);
extern void gpio_init(const gpio_dev *dev);
extern void gpio_init_all(void);
extern void gpio_set_mode(uint8_t pin, gpio_pin_mode mode);
extern void gpio_set_af_mode(uint8_t pin, int mode);

57
STM32F4/cores/maple/libmaple/gpioF4.c
View File

@ -24,8 +24,6 @@
* SOFTWARE.
*****************************************************************************/
#ifdef STM32F4
/**
* @file gpio.c
* @brief GPIO initialization routine
@ -38,64 +36,57 @@
* GPIO devices
*/
gpio_dev gpioa = {
/** GPIO port A device. */
const gpio_dev GPIOA = {
.regs = GPIOA_BASE,
.clk_id = RCC_GPIOA,
.exti_port = AFIO_EXTI_PA,
};
/** GPIO port A device. */
gpio_dev* const GPIOA = &gpioa;
gpio_dev gpiob = {
/** GPIO port B device. */
const gpio_dev GPIOB = {
.regs = GPIOB_BASE,
.clk_id = RCC_GPIOB,
.exti_port = AFIO_EXTI_PB,
};
/** GPIO port B device. */
gpio_dev* const GPIOB = &gpiob;
gpio_dev gpioc = {
/** GPIO port C device. */
const gpio_dev GPIOC = {
.regs = GPIOC_BASE,
.clk_id = RCC_GPIOC,
.exti_port = AFIO_EXTI_PC,
};
/** GPIO port C device. */
gpio_dev* const GPIOC = &gpioc;
gpio_dev gpiod = {
/** GPIO port D device. */
const gpio_dev GPIOD = {
.regs = GPIOD_BASE,
.clk_id = RCC_GPIOD,
.exti_port = AFIO_EXTI_PD,
};
/** GPIO port D device. */
gpio_dev* const GPIOD = &gpiod;
#ifdef STM32_HIGH_DENSITY
gpio_dev gpioe = {
/** GPIO port E device. */
const gpio_dev GPIOE = {
.regs = GPIOE_BASE,
.clk_id = RCC_GPIOE,
.exti_port = AFIO_EXTI_PE,
};
/** GPIO port E device. */
gpio_dev* const GPIOE = &gpioe;
#if 0 // not available on LQFP 100 package
gpio_dev gpiof = {
/** GPIO port F device. */
const gpio_dev GPIOF = {
.regs = GPIOF_BASE,
.clk_id = RCC_GPIOF,
.exti_port = AFIO_EXTI_PF,
};
/** GPIO port F device. */
gpio_dev* const GPIOF = &gpiof;
gpio_dev gpiog = {
/** GPIO port G device. */
const gpio_dev GPIOG = {
.regs = GPIOG_BASE,
.clk_id = RCC_GPIOG,
.exti_port = AFIO_EXTI_PG,
};
/** GPIO port G device. */
gpio_dev* const GPIOG = &gpiog;
#endif // not available on LQFP 100 package
#endif
#endif
/*
@ -109,7 +100,7 @@ gpio_dev* const GPIOG = &gpiog;
*
* @param dev GPIO device to initialize.
*/
void gpio_init(gpio_dev *dev) {
void gpio_init(const gpio_dev *dev) {
rcc_clk_enable(dev->clk_id);
rcc_reset_dev(dev->clk_id);
}
@ -118,13 +109,13 @@ void gpio_init(gpio_dev *dev) {
* Initialize and reset all available GPIO devices.
*/
void gpio_init_all(void) {
gpio_init(GPIOA);
gpio_init(GPIOB);
gpio_init(GPIOC);
gpio_init(GPIOD);
gpio_init(&GPIOA);
gpio_init(&GPIOB);
gpio_init(&GPIOC);
gpio_init(&GPIOD);
#ifdef STM32_HIGH_DENSITY
gpio_init(GPIOE);
gpio_init(&GPIOE);
#if 0 // not available on LQFP 100 package
gpio_init(GPIOF);
gpio_init(GPIOG);
@ -154,7 +145,7 @@ void gpio_init_all(void) {
*/
void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
uint8_t pin = PIN_MAP[io_pin].gpio_bit;
uint8_t pin = io_pin&0x0f;
//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
//gpio_set_af_mode(dev, pin, mode>>8);
@ -175,7 +166,7 @@ void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
*/
void gpio_set_af_mode(uint8_t io_pin, int mode) {
gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
uint8_t pin = PIN_MAP[io_pin].gpio_bit;
uint8_t pin = io_pin&0x0F;
regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << ((pin&7)<<2))) | (((mode >> 0) & 15) << ((pin&7)<<2));
}
@ -226,5 +217,3 @@ void afio_remap(afio_remap_peripheral remapping) {
}
}
#endif
#endif

15
STM32F4/cores/maple/libmaple/gpio_def.h
View File

@ -89,17 +89,12 @@ typedef struct gpio_dev {
afio_exti_port exti_port; /**< AFIO external interrupt port value */
} gpio_dev;
extern gpio_dev gpioa;
extern gpio_dev* const GPIOA;
extern gpio_dev gpiob;
extern gpio_dev* const GPIOB;
extern gpio_dev gpioc;
extern gpio_dev* const GPIOC;
extern gpio_dev gpiod;
extern gpio_dev* const GPIOD;
extern const gpio_dev GPIOA;
extern const gpio_dev GPIOB;
extern const gpio_dev GPIOC;
extern const gpio_dev GPIOD;
#ifdef STM32_HIGH_DENSITY
extern gpio_dev gpioe;
extern gpio_dev* const GPIOE;
extern const gpio_dev GPIOE;
#if 0 // not available on LQFP 100 package
extern gpio_dev gpiof;
extern gpio_dev* const GPIOF;

1
STM32F4/cores/maple/libmaple/spi.h
View File

@ -213,7 +213,6 @@ typedef struct spi_dev {
void spi_init(spi_dev *dev);
struct gpio_dev;
/**
* @brief Configure GPIO bit modes for use as a SPI port's pins.
*

16
STM32F4/cores/maple/libmaple/timer.c
View File

@ -44,7 +44,7 @@
/* Update only. */
#define NR_BAS_HANDLERS 1
static timer_dev timer1 = {
timer_dev timer1 = {
.regs = { .adv = TIMER1_BASE },
.clk_id = RCC_TIMER1,
.type = TIMER_ADVANCED,
@ -53,7 +53,7 @@ static timer_dev timer1 = {
/** Timer 1 device (advanced) */
timer_dev *TIMER1 = &timer1;
static timer_dev timer2 = {
timer_dev timer2 = {
.regs = { .gen = TIMER2_BASE },
.clk_id = RCC_TIMER2,
.type = TIMER_GENERAL,
@ -62,7 +62,7 @@ static timer_dev timer2 = {
/** Timer 2 device (general-purpose) */
timer_dev *TIMER2 = &timer2;
static timer_dev timer3 = {
timer_dev timer3 = {
.regs = { .gen = TIMER3_BASE },
.clk_id = RCC_TIMER3,
.type = TIMER_GENERAL,
@ -71,7 +71,7 @@ static timer_dev timer3 = {
/** Timer 3 device (general-purpose) */
timer_dev *TIMER3 = &timer3;
static timer_dev timer4 = {
timer_dev timer4 = {
.regs = { .gen = TIMER4_BASE },
.clk_id = RCC_TIMER4,
.type = TIMER_GENERAL,
@ -81,7 +81,7 @@ static timer_dev timer4 = {
timer_dev *TIMER4 = &timer4;
#ifdef STM32_HIGH_DENSITY
static timer_dev timer5 = {
timer_dev timer5 = {
.regs = { .gen = TIMER5_BASE },
.clk_id = RCC_TIMER5,
.type = TIMER_GENERAL,
@ -90,7 +90,7 @@ static timer_dev timer5 = {
/** Timer 5 device (general-purpose) */
timer_dev *TIMER5 = &timer5;
static timer_dev timer6 = {
timer_dev timer6 = {
.regs = { .bas = TIMER6_BASE },
.clk_id = RCC_TIMER6,
.type = TIMER_BASIC,
@ -99,7 +99,7 @@ static timer_dev timer6 = {
/** Timer 6 device (basic) */
timer_dev *TIMER6 = &timer6;
static timer_dev timer7 = {
timer_dev timer7 = {
.regs = { .bas = TIMER7_BASE },
.clk_id = RCC_TIMER7,
.type = TIMER_BASIC,
@ -108,7 +108,7 @@ static timer_dev timer7 = {
/** Timer 7 device (basic) */
timer_dev *TIMER7 = &timer7;
static timer_dev timer8 = {
timer_dev timer8 = {
.regs = { .adv = TIMER8_BASE },
.clk_id = RCC_TIMER8,
.type = TIMER_ADVANCED,

2
STM32F4/cores/maple/usb_serial.cpp
View File

@ -134,7 +134,7 @@ uint8 USBSerial::pending(void) {
return usbGetPending();
}
uint8 USBSerial::isConnected(void) {
USBSerial::operator bool() {
return usbIsConnected() && usbIsConfigured();
}

12
STM32F4/cores/maple/usb_serial.h
View File

@ -59,7 +59,8 @@ public:
uint8 getRTS();
uint8 getDTR();
uint8 isConnected();
operator bool();
uint8 isConnected() { return (bool) *this; }
uint8 pending();
void enableBlockingTx(void);
@ -67,9 +68,14 @@ public:
};
extern USBSerial SerialUSB;
#define Serial SerialUSB
#endif
#else // _USB_SERIAL_H_
#define Serial Serial1
#endif // SERIAL_USB
#endif
#endif // _USB_SERIAL_H_

1
STM32F4/cores/maple/wirish.h
View File

@ -58,7 +58,6 @@
#define false 0x0
#endif
#define lowByte(w) ((w) & 0xFF)
#define highByte(w) (((w) >> 8) & 0xFF)
#define bitRead(value, bit) (((value) >> (bit)) & 0x01)

8
STM32F4/cores/maple/wirish_types.h
View File

@ -50,13 +50,11 @@
#ifdef BOARD_generic_f407v
// restructure members to build consecutive pairs
typedef struct stm32_pin_info {
gpio_dev *gpio_device; /**< Maple pin's GPIO device */
uint8 gpio_bit; /**< Pin's GPIO port bit. */
timer_dev *timer_device; /**< Pin's timer device, if any. */
const gpio_dev * gpio_device; /**< Maple pin's GPIO device */
timer_dev * timer_device; /**< Pin's timer device, if any. */
uint8 timer_channel; /**< Timer channel, or 0 if none. */
const adc_dev *adc_device; /**< ADC device, if any. */
uint8 adc_channel; /**< Pin ADC channel, or ADCx if none. */
uint8 filler;
const adc_dev *adc_device; /**< ADC device, if any. */
} stm32_pin_info;
#else

1
STM32F4/libraries/SPI/src/SPI.h
View File

@ -397,5 +397,4 @@ private:
};
extern SPIClass SPI;//(1);// dummy params
#endif

130
STM32F4/variants/generic_f407v/black_f4.h.old
View File

@ -1,130 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2011 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file black_f4.h
* @author Marti Bolivar <mbolivar@leaflabs.com>
* @brief Private include file for Maple Native in boards.h
*
* See maple.h for more information on these definitions.
*/
#ifndef _BOARD_BLACK_F4_H_
#define _BOARD_BLACK_F4_H_
#define Port2Pin(port, bit) ((port-'A')*16+bit)
#define CYCLES_PER_MICROSECOND 168
#undef STM32_PCLK1
#undef STM32_PCLK2
#define STM32_PCLK1 (CYCLES_PER_MICROSECOND*1000000/4)
#define STM32_PCLK2 (CYCLES_PER_MICROSECOND*1000000/2)
#define SYSTICK_RELOAD_VAL (CYCLES_PER_MICROSECOND*1000-1)
#define BOARD_USB_DM_PIN PA11
#define BOARD_USB_DP_PIN PA12
#define BOARD_LED_PIN PA6 //Port2Pin('A', 6)
#define BOARD_LED2_PIN PA7 //Port2Pin('A', 7)
#define BOARD_BUTTON1_PIN PA0 //Port2Pin('A', 0)
#define BOARD_BUTTON2_PIN PE4 //Port2Pin('E', 4)
#define BOARD_BUTTON3_PIN PE3 //Port2Pin('E', 3)
#define BOARD_NR_USARTS 5
#define BOARD_USART1_TX_PIN PA9 //Port2Pin('A', 9)
#define BOARD_USART1_RX_PIN PA10 //Port2Pin('A',10)
#define BOARD_USART2_TX_PIN PA2 //Port2Pin('A', 2)
#define BOARD_USART2_RX_PIN PA3 //Port2Pin('A', 3)
#define BOARD_USART3_TX_PIN PB10 //Port2Pin('B',10)
#define BOARD_USART3_RX_PIN PB11 //Port2Pin('B',11)
#define BOARD_UART4_TX_PIN PA0 //Port2Pin('A', 0)
#define BOARD_UART4_RX_PIN PA1 //Port2Pin('A', 1)
#define BOARD_UART5_TX_PIN PC12 //Port2Pin('C',12)
#define BOARD_UART5_RX_PIN PD2 //Port2Pin('D', 2)
#define BOARD_NR_SPI 3
#define BOARD_SPI1_NSS_PIN PA4 //Port2Pin('A', 4)
#define BOARD_SPI1_SCK_PIN PA5 //Port2Pin('A', 5)
#define BOARD_SPI1_MISO_PIN PA6 //Port2Pin('A', 6)
#define BOARD_SPI1_MOSI_PIN PA7 //Port2Pin('A', 7)
#define BOARD_SPI1A_NSS_PIN PA15 //Port2Pin('A',15)
#define BOARD_SPI1A_SCK_PIN PB3 //Port2Pin('B', 3)
#define BOARD_SPI1A_MISO_PIN PB4 //Port2Pin('B', 4)
#define BOARD_SPI1A_MOSI_PIN PB5 //Port2Pin('B', 5)
#define BOARD_SPI2_NSS_PIN PB12 //Port2Pin('B',12)
#define BOARD_SPI2_SCK_PIN PB13 //Port2Pin('B',13)
#define BOARD_SPI2_MISO_PIN PB14 //Port2Pin('B',14)
#define BOARD_SPI2_MOSI_PIN PB15 //Port2Pin('B',15)
#define BOARD_SPI2A_NSS_PIN PB9 //Port2Pin('B', 9)
#define BOARD_SPI2A_SCK_PIN PB10 //Port2Pin('B',10)
#define BOARD_SPI2A_MISO_PIN PC2 //Port2Pin('C', 2)
#define BOARD_SPI2A_MOSI_PIN pc3 //Port2Pin('C', 3)
#define BOARD_SPI3_NSS_PIN PA15 //Port2Pin('A',15)
#define BOARD_SPI3_SCK_PIN PB3 //Port2Pin('B', 3)
#define BOARD_SPI3_MISO_PIN PB4 //Port2Pin('B', 4)
#define BOARD_SPI3_MOSI_PIN PB5 //Port2Pin('B', 5)
/* overlap with the SDIO interface for SD card
#define BOARD_SPI3A_NSS_PIN Port2Pin('A', 4)
#define BOARD_SPI3A_SCK_PIN Port2Pin('C',10)
#define BOARD_SPI3A_MISO_PIN Port2Pin('C',11)
#define BOARD_SPI3A_MOSI_PIN Port2Pin('C',12)
*/
#define BOARD_SDIO_D0 PC8 //Port2Pin('C', 8)
#define BOARD_SDIO_D1 PC9 //Port2Pin('C', 9)
#define BOARD_SDIO_D2 PC10 //Port2Pin('C',10)
#define BOARD_SDIO_D3 PC11 //Port2Pin('C',11)
#define BOARD_SDIO_CK PC12 //Port2Pin('C',12)
#define BOARD_SDIO_CMD PD2 //Port2Pin('D', 2)
#define BOARD_NR_GPIO_PINS 80
#define BOARD_NR_PWM_PINS 22
#define BOARD_NR_ADC_PINS 16
#define BOARD_NR_USED_PINS 22
#define BOARD_JTMS_SWDIO_PIN PA13 //Port2Pin('A',13)
#define BOARD_JTCK_SWCLK_PIN PA14 //Port2Pin('A',14)
#define BOARD_JTDI_PIN PA15 //Port2Pin('A',15)
#define BOARD_JTDO_PIN PB3 //Port2Pin('B', 3)
#define BOARD_NJTRST_PIN PB4 //Port2Pin('B', 4)
enum {
PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
#if 0 // not available on LQFP100 package
PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
#endif
};
#endif

156
STM32F4/variants/generic_f407v/generic_f407v.cpp
View File

@ -34,12 +34,7 @@
#include "generic_f407v.h"
//#include "fsmc.h"
#include <libmaple/gpio.h>
#include <libmaple/rcc.h>
#include <libmaple/timer.h>
#include <wirish_types.h>
#include "wirish_types.h"
//static void initSRAMChip(void);
/*****************************************************************************/
@ -70,155 +65,6 @@ void boardInit(void) {
return;
}
/*
typedef struct stm32_pin_info {
gpio_dev *gpio_device; // Maple pin's GPIO device
uint8 gpio_bit; // Pin's GPIO port bit.
timer_dev *timer_device; // Pin's timer device, if any.
uint8 timer_channel; // Timer channel, or 0 if none.
const adc_dev *adc_device; // ADC device, if any.
uint8 adc_channel; // Pin ADC channel, or ADCx if none.
} stm32_pin_info;
*/
extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { // LQFP100 package pin
{GPIOA, 0, TIMER5, 1, ADC1, 0}, // D00/PA0 | 23 | USART2_CTS | UART4_TX | ETH_MII_CRS | TIM2_CH1_ETR | TIM5_CH1 | TIM8_ETR | ADC123_IN0/WKUP
{GPIOA, 1, TIMER5, 2, ADC1, 1}, // D01/PA1 | 24 | USART2_RTS | UART4_RX | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2 | TIM2_CH2 | ADC123_IN1
{GPIOA, 2, TIMER5, 3, ADC1, 2}, // D02/PA2 | 25 | USART2_TX | TIM5_CH3 | TIM9_CH1 | TIM2_CH3 | ETH_MDIO | ADC123_IN2
{GPIOA, 3, TIMER5, 4, ADC1, 3}, // D03/PA3 | 26 | USART2_RX | TIM5_CH4 | TIM9_CH2 | TIM2_CH4 | OTG_HS_ULPI_D0 | ETH_MII_COL | ADC123_IN3
{GPIOA, 4, NULL, 0, ADC1, 4}, // D04/PA4 | 29 | SPI1_NSS | SPI3_NSS | USART2_CK | DCMI_HSYNC | OTG_HS_SOF | I2S3_WS | ADC12_IN4 / DAC_OUT1
{GPIOA, 5, NULL, 0, ADC1, 5}, // D05/PA5 | 30 | SPI1_SCK | OTG_HS_ULPI_CK | TIM2_CH1_ETR | TIM8_CH1N | ADC12_IN5 / DAC_OUT2
{GPIOA, 6, NULL, 1, ADC1, 6}, // D06/PA6 | 31 | SPI1_MISO | TIM8_BKIN | TIM13_CH1 | DCMI_PIXCLK | TIM3_CH1 | TIM1_BKIN | ADC12_IN6
{GPIOA, 7, NULL, 0, ADC1, 7}, // D07/PA7 | 32 | SPI1_MOSI | TIM8_CH1N | TIM14_CH1 | TIM3_CH2 | ETH_MII_RX_DV | TIM1_CH1N / ETH_RMII_CRS_DV | ADC12_IN7
{GPIOA, 8, NULL, 0, NULL, ADCx}, // D08/PA8 | 67 | MCO1 | USART1_CK | TIM1_CH1 | I2C3_SCL | OTG_FS_SOF
{GPIOA, 9, NULL, 0, NULL, ADCx}, // D09/PA9 | 68 | USART1_TX | TIM1_CH2 | I2C3_SMBA | DCMI_D0
{GPIOA, 10, NULL, 0, NULL, ADCx}, // D10/PA10 | 69 | USART1_RX | TIM1_CH3 | OTG_FS_ID | DCMI_D1
{GPIOA, 11, NULL, 0, NULL, ADCx}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX | TIM1_CH4 | OTG_FS_DM
{GPIOA, 12, NULL, 0, NULL, ADCx}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX | TIM1_ETR | OTG_FS_DP
{GPIOA, 13, NULL, 0, NULL, ADCx}, // D13/PA13 | 72 | JTMS-SWDIO
{GPIOA, 14, NULL, 0, NULL, ADCx}, // D14/PA14 | 76 | JTCK-SWCLK
{GPIOA, 15, TIMER2, 1, NULL, ADCx}, // D15/PA15 | 77 | JTDI | SPI3_NSS | I2S3_WS | TIM2_CH1_ETR | SPI1_NSS
{GPIOB, 0, TIMER3, 3, ADC1, 8}, // D16/PB0 | 35 | TIM3_CH3 | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2 | TIM1_CH2N | ADC12_IN8
{GPIOB, 1, TIMER3, 4, ADC1, 9}, // D17/PB1 | 36 | TIM3_CH4 | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3 | TIM1_CH3N | ADC12_IN9
{GPIOB, 2, NULL, 0, NULL, ADCx}, // D18/PB2 | 37 | BOOT1
{GPIOB, 3, TIMER2, 2, NULL, ADCx}, // D19/PB3 | 89 | JTDO | TRACESWO | SPI3_SCK | I2S3_CK | TIM2_CH2 | SPI1_SCK
{GPIOB, 4, TIMER3, 1, NULL, ADCx}, // D20/PB4 | 90 | NJTRST | SPI3_MISO | TIM3_CH1 | SPI1_MISO | I2S3ext_SD
{GPIOB, 5, TIMER3, 2, NULL, ADCx}, // D21/PB5 | 91 | I2C1_SMBA | CAN2_RX | OTG_HS_ULPI_D7 | ETH_PPS_OUT | TIM3_CH2 | SPI1_MOSI | SPI3_MOSI | DCMI_D10 | I2S3_SD
{GPIOB, 6, NULL, 0, NULL, ADCx}, // D22/PB6 | 92 | I2C1_SCL | TIM4_CH1 | CAN2_TX | DCMI_D5 | USART1_TX
{GPIOB, 7, NULL, 0, NULL, ADCx}, // D23/PB7 | 93 | I2C1_SDA | FSMC_NL | DCMI_VSYNC | USART1_RX | TIM4_CH2
{GPIOB, 8, NULL, 0, NULL, ADCx}, // D24/PB8 | 95 | TIM4_CH3 | SDIO_D4 | TIM10_CH1 | DCMI_D6 | ETH_MII_TXD3 | I2C1_SCL | CAN1_RX
{GPIOB, 9, NULL, 0, NULL, ADCx}, // D25/PB9 | 96 | SPI2_NSS | I2S2_WS | TIM4_CH4 | TIM11_CH1 | SDIO_D5 | DCMI_D7 | I2C1_SDA | CAN1_TX
{GPIOB, 10, NULL, 0, NULL, ADCx}, // D26/PB10 | 47 | SPI2_SCK | I2S2_CK | I2C2_SCL | USART3_TX | OTG_HS_ULPI_D3 | ETH_MII_RX_ER | TIM2_CH3
{GPIOB, 11, NULL, 0, NULL, ADCx}, // D27/PB11 | 48 | I2C2_SDA | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN | TIM2_CH4
{GPIOB, 12, NULL, 0, NULL, ADCx}, // D28/PB12 | 51 | SPI2_NSS | I2S2_WS | I2C2_SMBA | USART3_CK | TIM1_BKIN | CAN2_RX | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
{GPIOB, 13, NULL, 0, NULL, ADCx}, // D29/PB13 | 52 | SPI2_SCK | I2S2_CK | USART3_CTS | TIM1_CH1N | CAN2_TX | OTG_HS_ULPI_D6 | ETH_RMII_TXD1 | ETH_MII_TXD1
{GPIOB, 14, NULL, 0, NULL, ADCx}, // D30/PB14 | 53 | SPI2_MISO | TIM1_CH2N | TIM12_CH1 | OTG_HS_DM | USART3_RTS | TIM8_CH2N | I2S2ext_SD
{GPIOB, 15, NULL, 0, NULL, ADCx}, // D31/PB15 | 54 | SPI2_MOSI | I2S2_SD | TIM1_CH3N | TIM8_CH3N | TIM12_CH2 | OTG_HS_DP
{GPIOC, 0, NULL, 0, ADC1, 10}, // D32/PC0 | 15 | OTG_HS_ULPI_STP | ADC123_IN10
{GPIOC, 1, NULL, 0, ADC1, 11}, // D33/PC1 | 16 | ETH_MDC | ADC123_IN11
{GPIOC, 2, NULL, 0, ADC1, 12}, // D34/PC2 | 17 | SPI2_MISO | OTG_HS_ULPI_DIR | ETH_MII_TXD2 | I2S2ext_SD | ADC123_IN12
{GPIOC, 3, NULL, 0, ADC1, 13}, // D35/PC3 | 18 | SPI2_MOSI | I2S2_SD | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
{GPIOC, 4, NULL, 0, ADC1, 14}, // D36/PC4 | 33 | ETH_RMII_RX_D0 | ETH_MII_RX_D0 | ADC12_IN14
{GPIOC, 5, NULL, 0, ADC1, 15}, // D37/PC5 | 34 | ETH_RMII_RX_D1 | ETH_MII_RX_D1 | ADC12_IN15
{GPIOC, 6, TIMER8, 1, NULL, ADCx}, // D38/PC6 | 63 | I2S2_MCK | TIM8_CH1/SDIO_D6 | USART6_TX | DCMI_D0/TIM3_CH1
{GPIOC, 7, TIMER8, 2, NULL, ADCx}, // D39/PC7 | 64 | I2S3_MCK | TIM8_CH2/SDIO_D7 | USART6_RX | DCMI_D1/TIM3_CH2
{GPIOC, 8, TIMER8, 3, NULL, ADCx}, // D40/PC8 | 65 | TIM8_CH3 | SDIO_D0 | TIM3_CH3 | USART6_CK | DCMI_D2
{GPIOC, 9, TIMER8, 4, NULL, ADCx}, // D41/PC9 | 66 | I2S_CKIN | MCO2 | TIM8_CH4 | SDIO_D1 | I2C3_SDA | DCMI_D3 | TIM3_CH4
{GPIOC, 10, NULL, 0, NULL, ADCx}, // D42/PC10 | 78 | SPI3_SCK | I2S3_CK | UART4_TX | SDIO_D2 | DCMI_D8 | USART3_TX
{GPIOC, 11, NULL, 0, NULL, ADCx}, // D43/PC11 | 79 | UART4_RX | SPI3_MISO | SDIO_D3 | DCMI_D4 | USART3_RX | I2S3ext_SD
{GPIOC, 12, NULL, 0, NULL, ADCx}, // D44/PC12 | 80 | UART5_TX | SDIO_CK | DCMI_D9 | SPI3_MOSI | I2S3_SD | USART3_CK
{GPIOC, 13, NULL, 0, NULL, ADCx}, // D45/PC13 | 7 | RTC_OUT, RTC_TAMP1, RTC_TS
{GPIOC, 14, NULL, 0, NULL, ADCx}, // D46/PC14 | 8 | OSC32_IN
{GPIOC, 15, NULL, 0, NULL, ADCx}, // D47/PC15 | 9 | OSC32_OUT
{GPIOD, 0, NULL, 0, NULL, ADCx}, // D48/PD0 | 81 | FSMC_D2 | CAN1_RX
{GPIOD, 1, NULL, 0, NULL, ADCx}, // D49/PD1 | 82 | FSMC_D3 | CAN1_TX
{GPIOD, 2, NULL, 0, NULL, ADCx}, // D50/PD2 | 83 | TIM3_ETR | UART5_RX | SDIO_CMD | DCMI_D11
{GPIOD, 3, NULL, 0, NULL, ADCx}, // D51/PD3 | 84 | FSMC_CLK | USART2_CTS
{GPIOD, 4, NULL, 0, NULL, ADCx}, // D52/PD4 | 85 | FSMC_NOE | USART2_RTS
{GPIOD, 5, NULL, 0, NULL, ADCx}, // D53/PD5 | 86 | FSMC_NWE | USART2_TX
{GPIOD, 6, NULL, 0, NULL, ADCx}, // D54/PD6 | 87 | FSMC_NWAIT | USART2_RX
{GPIOD, 7, NULL, 0, NULL, ADCx}, // D55/PD7 | 88 | USART2_CK | FSMC_NE1 | FSMC_NCE2
{GPIOD, 8, NULL, 0, NULL, ADCx}, // D56/PD8 | 55 | FSMC_D13 | USART3_TX
{GPIOD, 9, NULL, 0, NULL, ADCx}, // D57/PD9 | 56 | FSMC_D14 | USART3_RX
{GPIOD, 10, NULL, 0, NULL, ADCx}, // D58/PD10 | 57 | FSMC_D15 | USART3_CK
{GPIOD, 11, NULL, 0, NULL, ADCx}, // D59/PD11 | 58 | FSMC_CLE | FSMC_A16 | USART3_CTS
{GPIOD, 12, TIMER4, 1, NULL, ADCx}, // D60/PD12 | 59 | FSMC_ALE | FSMC_A17 | TIM4_CH1 | USART3_RTS // remap in
{GPIOD, 13, TIMER4, 2, NULL, ADCx}, // D61/PD13 | 60 | FSMC_A18 | TIM4_CH2 // remap in
{GPIOD, 14, TIMER4, 3, NULL, ADCx}, // D62/PD14 | 61 | FSMC_D0 | TIM4_CH3 // remap in
{GPIOD, 15, TIMER4, 4, NULL, ADCx}, // D63/PD15 | 62 | FSMC_D1 | TIM4_CH4 // remap in
{GPIOE, 0, NULL, 0, NULL, ADCx}, // D64/PE0 | 97 | TIM4_ETR | FSMC_NBL0 | DCMI_D2
{GPIOE, 1, NULL, 0, NULL, ADCx}, // D65/PE1 | 98 | FSMC_NBL1 | DCMI_D3
{GPIOE, 2, NULL, 0, NULL, ADCx}, // D66/PE2 | 1 | TRACECLK | FSMC_A23 | ETH_MII_TXD3
{GPIOE, 3, NULL, 0, NULL, ADCx}, // D67/PE3 | 2 | TRACED0 | FSMC_A19
{GPIOE, 4, NULL, 0, NULL, ADCx}, // D68/PE4 | 3 | TRACED1 | FSMC_A20 | DCMI_D4
{GPIOE, 5, NULL, 0, NULL, ADCx}, // D69/PE5 | 4 | TRACED2 | FSMC_A21 | TIM9_CH1 / DCMI_D6
{GPIOE, 6, NULL, 0, NULL, ADCx}, // D70/PE6 | 5 | TRACED3 | FSMC_A22 | TIM9_CH2 / DCMI_D7
{GPIOE, 7, NULL, 0, NULL, ADCx}, // D71/PE7 | 38 | FSMC_D4 | TIM1_ETR
{GPIOE, 8, NULL, 0, NULL, ADCx}, // D72/PE8 | 39 | FSMC_D5 | TIM1_CH1N
{GPIOE, 9, TIMER1, 1, NULL, ADCx}, // D73/PE9 | 40 | FSMC_D6 | TIM1_CH1 // remap in
{GPIOE, 10, NULL, 0, NULL, ADCx}, // D74/PE10 | 41 | FSMC_D7 | TIM1_CH2N
{GPIOE, 11, TIMER1, 2, NULL, ADCx}, // D75/PE11 | 42 | FSMC_D8 | TIM1_CH2 // remap in
{GPIOE, 12, NULL, 0, NULL, ADCx}, // D76/PE12 | 43 | FSMC_D9 | TIM1_CH3N
{GPIOE, 13, TIMER1, 3, NULL, ADCx}, // D77/PE13 | 44 | FSMC_D10 | TIM1_CH3 // remap in
{GPIOE, 14, TIMER1, 4, NULL, ADCx}, // D78/PE14 | 45 | FSMC_D11 | TIM1_CH4 // remap in
{GPIOE, 15, NULL, 0, NULL, ADCx}, // D79/PE15 | 46 | FSMC_D12 | TIM1_BKIN
#if 0
{GPIOF, 0, NULL, 0, NULL, ADCx}, // D80/PF0
{GPIOF, 1, NULL, 0, NULL, ADCx}, // D81/PF1
{GPIOF, 2, NULL, 0, NULL, ADCx}, // D82/PF2
{GPIOF, 3, NULL, 0, NULL, ADCx}, // D83/PF3
{GPIOF, 4, NULL, 0, NULL, ADCx}, // D84/PF4
{GPIOF, 5, NULL, 0, NULL, ADCx}, // D85/PF5
{GPIOF, 6, NULL, 0, NULL, ADCx}, // D86/PF6
{GPIOF, 7, NULL, 0, NULL, ADCx}, // D87/PF7
{GPIOF, 8, NULL, 0, NULL, ADCx}, // D88/PF8
{GPIOF, 9, NULL, 0, NULL, ADCx}, // D89/PF9
{GPIOF, 10, NULL, 0, NULL, ADCx}, // D90/PF10
{GPIOF, 11, NULL, 0, NULL, ADCx}, // D91/PF11
{GPIOF, 12, NULL, 0, NULL, ADCx}, // D92/PF12
{GPIOF, 13, NULL, 0, NULL, ADCx}, // D93/PF13
{GPIOF, 14, NULL, 0, NULL, ADCx}, // D94/PF14
{GPIOF, 15, NULL, 0, NULL, ADCx}, // D95/PF15
{GPIOG, 0, NULL, 0, NULL, ADCx}, // D96/PG0
{GPIOG, 1, NULL, 0, NULL, ADCx}, // D97/PG1
{GPIOG, 2, NULL, 0, NULL, ADCx}, // D98/PG2
{GPIOG, 3, NULL, 0, NULL, ADCx}, // D99/PG3
{GPIOG, 4, NULL, 0, NULL, ADCx}, // D100/PG4
{GPIOG, 5, NULL, 0, NULL, ADCx}, // D101/PG5
{GPIOG, 6, NULL, 0, NULL, ADCx}, // D102/PG6
{GPIOG, 7, NULL, 0, NULL, ADCx}, // D103/PG7
{GPIOG, 8, NULL, 0, NULL, ADCx}, // D104/PG8
{GPIOG, 9, NULL, 0, NULL, ADCx}, // D105/PG9
{GPIOG, 10, NULL, 0, NULL, ADCx}, // D106/PG10
{GPIOG, 11, NULL, 0, NULL, ADCx}, // D107/PG11
{GPIOG, 12, NULL, 0, NULL, ADCx}, // D108/PG12
{GPIOG, 13, NULL, 0, NULL, ADCx}, // D109/PG13
{GPIOG, 14, NULL, 0, NULL, ADCx}, // D110/PG14
{GPIOG, 15, NULL, 0, NULL, ADCx} // D111/PG15
#endif
};
/* to be defined
extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
};
*/
extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = {
PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
};
extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
USB_DM_PIN, USB_DP_PIN
};
/*
static void initSRAMChip(void) {
fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;

214
STM32F4/variants/generic_f407v/pin_map.c Normal file
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/******************************************************************************
* The MIT License
*
* Copyright (c) 2011 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file generic_f407v.cpp
* @author ala42
* @brief generic_f407v board file.
*/
#ifdef BOARD_generic_f407v
#ifdef __cplusplus
extern "C"{
#endif
//#include "generic_f407v.h"
//#include "fsmc.h"
#include <libmaple\gpio.h>
#include <libmaple\rcc.h>
#include <libmaple\timer.h>
#include <wirish_types.h>
extern timer_dev timer1;
extern timer_dev timer2;
extern timer_dev timer3;
extern timer_dev timer4;
extern timer_dev timer5;
extern timer_dev timer6;
extern timer_dev timer7;
extern timer_dev timer8;
/*
typedef struct stm32_pin_info {
gpio_dev *gpio_device; // Maple pin's GPIO device
uint8 gpio_bit; // Pin's GPIO port bit.
timer_dev *timer_device; // Pin's timer device, if any.
uint8 timer_channel; // Timer channel, or 0 if none.
const adc_dev *adc_device; // ADC device, if any.
uint8 adc_channel; // Pin ADC channel, or ADCx if none.
} stm32_pin_info;
*/
const stm32_pin_info PIN_MAP1[] = { // LQFP100 package pin
{&GPIOA, &timer5, 1, 0, &ADC1}, // D00/PA0 | 23 | USART2_CTS | UART4_TX | ETH_MII_CRS | TIM2_CH1_ETR | TIM5_CH1 | TIM8_ETR | ADC123_IN0/WKUP
};
const stm32_pin_info PIN_MAP[] = { // LQFP100 package pin
{&GPIOA, &timer5, 1, 0, &ADC1}, // D00/PA0 | 23 | USART2_CTS | UART4_TX | ETH_MII_CRS | TIM2_CH1_ETR | TIM5_CH1 | TIM8_ETR | ADC123_IN0/WKUP
{&GPIOA, &timer5, 2, 1, &ADC1}, // D01/PA1 | 24 | USART2_RTS | UART4_RX | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2 | TIM2_CH2 | ADC123_IN1
{&GPIOA, &timer5, 3, 2, &ADC1}, // D02/PA2 | 25 | USART2_TX | TIM5_CH3 | TIM9_CH1 | TIM2_CH3 | ETH_MDIO | ADC123_IN2
{&GPIOA, &timer5, 4, 3, &ADC1}, // D03/PA3 | 26 | USART2_RX | TIM5_CH4 | TIM9_CH2 | TIM2_CH4 | OTG_HS_ULPI_D0 | ETH_MII_COL | ADC123_IN3
{&GPIOA, NULL, 0, 4, &ADC1}, // D04/PA4 | 29 | SPI1_NSS | SPI3_NSS | USART2_CK | DCMI_HSYNC | OTG_HS_SOF | I2S3_WS | ADC12_IN4 / DAC_OUT1
{&GPIOA, NULL, 0, 5, &ADC1}, // D05/PA5 | 30 | SPI1_SCK | OTG_HS_ULPI_CK | TIM2_CH1_ETR | TIM8_CH1N | ADC12_IN5 / DAC_OUT2
{&GPIOA, NULL, 1, 6, &ADC1}, // D06/PA6 | 31 | SPI1_MISO | TIM8_BKIN | TIM13_CH1 | DCMI_PIXCLK | TIM3_CH1 | TIM1_BKIN | ADC12_IN6
{&GPIOA, NULL, 0, 7, &ADC1}, // D07/PA7 | 32 | SPI1_MOSI | TIM8_CH1N | TIM14_CH1 | TIM3_CH2 | ETH_MII_RX_DV | TIM1_CH1N / ETH_RMII_CRS_DV | ADC12_IN7
{&GPIOA, NULL, 0, ADCx, NULL}, // D08/PA8 | 67 | MCO1 | USART1_CK | TIM1_CH1 | I2C3_SCL | OTG_FS_SOF
{&GPIOA, NULL, 0, ADCx, NULL}, // D09/PA9 | 68 | USART1_TX | TIM1_CH2 | I2C3_SMBA | DCMI_D0
{&GPIOA, NULL, 0, ADCx, NULL}, // D10/PA10 | 69 | USART1_RX | TIM1_CH3 | OTG_FS_ID | DCMI_D1
{&GPIOA, NULL, 0, ADCx, NULL}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX | TIM1_CH4 | OTG_FS_DM
{&GPIOA, NULL, 0, ADCx, NULL}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX | TIM1_ETR | OTG_FS_DP
{&GPIOA, NULL, 0, ADCx, NULL}, // D13/PA13 | 72 | JTMS-SWDIO
{&GPIOA, NULL, 0, ADCx, NULL}, // D14/PA14 | 76 | JTCK-SWCLK
{&GPIOA, &timer2, 1, ADCx, NULL}, // D15/PA15 | 77 | JTDI | SPI3_NSS | I2S3_WS | TIM2_CH1_ETR | SPI1_NSS
{&GPIOB, &timer3, 3, 8, &ADC1}, // D16/PB0 | 35 | TIM3_CH3 | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2 | TIM1_CH2N | ADC12_IN8
{&GPIOB, &timer3, 4, 9, &ADC1}, // D17/PB1 | 36 | TIM3_CH4 | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3 | TIM1_CH3N | ADC12_IN9
{&GPIOB, NULL, 0, ADCx, NULL}, // D18/PB2 | 37 | BOOT1
{&GPIOB, &timer2, 2, ADCx, NULL}, // D19/PB3 | 89 | JTDO | TRACESWO | SPI3_SCK | I2S3_CK | TIM2_CH2 | SPI1_SCK
{&GPIOB, &timer3, 1, ADCx, NULL}, // D20/PB4 | 90 | NJTRST | SPI3_MISO | TIM3_CH1 | SPI1_MISO | I2S3ext_SD
{&GPIOB, &timer3, 2, ADCx, NULL}, // D21/PB5 | 91 | I2C1_SMBA | CAN2_RX | OTG_HS_ULPI_D7 | ETH_PPS_OUT | TIM3_CH2 | SPI1_MOSI | SPI3_MOSI | DCMI_D10 | I2S3_SD
{&GPIOB, NULL, 0, ADCx, NULL}, // D22/PB6 | 92 | I2C1_SCL | TIM4_CH1 | CAN2_TX | DCMI_D5 | USART1_TX
{&GPIOB, NULL, 0, ADCx, NULL}, // D23/PB7 | 93 | I2C1_SDA | FSMC_NL | DCMI_VSYNC | USART1_RX | TIM4_CH2
{&GPIOB, NULL, 0, ADCx, NULL}, // D24/PB8 | 95 | TIM4_CH3 | SDIO_D4 | TIM10_CH1 | DCMI_D6 | ETH_MII_TXD3 | I2C1_SCL | CAN1_RX
{&GPIOB, NULL, 0, ADCx, NULL}, // D25/PB9 | 96 | SPI2_NSS | I2S2_WS | TIM4_CH4 | TIM11_CH1 | SDIO_D5 | DCMI_D7 | I2C1_SDA | CAN1_TX
{&GPIOB, NULL, 0, ADCx, NULL}, // D26/PB10 | 47 | SPI2_SCK | I2S2_CK | I2C2_SCL | USART3_TX | OTG_HS_ULPI_D3 | ETH_MII_RX_ER | TIM2_CH3
{&GPIOB, NULL, 0, ADCx, NULL}, // D27/PB11 | 48 | I2C2_SDA | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN | TIM2_CH4
{&GPIOB, NULL, 0, ADCx, NULL}, // D28/PB12 | 51 | SPI2_NSS | I2S2_WS | I2C2_SMBA | USART3_CK | TIM1_BKIN | CAN2_RX | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
{&GPIOB, NULL, 0, ADCx, NULL}, // D29/PB13 | 52 | SPI2_SCK | I2S2_CK | USART3_CTS | TIM1_CH1N | CAN2_TX | OTG_HS_ULPI_D6 | ETH_RMII_TXD1 | ETH_MII_TXD1
{&GPIOB, NULL, 0, ADCx, NULL}, // D30/PB14 | 53 | SPI2_MISO | TIM1_CH2N | TIM12_CH1 | OTG_HS_DM | USART3_RTS | TIM8_CH2N | I2S2ext_SD
{&GPIOB, NULL, 0, ADCx, NULL}, // D31/PB15 | 54 | SPI2_MOSI | I2S2_SD | TIM1_CH3N | TIM8_CH3N | TIM12_CH2 | OTG_HS_DP
{&GPIOC, NULL, 0, 10, &ADC1}, // D32/PC0 | 15 | OTG_HS_ULPI_STP | ADC123_IN10
{&GPIOC, NULL, 0, 11, &ADC1}, // D33/PC1 | 16 | ETH_MDC | ADC123_IN11
{&GPIOC, NULL, 0, 12, &ADC1}, // D34/PC2 | 17 | SPI2_MISO | OTG_HS_ULPI_DIR | ETH_MII_TXD2 | I2S2ext_SD | ADC123_IN12
{&GPIOC, NULL, 0, 13, &ADC1}, // D35/PC3 | 18 | SPI2_MOSI | I2S2_SD | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
{&GPIOC, NULL, 0, 14, &ADC1}, // D36/PC4 | 33 | ETH_RMII_RX_D0 | ETH_MII_RX_D0 | ADC12_IN14
{&GPIOC, NULL, 0, 15, &ADC1}, // D37/PC5 | 34 | ETH_RMII_RX_D1 | ETH_MII_RX_D1 | ADC12_IN15
{&GPIOC, &timer8, 1, ADCx, NULL}, // D38/PC6 | 63 | I2S2_MCK | TIM8_CH1/SDIO_D6 | USART6_TX | DCMI_D0/TIM3_CH1
{&GPIOC, &timer8, 2, ADCx, NULL}, // D39/PC7 | 64 | I2S3_MCK | TIM8_CH2/SDIO_D7 | USART6_RX | DCMI_D1/TIM3_CH2
{&GPIOC, &timer8, 3, ADCx, NULL}, // D40/PC8 | 65 | TIM8_CH3 | SDIO_D0 | TIM3_CH3 | USART6_CK | DCMI_D2
{&GPIOC, &timer8, 4, ADCx, NULL}, // D41/PC9 | 66 | I2S_CKIN | MCO2 | TIM8_CH4 | SDIO_D1 | I2C3_SDA | DCMI_D3 | TIM3_CH4
{&GPIOC, NULL, 0, ADCx, NULL}, // D42/PC10 | 78 | SPI3_SCK | I2S3_CK | UART4_TX | SDIO_D2 | DCMI_D8 | USART3_TX
{&GPIOC, NULL, 0, ADCx, NULL}, // D43/PC11 | 79 | UART4_RX | SPI3_MISO | SDIO_D3 | DCMI_D4 | USART3_RX | I2S3ext_SD
{&GPIOC, NULL, 0, ADCx, NULL}, // D44/PC12 | 80 | UART5_TX | SDIO_CK | DCMI_D9 | SPI3_MOSI | I2S3_SD | USART3_CK
{&GPIOC, NULL, 0, ADCx, NULL}, // D45/PC13 | 7 | RTC_OUT, RTC_TAMP1, RTC_TS
{&GPIOC, NULL, 0, ADCx, NULL}, // D46/PC14 | 8 | OSC32_IN
{&GPIOC, NULL, 0, ADCx, NULL}, // D47/PC15 | 9 | OSC32_OUT
{&GPIOD, NULL, 0, ADCx, NULL}, // D48/PD0 | 81 | FSMC_D2 | CAN1_RX
{&GPIOD, NULL, 0, ADCx, NULL}, // D49/PD1 | 82 | FSMC_D3 | CAN1_TX
{&GPIOD, NULL, 0, ADCx, NULL}, // D50/PD2 | 83 | TIM3_ETR | UART5_RX | SDIO_CMD | DCMI_D11
{&GPIOD, NULL, 0, ADCx, NULL}, // D51/PD3 | 84 | FSMC_CLK | USART2_CTS
{&GPIOD, NULL, 0, ADCx, NULL}, // D52/PD4 | 85 | FSMC_NOE | USART2_RTS
{&GPIOD, NULL, 0, ADCx, NULL}, // D53/PD5 | 86 | FSMC_NWE | USART2_TX
{&GPIOD, NULL, 0, ADCx, NULL}, // D54/PD6 | 87 | FSMC_NWAIT | USART2_RX
{&GPIOD, NULL, 0, ADCx, NULL}, // D55/PD7 | 88 | USART2_CK | FSMC_NE1 | FSMC_NCE2
{&GPIOD, NULL, 0, ADCx, NULL}, // D56/PD8 | 55 | FSMC_D13 | USART3_TX
{&GPIOD, NULL, 0, ADCx, NULL}, // D57/PD9 | 56 | FSMC_D14 | USART3_RX
{&GPIOD, NULL, 0, ADCx, NULL}, // D58/PD10 | 57 | FSMC_D15 | USART3_CK
{&GPIOD, NULL, 0, ADCx, NULL}, // D59/PD11 | 58 | FSMC_CLE | FSMC_A16 | USART3_CTS
{&GPIOD, &timer4, 1, ADCx, NULL}, // D60/PD12 | 59 | FSMC_ALE | FSMC_A17 | TIM4_CH1 | USART3_RTS // remap in
{&GPIOD, &timer4, 2, ADCx, NULL}, // D61/PD13 | 60 | FSMC_A18 | TIM4_CH2 // remap in
{&GPIOD, &timer4, 3, ADCx, NULL}, // D62/PD14 | 61 | FSMC_D0 | TIM4_CH3 // remap in
{&GPIOD, &timer4, 4, ADCx, NULL}, // D63/PD15 | 62 | FSMC_D1 | TIM4_CH4 // remap in
{&GPIOE, NULL, 0, ADCx, NULL}, // D64/PE0 | 97 | TIM4_ETR | FSMC_NBL0 | DCMI_D2
{&GPIOE, NULL, 0, ADCx, NULL}, // D65/PE1 | 98 | FSMC_NBL1 | DCMI_D3
{&GPIOE, NULL, 0, ADCx, NULL}, // D66/PE2 | 1 | TRACECLK | FSMC_A23 | ETH_MII_TXD3
{&GPIOE, NULL, 0, ADCx, NULL}, // D67/PE3 | 2 | TRACED0 | FSMC_A19
{&GPIOE, NULL, 0, ADCx, NULL}, // D68/PE4 | 3 | TRACED1 | FSMC_A20 | DCMI_D4
{&GPIOE, NULL, 0, ADCx, NULL}, // D69/PE5 | 4 | TRACED2 | FSMC_A21 | TIM9_CH1 / DCMI_D6
{&GPIOE, NULL, 0, ADCx, NULL}, // D70/PE6 | 5 | TRACED3 | FSMC_A22 | TIM9_CH2 / DCMI_D7
{&GPIOE, NULL, 0, ADCx, NULL}, // D71/PE7 | 38 | FSMC_D4 | TIM1_ETR
{&GPIOE, NULL, 0, ADCx, NULL}, // D72/PE8 | 39 | FSMC_D5 | TIM1_CH1N
{&GPIOE, &timer1, 1, ADCx, NULL}, // D73/PE9 | 40 | FSMC_D6 | TIM1_CH1 // remap in
{&GPIOE, NULL, 0, ADCx, NULL}, // D74/PE10 | 41 | FSMC_D7 | TIM1_CH2N
{&GPIOE, &timer1, 2, ADCx, NULL}, // D75/PE11 | 42 | FSMC_D8 | TIM1_CH2 // remap in
{&GPIOE, NULL, 0, ADCx, NULL}, // D76/PE12 | 43 | FSMC_D9 | TIM1_CH3N
{&GPIOE, &timer1, 3, ADCx, NULL}, // D77/PE13 | 44 | FSMC_D10 | TIM1_CH3 // remap in
{&GPIOE, &timer1, 4, ADCx, NULL}, // D78/PE14 | 45 | FSMC_D11 | TIM1_CH4 // remap in
{&GPIOE, NULL, 0, ADCx, NULL}, // D79/PE15 | 46 | FSMC_D12 | TIM1_BKIN
#if 0
{GPIOF, 0, NULL, 0, NULL, ADCx}, // D80/PF0
{GPIOF, 1, NULL, 0, NULL, ADCx}, // D81/PF1
{GPIOF, 2, NULL, 0, NULL, ADCx}, // D82/PF2
{GPIOF, 3, NULL, 0, NULL, ADCx}, // D83/PF3
{GPIOF, 4, NULL, 0, NULL, ADCx}, // D84/PF4
{GPIOF, 5, NULL, 0, NULL, ADCx}, // D85/PF5
{GPIOF, 6, NULL, 0, NULL, ADCx}, // D86/PF6
{GPIOF, 7, NULL, 0, NULL, ADCx}, // D87/PF7
{GPIOF, 8, NULL, 0, NULL, ADCx}, // D88/PF8
{GPIOF, 9, NULL, 0, NULL, ADCx}, // D89/PF9
{GPIOF, 10, NULL, 0, NULL, ADCx}, // D90/PF10
{GPIOF, 11, NULL, 0, NULL, ADCx}, // D91/PF11
{GPIOF, 12, NULL, 0, NULL, ADCx}, // D92/PF12
{GPIOF, 13, NULL, 0, NULL, ADCx}, // D93/PF13
{GPIOF, 14, NULL, 0, NULL, ADCx}, // D94/PF14
{GPIOF, 15, NULL, 0, NULL, ADCx}, // D95/PF15
{GPIOG, 0, NULL, 0, NULL, ADCx}, // D96/PG0
{GPIOG, 1, NULL, 0, NULL, ADCx}, // D97/PG1
{GPIOG, 2, NULL, 0, NULL, ADCx}, // D98/PG2
{GPIOG, 3, NULL, 0, NULL, ADCx}, // D99/PG3
{GPIOG, 4, NULL, 0, NULL, ADCx}, // D100/PG4
{GPIOG, 5, NULL, 0, NULL, ADCx}, // D101/PG5
{GPIOG, 6, NULL, 0, NULL, ADCx}, // D102/PG6
{GPIOG, 7, NULL, 0, NULL, ADCx}, // D103/PG7
{GPIOG, 8, NULL, 0, NULL, ADCx}, // D104/PG8
{GPIOG, 9, NULL, 0, NULL, ADCx}, // D105/PG9
{GPIOG, 10, NULL, 0, NULL, ADCx}, // D106/PG10
{GPIOG, 11, NULL, 0, NULL, ADCx}, // D107/PG11
{GPIOG, 12, NULL, 0, NULL, ADCx}, // D108/PG12
{GPIOG, 13, NULL, 0, NULL, ADCx}, // D109/PG13
{GPIOG, 14, NULL, 0, NULL, ADCx}, // D110/PG14
{GPIOG, 15, NULL, 0, NULL, ADCx} // D111/PG15
#endif
};
/* to be defined
extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
};
*/
const uint8 boardADCPins[BOARD_NR_ADC_PINS] = {
PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
};
const uint8 boardUsedPins[BOARD_NR_USED_PINS] = {
BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
USB_DM_PIN, USB_DP_PIN
};
#ifdef __cplusplus
}
#endif
#endif // BOARD_generic_f407v