victorpv
commit
66b3a0394e
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@ -0,0 +1,93 @@
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/*
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* test-rtc.c
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*
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* Example program that sets up the Real Time Clock and then blinks the
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* LED in patterns for seconds and alarm interrupts.
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*
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* Created by Rod Gilchrist on 11-12-24.
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Ray Burnette: 20150521:
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Edited: \Documents\Arduino\hardware\STM32\STM32F1\system\libmaple\stm32f1\include\series\rcc.h to include:
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#include <libmaple/bitband.h>
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#define RCC_BDCR_RTCSEL_LSI (0x2 << 8)
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static inline void rcc_start_lsi(void)
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static inline void rcc_start_lse(void)
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static inline void rcc_start_hse(void)
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Arduino GUI 1.7.3 from Arduino.org
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Sketch uses 20,268 bytes (18%) of program storage space. Maximum is 110,592 bytes.
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Global variables use 4,552 bytes of dynamic memory.
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*/
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#include "RTClock.h"
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#define BOARD_LED_PIN PB1
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int globAlmCnt = 0;
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int globOvCnt = 0;
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int globSecCnt = 0;
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int specAlmCnt = 0;
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int lastGlobAlmCnt = -1;
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int lastSpecAlmCnt = -1;
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void rtc_sec_intr() { if (rtc_is_second()) globSecCnt++; }
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void rtc_ovf_intr() { if (rtc_is_overflow()) globOvCnt++; }
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void rtc_glob_alm_intr() { if (rtc_is_alarm()) globAlmCnt++; }
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void rtc_spec_alm_intr() { if (rtc_is_alarm()) specAlmCnt++; }
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void setup() {
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// http://forums.leaflabs.com/topic.php?id=1437
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// slow! div speed. NOTE! 512 is stop/hang when USB not connected!
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// rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_256);
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// Normal speed:
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// rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1);
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pinMode(BOARD_LED_PIN, OUTPUT);
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delay(5000);
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Serial.println("begin RTC blink");
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delay(1000);
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rtc_init(RTCSEL_LSI);
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rtc_set_prescaler_load(0x7fff);
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rtc_set_count(0);
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rtc_attach_interrupt(RTC_SECONDS_INTERRUPT, rtc_sec_intr);
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rtc_attach_interrupt(RTC_OVERFLOW_INTERRUPT, rtc_ovf_intr); // expected every 128000 seconds
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rtc_attach_interrupt(RTC_ALARM_GLOBAL_INTERRUPT, rtc_glob_alm_intr);
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rtc_attach_interrupt(RTC_ALARM_SPECIFIC_INTERRUPT, rtc_spec_alm_intr);
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}
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void loop() {
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int i,n;
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Serial.print("Time + interrupt counts: ");
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Serial.print(rtc_get_count());
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Serial.print(".");
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Serial.print(rtc_get_divider());
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Serial.print(" (");
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Serial.print(globSecCnt);
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Serial.print(", ");
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Serial.print(globOvCnt);
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Serial.print(", ");
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Serial.print(globAlmCnt);
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Serial.print(", ");
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Serial.print(specAlmCnt);
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Serial.println(")");
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delay(1000);
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digitalWrite(BOARD_LED_PIN, 1);
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if ((lastSpecAlmCnt != specAlmCnt) || (lastGlobAlmCnt != globAlmCnt)){
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lastGlobAlmCnt = globAlmCnt;
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lastSpecAlmCnt = specAlmCnt;
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Serial.println(" -- alarm -- ");
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for (i=0;i<3;i++) { digitalWrite(BOARD_LED_PIN, 0); delay(100); digitalWrite(BOARD_LED_PIN, 1); delay(100);}
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n = rtc_get_count() + 5;
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rtc_set_alarm(n);
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}
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delay(1000);
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digitalWrite(BOARD_LED_PIN, 0);
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}
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@ -0,0 +1,33 @@
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#include <RTClock.h>
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RTClock rt (RTCSEL_LSE); // initialise
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uint32 tt;
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#define LED_PIN PB1
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// This function is called in the attachSecondsInterrpt
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void blink ()
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{
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digitalWrite(LED_PIN,!digitalRead(LED_PIN));
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}
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void setup()
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{
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pinMode(LED_PIN, OUTPUT);
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rt.attachSecondsInterrupt(blink);// Call blink
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}
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void loop()
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{
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if (rt.getTime()!=tt)
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{
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tt = rt.getTime();
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Serial.print("time is: ");
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Serial.println(tt);
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}
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}
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@ -0,0 +1,23 @@
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#######################################
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# Syntax Coloring Map RTClock
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#######################################
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#######################################
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# Datatypes (KEYWORD1)
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#######################################
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RTClock KEYWORD1
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setTime KEYWORD2
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getTime KEYWORD2
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createAlarm KEYWORD2
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attachSecondsInterrupt KEYWORD2
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detachSecondsInterrupt KEYWORD2
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setAlarmTime KEYWORD2
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#######################################
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# Constants (LITERAL1)
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#######################################
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@ -0,0 +1,8 @@
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name=RTClock
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version=1.0
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author=Various
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email=
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sentence=Real Time Clock
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paragraph=Real Time Clock for STM32F1
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url=
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architectures=STM32F1
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@ -1,4 +1,6 @@
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#include "utility/rtc_util.h"
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#include <utility/rtc_util.h>
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#include <libmaple/rcc.h>
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#include <libmaple/bitband.h>
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#include <time.h>
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@ -34,13 +34,13 @@
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#ifndef _RTC_UTIL_H
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#define _RTC_UTIL_H
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#include <libmaple\libmaple.h>
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#include <libmaple\rcc.h>
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#include <libmaple\nvic.h>
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#include <libmaple\bitband.h>
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#include <libmaple\pwr.h>
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#include <libmaple\bkp.h>
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#include <libmaple\exti.h>
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#include <libmaple/libmaple.h>
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#include <libmaple/rcc.h>
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#include <libmaple/nvic.h>
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#include <libmaple/bitband.h>
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#include <libmaple/pwr.h>
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#include <libmaple/bkp.h>
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#include <libmaple/exti.h>
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#define EXTI_RTC_ALARM_BIT 17 // the extra exti interrupts (16,17,18,19) should be defined in exti.h (BUG)
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@ -1,19 +0,0 @@
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Real Time Clock implementation for the STM32F1xx family of microcontrollers.
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It has been tested in:
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- Maple
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- Maple Mini
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- Olimexino.
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RTClockTest.pde is an example to use all the features in the library.
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Instructions:
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- Copy the folder to the MapleIDE\libraries folder. You may have to create a new folder named libraries
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- Copy the files in the New RCC folder and replace the same files in your libmaple installation with them.
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- Open the example PDE
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- Compile, Download and Test.
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@ -1,27 +0,0 @@
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#include <RTClock.h>
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//#include <time.h>
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RTClock rt (RTCSEL_LSE);
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uint32 tt;
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//time_t timer;
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void blink () {
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toggleLED();
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}
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void setup() {
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pinMode(PB1, OUTPUT);// Roger Clark. Updated for removal of LED pin as a global define (PB1 is Maple mini LED Pin)
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rt.attachSecondsInterrupt(blink);
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}
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void loop() {
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tt = rt.getTime();
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SerialUSB.print("time is: ");
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SerialUSB.println(tt);
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// toggleLED();
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}
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@ -1,204 +0,0 @@
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/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @brief Implements pretty much only the basic clock setup on the
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* stm32, clock enable/disable and peripheral reset commands.
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*/
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#include "libmaple.h"
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#include "flash.h"
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#include "rcc.h"
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#include "bitband.h"
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#define APB1 RCC_APB1
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#define APB2 RCC_APB2
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#define AHB RCC_AHB
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struct rcc_dev_info {
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const rcc_clk_domain clk_domain;
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const uint8 line_num;
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};
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/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
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* register bit numbers. */
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static const struct rcc_dev_info rcc_dev_table[] = {
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[RCC_GPIOA] = { .clk_domain = APB2, .line_num = 2 },
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[RCC_GPIOB] = { .clk_domain = APB2, .line_num = 3 },
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[RCC_GPIOC] = { .clk_domain = APB2, .line_num = 4 },
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[RCC_GPIOD] = { .clk_domain = APB2, .line_num = 5 },
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[RCC_AFIO] = { .clk_domain = APB2, .line_num = 0 },
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[RCC_ADC1] = { .clk_domain = APB2, .line_num = 9 },
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[RCC_ADC2] = { .clk_domain = APB2, .line_num = 10 },
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[RCC_ADC3] = { .clk_domain = APB2, .line_num = 15 },
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[RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
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[RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
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[RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
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[RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
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[RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
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[RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
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[RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
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[RCC_SPI1] = { .clk_domain = APB2, .line_num = 12 },
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[RCC_SPI2] = { .clk_domain = APB1, .line_num = 14 },
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[RCC_DMA1] = { .clk_domain = AHB, .line_num = 0 },
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[RCC_PWR] = { .clk_domain = APB1, .line_num = 28},
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[RCC_BKP] = { .clk_domain = APB1, .line_num = 27},
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[RCC_I2C1] = { .clk_domain = APB1, .line_num = 21 },
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[RCC_I2C2] = { .clk_domain = APB1, .line_num = 22 },
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[RCC_CRC] = { .clk_domain = AHB, .line_num = 6},
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[RCC_FLITF] = { .clk_domain = AHB, .line_num = 4},
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[RCC_SRAM] = { .clk_domain = AHB, .line_num = 2},
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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[RCC_GPIOE] = { .clk_domain = APB2, .line_num = 6 },
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[RCC_GPIOF] = { .clk_domain = APB2, .line_num = 7 },
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[RCC_GPIOG] = { .clk_domain = APB2, .line_num = 8 },
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[RCC_UART4] = { .clk_domain = APB1, .line_num = 19 },
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[RCC_UART5] = { .clk_domain = APB1, .line_num = 20 },
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[RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
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[RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
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[RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
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[RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
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[RCC_FSMC] = { .clk_domain = AHB, .line_num = 8 },
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[RCC_DAC] = { .clk_domain = APB1, .line_num = 29 },
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[RCC_DMA2] = { .clk_domain = AHB, .line_num = 1 },
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[RCC_SDIO] = { .clk_domain = AHB, .line_num = 10 },
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[RCC_SPI3] = { .clk_domain = APB1, .line_num = 15 },
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#endif
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#ifdef STM32_XL_DENSITY
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[RCC_TIMER9] = { .clk_domain = APB2, .line_num = 19 },
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[RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
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[RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
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[RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
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[RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
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[RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
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#endif
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};
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/**
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* @brief Initialize the clock control system. Initializes the system
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* clock source to use the PLL driven by an external oscillator
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* @param sysclk_src system clock source, must be PLL
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* @param pll_src pll clock source, must be HSE
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* @param pll_mul pll multiplier
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*/
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void rcc_clk_init(rcc_sysclk_src sysclk_src,
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rcc_pllsrc pll_src,
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rcc_pll_multiplier pll_mul) {
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uint32 cfgr = 0;
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uint32 cr;
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/* Assume that we're going to clock the chip off the PLL, fed by
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* the HSE */
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ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
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pll_src == RCC_PLLSRC_HSE);
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RCC_BASE->CFGR = pll_src | pll_mul;
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/* Turn on the HSE */
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cr = RCC_BASE->CR;
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cr |= RCC_CR_HSEON;
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RCC_BASE->CR = cr;
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while (!(RCC_BASE->CR & RCC_CR_HSERDY))
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;
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/* Now the PLL */
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cr |= RCC_CR_PLLON;
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RCC_BASE->CR = cr;
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while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
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;
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/* Finally, let's switch over to the PLL */
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cfgr &= ~RCC_CFGR_SW;
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cfgr |= RCC_CFGR_SW_PLL;
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RCC_BASE->CFGR = cfgr;
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while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
|
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;
|
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}
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/**
|
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* @brief Turn on the clock line on a peripheral
|
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* @param id Clock ID of the peripheral to turn on.
|
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*/
|
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void rcc_clk_enable(rcc_clk_id id) {
|
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static const __io uint32* enable_regs[] = {
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[APB1] = &RCC_BASE->APB1ENR,
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[APB2] = &RCC_BASE->APB2ENR,
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[AHB] = &RCC_BASE->AHBENR,
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};
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rcc_clk_domain clk_domain = rcc_dev_clk(id);
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__io uint32* enr = (__io uint32*)enable_regs[clk_domain];
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uint8 lnum = rcc_dev_table[id].line_num;
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bb_peri_set_bit(enr, lnum, 1);
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}
|
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|
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/**
|
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* @brief Reset a peripheral.
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* @param id Clock ID of the peripheral to reset.
|
||||
*/
|
||||
void rcc_reset_dev(rcc_clk_id id) {
|
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static const __io uint32* reset_regs[] = {
|
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[APB1] = &RCC_BASE->APB1RSTR,
|
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[APB2] = &RCC_BASE->APB2RSTR,
|
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};
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rcc_clk_domain clk_domain = rcc_dev_clk(id);
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__io void* addr = (__io void*)reset_regs[clk_domain];
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uint8 lnum = rcc_dev_table[id].line_num;
|
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bb_peri_set_bit(addr, lnum, 1);
|
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bb_peri_set_bit(addr, lnum, 0);
|
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}
|
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|
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/**
|
||||
* @brief Get a peripheral's clock domain
|
||||
* @param id Clock ID of the peripheral whose clock domain to return
|
||||
* @return Clock source for the given clock ID
|
||||
*/
|
||||
rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
|
||||
return rcc_dev_table[id].clk_domain;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the divider on a peripheral prescaler
|
||||
* @param prescaler prescaler to set
|
||||
* @param divider prescaler divider
|
||||
*/
|
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void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
|
||||
static const uint32 masks[] = {
|
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[RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
|
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[RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
|
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[RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
|
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[RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
|
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[RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
|
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};
|
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|
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uint32 cfgr = RCC_BASE->CFGR;
|
||||
cfgr &= ~masks[prescaler];
|
||||
cfgr |= divider;
|
||||
RCC_BASE->CFGR = cfgr;
|
||||
}
|
||||
|
|
@ -1,619 +0,0 @@
|
|||
/******************************************************************************
|
||||
* The MIT License
|
||||
*
|
||||
* Copyright (c) 2010 Perry Hung.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use, copy,
|
||||
* modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
* of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file rcc.h
|
||||
* @brief reset and clock control definitions and prototypes
|
||||
*/
|
||||
|
||||
#include "libmaple_types.h"
|
||||
#include "util.h"
|
||||
#include "bitband.h"
|
||||
|
||||
#ifndef _RCC_H_
|
||||
#define _RCC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
/** RCC register map type */
|
||||
typedef struct rcc_reg_map {
|
||||
__io uint32 CR; /**< Clock control register */
|
||||
__io uint32 CFGR; /**< Clock configuration register */
|
||||
__io uint32 CIR; /**< Clock interrupt register */
|
||||
__io uint32 APB2RSTR; /**< APB2 peripheral reset register */
|
||||
__io uint32 APB1RSTR; /**< APB1 peripheral reset register */
|
||||
__io uint32 AHBENR; /**< AHB peripheral clock enable register */
|
||||
__io uint32 APB2ENR; /**< APB2 peripheral clock enable register */
|
||||
__io uint32 APB1ENR; /**< APB1 peripheral clock enable register */
|
||||
__io uint32 BDCR; /**< Backup domain control register */
|
||||
__io uint32 CSR; /**< Control/status register */
|
||||
} rcc_reg_map;
|
||||
|
||||
/** RCC register map base pointer */
|
||||
#define RCC_BASE ((struct rcc_reg_map*)0x40021000)
|
||||
|
||||
/*
|
||||
* Register bit definitions
|
||||
*/
|
||||
|
||||
/* Clock control register */
|
||||
|
||||
#define RCC_CR_PLLRDY_BIT 25
|
||||
#define RCC_CR_PLLON_BIT 24
|
||||
#define RCC_CR_CSSON_BIT 19
|
||||
#define RCC_CR_HSEBYP_BIT 18
|
||||
#define RCC_CR_HSERDY_BIT 17
|
||||
#define RCC_CR_HSEON_BIT 16
|
||||
#define RCC_CR_HSIRDY_BIT 1
|
||||
#define RCC_CR_HSION_BIT 0
|
||||
|
||||
#define RCC_CR_PLLRDY BIT(RCC_CR_PLLRDY_BIT)
|
||||
#define RCC_CR_PLLON BIT(RCC_CR_PLLON_BIT)
|
||||
#define RCC_CR_CSSON BIT(RCC_CR_CSSON_BIT)
|
||||
#define RCC_CR_HSEBYP BIT(RCC_CR_HSEBYP_BIT)
|
||||
#define RCC_CR_HSERDY BIT(RCC_CR_HSERDY_BIT)
|
||||
#define RCC_CR_HSEON BIT(RCC_CR_HSEON_BIT)
|
||||
#define RCC_CR_HSICAL (0xFF << 8)
|
||||
#define RCC_CR_HSITRIM (0x1F << 3)
|
||||
#define RCC_CR_HSIRDY BIT(RCC_CR_HSIRDY_BIT)
|
||||
#define RCC_CR_HSION BIT(RCC_CR_HSION_BIT)
|
||||
|
||||
/* Clock configuration register */
|
||||
|
||||
#define RCC_CFGR_USBPRE_BIT 22
|
||||
#define RCC_CFGR_PLLXTPRE_BIT 17
|
||||
#define RCC_CFGR_PLLSRC_BIT 16
|
||||
|
||||
#define RCC_CFGR_MCO (0x3 << 24)
|
||||
#define RCC_CFGR_USBPRE BIT(RCC_CFGR_USBPRE_BIT)
|
||||
#define RCC_CFGR_PLLMUL (0xF << 18)
|
||||
#define RCC_CFGR_PLLXTPRE BIT(RCC_CFGR_PLLXTPRE_BIT)
|
||||
#define RCC_CFGR_PLLSRC BIT(RCC_CFGR_PLLSRC_BIT)
|
||||
#define RCC_CFGR_ADCPRE (0x3 << 14)
|
||||
#define RCC_CFGR_PPRE2 (0x7 << 11)
|
||||
#define RCC_CFGR_PPRE1 (0x7 << 8)
|
||||
#define RCC_CFGR_HPRE (0xF << 4)
|
||||
#define RCC_CFGR_SWS (0x3 << 2)
|
||||
#define RCC_CFGR_SWS_PLL (0x2 << 2)
|
||||
#define RCC_CFGR_SWS_HSE (0x1 << 2)
|
||||
#define RCC_CFGR_SW 0x3
|
||||
#define RCC_CFGR_SW_PLL 0x2
|
||||
#define RCC_CFGR_SW_HSE 0x1
|
||||
|
||||
/* Clock interrupt register */
|
||||
|
||||
#define RCC_CIR_CSSC_BIT 23
|
||||
#define RCC_CIR_PLLRDYC_BIT 20
|
||||
#define RCC_CIR_HSERDYC_BIT 19
|
||||
#define RCC_CIR_HSIRDYC_BIT 18
|
||||
#define RCC_CIR_LSERDYC_BIT 17
|
||||
#define RCC_CIR_LSIRDYC_BIT 16
|
||||
#define RCC_CIR_PLLRDYIE_BIT 12
|
||||
#define RCC_CIR_HSERDYIE_BIT 11
|
||||
#define RCC_CIR_HSIRDYIE_BIT 10
|
||||
#define RCC_CIR_LSERDYIE_BIT 9
|
||||
#define RCC_CIR_LSIRDYIE_BIT 8
|
||||
#define RCC_CIR_CSSF_BIT 7
|
||||
#define RCC_CIR_PLLRDYF_BIT 4
|
||||
#define RCC_CIR_HSERDYF_BIT 3
|
||||
#define RCC_CIR_HSIRDYF_BIT 2
|
||||
#define RCC_CIR_LSERDYF_BIT 1
|
||||
#define RCC_CIR_LSIRDYF_BIT 0
|
||||
|
||||
#define RCC_CIR_CSSC BIT(RCC_CIR_CSSC_BIT)
|
||||
#define RCC_CIR_PLLRDYC BIT(RCC_CIR_PLLRDYC_BIT)
|
||||
#define RCC_CIR_HSERDYC BIT(RCC_CIR_HSERDYC_BIT)
|
||||
#define RCC_CIR_HSIRDYC BIT(RCC_CIR_HSIRDYC_BIT)
|
||||
#define RCC_CIR_LSERDYC BIT(RCC_CIR_LSERDYC_BIT)
|
||||
#define RCC_CIR_LSIRDYC BIT(RCC_CIR_LSIRDYC_BIT)
|
||||
#define RCC_CIR_PLLRDYIE BIT(RCC_CIR_PLLRDYIE_BIT)
|
||||
#define RCC_CIR_HSERDYIE BIT(RCC_CIR_HSERDYIE_BIT)
|
||||
#define RCC_CIR_HSIRDYIE BIT(RCC_CIR_HSIRDYIE_BIT)
|
||||
#define RCC_CIR_LSERDYIE BIT(RCC_CIR_LSERDYIE_BIT)
|
||||
#define RCC_CIR_LSIRDYIE BIT(RCC_CIR_LSIRDYIE_BIT)
|
||||
#define RCC_CIR_CSSF BIT(RCC_CIR_CSSF_BIT)
|
||||
#define RCC_CIR_PLLRDYF BIT(RCC_CIR_PLLRDYF_BIT)
|
||||
#define RCC_CIR_HSERDYF BIT(RCC_CIR_HSERDYF_BIT)
|
||||
#define RCC_CIR_HSIRDYF BIT(RCC_CIR_HSIRDYF_BIT)
|
||||
#define RCC_CIR_LSERDYF BIT(RCC_CIR_LSERDYF_BIT)
|
||||
#define RCC_CIR_LSIRDYF BIT(RCC_CIR_LSIRDYF_BIT)
|
||||
|
||||
/* APB2 peripheral reset register */
|
||||
|
||||
#define RCC_APB2RSTR_TIM11RST_BIT 21
|
||||
#define RCC_APB2RSTR_TIM10RST_BIT 20
|
||||
#define RCC_APB2RSTR_TIM9RST_BIT 19
|
||||
#define RCC_APB2RSTR_ADC3RST_BIT 15
|
||||
#define RCC_APB2RSTR_USART1RST_BIT 14
|
||||
#define RCC_APB2RSTR_TIM8RST_BIT 13
|
||||
#define RCC_APB2RSTR_SPI1RST_BIT 12
|
||||
#define RCC_APB2RSTR_TIM1RST_BIT 11
|
||||
#define RCC_APB2RSTR_ADC2RST_BIT 10
|
||||
#define RCC_APB2RSTR_ADC1RST_BIT 9
|
||||
#define RCC_APB2RSTR_IOPGRST_BIT 8
|
||||
#define RCC_APB2RSTR_IOPFRST_BIT 7
|
||||
#define RCC_APB2RSTR_IOPERST_BIT 6
|
||||
#define RCC_APB2RSTR_IOPDRST_BIT 5
|
||||
#define RCC_APB2RSTR_IOPCRST_BIT 4
|
||||
#define RCC_APB2RSTR_IOPBRST_BIT 3
|
||||
#define RCC_APB2RSTR_IOPARST_BIT 2
|
||||
#define RCC_APB2RSTR_AFIORST_BIT 0
|
||||
|
||||
#define RCC_APB2RSTR_TIM11RST BIT(RCC_APB2RSTR_TIM11RST_BIT)
|
||||
#define RCC_APB2RSTR_TIM10RST BIT(RCC_APB2RSTR_TIM10RST_BIT)
|
||||
#define RCC_APB2RSTR_TIM9RST BIT(RCC_APB2RSTR_TIM9RST_BIT)
|
||||
#define RCC_APB2RSTR_ADC3RST BIT(RCC_APB2RSTR_ADC3RST_BIT)
|
||||
#define RCC_APB2RSTR_USART1RST BIT(RCC_APB2RSTR_USART1RST_BIT)
|
||||
#define RCC_APB2RSTR_TIM8RST BIT(RCC_APB2RSTR_TIM8RST_BIT)
|
||||
#define RCC_APB2RSTR_SPI1RST BIT(RCC_APB2RSTR_SPI1RST_BIT)
|
||||
#define RCC_APB2RSTR_TIM1RST BIT(RCC_APB2RSTR_TIM1RST_BIT)
|
||||
#define RCC_APB2RSTR_ADC2RST BIT(RCC_APB2RSTR_ADC2RST_BIT)
|
||||
#define RCC_APB2RSTR_ADC1RST BIT(RCC_APB2RSTR_ADC1RST_BIT)
|
||||
#define RCC_APB2RSTR_IOPGRST BIT(RCC_APB2RSTR_IOPGRST_BIT)
|
||||
#define RCC_APB2RSTR_IOPFRST BIT(RCC_APB2RSTR_IOPFRST_BIT)
|
||||
#define RCC_APB2RSTR_IOPERST BIT(RCC_APB2RSTR_IOPERST_BIT)
|
||||
#define RCC_APB2RSTR_IOPDRST BIT(RCC_APB2RSTR_IOPDRST_BIT)
|
||||
#define RCC_APB2RSTR_IOPCRST BIT(RCC_APB2RSTR_IOPCRST_BIT)
|
||||
#define RCC_APB2RSTR_IOPBRST BIT(RCC_APB2RSTR_IOPBRST_BIT)
|
||||
#define RCC_APB2RSTR_IOPARST BIT(RCC_APB2RSTR_IOPARST_BIT)
|
||||
#define RCC_APB2RSTR_AFIORST BIT(RCC_APB2RSTR_AFIORST_BIT)
|
||||
|
||||
/* APB1 peripheral reset register */
|
||||
|
||||
#define RCC_APB1RSTR_DACRST_BIT 29
|
||||
#define RCC_APB1RSTR_PWRRST_BIT 28
|
||||
#define RCC_APB1RSTR_BKPRST_BIT 27
|
||||
#define RCC_APB1RSTR_CANRST_BIT 25
|
||||
#define RCC_APB1RSTR_USBRST_BIT 23
|
||||
#define RCC_APB1RSTR_I2C2RST_BIT 22
|
||||
#define RCC_APB1RSTR_I2C1RST_BIT 21
|
||||
#define RCC_APB1RSTR_UART5RST_BIT 20
|
||||
#define RCC_APB1RSTR_UART4RST_BIT 19
|
||||
#define RCC_APB1RSTR_USART3RST_BIT 18
|
||||
#define RCC_APB1RSTR_USART2RST_BIT 17
|
||||
#define RCC_APB1RSTR_SPI3RST_BIT 15
|
||||
#define RCC_APB1RSTR_SPI2RST_BIT 14
|
||||
#define RCC_APB1RSTR_WWDRST_BIT 11
|
||||
#define RCC_APB1RSTR_TIM14RST_BIT 8
|
||||
#define RCC_APB1RSTR_TIM13RST_BIT 7
|
||||
#define RCC_APB1RSTR_TIM12RST_BIT 6
|
||||
#define RCC_APB1RSTR_TIM7RST_BIT 5
|
||||
#define RCC_APB1RSTR_TIM6RST_BIT 4
|
||||
#define RCC_APB1RSTR_TIM5RST_BIT 3
|
||||
#define RCC_APB1RSTR_TIM4RST_BIT 2
|
||||
#define RCC_APB1RSTR_TIM3RST_BIT 1
|
||||
#define RCC_APB1RSTR_TIM2RST_BIT 0
|
||||
|
||||
#define RCC_APB1RSTR_DACRST BIT(RCC_APB1RSTR_DACRST_BIT)
|
||||
#define RCC_APB1RSTR_PWRRST BIT(RCC_APB1RSTR_PWRRST_BIT)
|
||||
#define RCC_APB1RSTR_BKPRST BIT(RCC_APB1RSTR_BKPRST_BIT)
|
||||
#define RCC_APB1RSTR_CANRST BIT(RCC_APB1RSTR_CANRST_BIT)
|
||||
#define RCC_APB1RSTR_USBRST BIT(RCC_APB1RSTR_USBRST_BIT)
|
||||
#define RCC_APB1RSTR_I2C2RST BIT(RCC_APB1RSTR_I2C2RST_BIT)
|
||||
#define RCC_APB1RSTR_I2C1RST BIT(RCC_APB1RSTR_I2C1RST_BIT)
|
||||
#define RCC_APB1RSTR_UART5RST BIT(RCC_APB1RSTR_UART5RST_BIT)
|
||||
#define RCC_APB1RSTR_UART4RST BIT(RCC_APB1RSTR_UART4RST_BIT)
|
||||
#define RCC_APB1RSTR_USART3RST BIT(RCC_APB1RSTR_USART3RST_BIT)
|
||||
#define RCC_APB1RSTR_USART2RST BIT(RCC_APB1RSTR_USART2RST_BIT)
|
||||
#define RCC_APB1RSTR_SPI3RST BIT(RCC_APB1RSTR_SPI3RST_BIT)
|
||||
#define RCC_APB1RSTR_SPI2RST BIT(RCC_APB1RSTR_SPI2RST_BIT)
|
||||
#define RCC_APB1RSTR_WWDRST BIT(RCC_APB1RSTR_WWDRST_BIT)
|
||||
#define RCC_APB1RSTR_TIM14RST BIT(RCC_APB1RSTR_TIM14RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM13RST BIT(RCC_APB1RSTR_TIM13RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM12RST BIT(RCC_APB1RSTR_TIM12RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM7RST BIT(RCC_APB1RSTR_TIM7RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM6RST BIT(RCC_APB1RSTR_TIM6RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM5RST BIT(RCC_APB1RSTR_TIM5RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM4RST BIT(RCC_APB1RSTR_TIM4RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM3RST BIT(RCC_APB1RSTR_TIM3RST_BIT)
|
||||
#define RCC_APB1RSTR_TIM2RST BIT(RCC_APB1RSTR_TIM2RST_BIT)
|
||||
|
||||
/* AHB peripheral clock enable register */
|
||||
|
||||
#define RCC_AHBENR_SDIOEN_BIT 10
|
||||
#define RCC_AHBENR_FSMCEN_BIT 8
|
||||
#define RCC_AHBENR_CRCEN_BIT 7
|
||||
#define RCC_AHBENR_FLITFEN_BIT 4
|
||||
#define RCC_AHBENR_SRAMEN_BIT 2
|
||||
#define RCC_AHBENR_DMA2EN_BIT 1
|
||||
#define RCC_AHBENR_DMA1EN_BIT 0
|
||||
|
||||
#define RCC_AHBENR_SDIOEN BIT(RCC_AHBENR_SDIOEN_BIT)
|
||||
#define RCC_AHBENR_FSMCEN BIT(RCC_AHBENR_FSMCEN_BIT)
|
||||
#define RCC_AHBENR_CRCEN BIT(RCC_AHBENR_CRCEN_BIT)
|
||||
#define RCC_AHBENR_FLITFEN BIT(RCC_AHBENR_FLITFEN_BIT)
|
||||
#define RCC_AHBENR_SRAMEN BIT(RCC_AHBENR_SRAMEN_BIT)
|
||||
#define RCC_AHBENR_DMA2EN BIT(RCC_AHBENR_DMA2EN_BIT)
|
||||
#define RCC_AHBENR_DMA1EN BIT(RCC_AHBENR_DMA1EN_BIT)
|
||||
|
||||
/* APB2 peripheral clock enable register */
|
||||
|
||||
#define RCC_APB2ENR_TIM11EN_BIT 21
|
||||
#define RCC_APB2ENR_TIM10EN_BIT 20
|
||||
#define RCC_APB2ENR_TIM9EN_BIT 19
|
||||
#define RCC_APB2ENR_ADC3EN_BIT 15
|
||||
#define RCC_APB2ENR_USART1EN_BIT 14
|
||||
#define RCC_APB2ENR_TIM8EN_BIT 13
|
||||
#define RCC_APB2ENR_SPI1EN_BIT 12
|
||||
#define RCC_APB2ENR_TIM1EN_BIT 11
|
||||
#define RCC_APB2ENR_ADC2EN_BIT 10
|
||||
#define RCC_APB2ENR_ADC1EN_BIT 9
|
||||
#define RCC_APB2ENR_IOPGEN_BIT 8
|
||||
#define RCC_APB2ENR_IOPFEN_BIT 7
|
||||
#define RCC_APB2ENR_IOPEEN_BIT 6
|
||||
#define RCC_APB2ENR_IOPDEN_BIT 5
|
||||
#define RCC_APB2ENR_IOPCEN_BIT 4
|
||||
#define RCC_APB2ENR_IOPBEN_BIT 3
|
||||
#define RCC_APB2ENR_IOPAEN_BIT 2
|
||||
#define RCC_APB2ENR_AFIOEN_BIT 0
|
||||
|
||||
#define RCC_APB2ENR_TIM11EN BIT(RCC_APB2ENR_TIM11EN_BIT)
|
||||
#define RCC_APB2ENR_TIM10EN BIT(RCC_APB2ENR_TIM10EN_BIT)
|
||||
#define RCC_APB2ENR_TIM9EN BIT(RCC_APB2ENR_TIM9EN_BIT)
|
||||
#define RCC_APB2ENR_ADC3EN BIT(RCC_APB2ENR_ADC3EN_BIT)
|
||||
#define RCC_APB2ENR_USART1EN BIT(RCC_APB2ENR_USART1EN_BIT)
|
||||
#define RCC_APB2ENR_TIM8EN BIT(RCC_APB2ENR_TIM8EN_BIT)
|
||||
#define RCC_APB2ENR_SPI1EN BIT(RCC_APB2ENR_SPI1EN_BIT)
|
||||
#define RCC_APB2ENR_TIM1EN BIT(RCC_APB2ENR_TIM1EN_BIT)
|
||||
#define RCC_APB2ENR_ADC2EN BIT(RCC_APB2ENR_ADC2EN_BIT)
|
||||
#define RCC_APB2ENR_ADC1EN BIT(RCC_APB2ENR_ADC1EN_BIT)
|
||||
#define RCC_APB2ENR_IOPGEN BIT(RCC_APB2ENR_IOPGEN_BIT)
|
||||
#define RCC_APB2ENR_IOPFEN BIT(RCC_APB2ENR_IOPFEN_BIT)
|
||||
#define RCC_APB2ENR_IOPEEN BIT(RCC_APB2ENR_IOPEEN_BIT)
|
||||
#define RCC_APB2ENR_IOPDEN BIT(RCC_APB2ENR_IOPDEN_BIT)
|
||||
#define RCC_APB2ENR_IOPCEN BIT(RCC_APB2ENR_IOPCEN_BIT)
|
||||
#define RCC_APB2ENR_IOPBEN BIT(RCC_APB2ENR_IOPBEN_BIT)
|
||||
#define RCC_APB2ENR_IOPAEN BIT(RCC_APB2ENR_IOPAEN_BIT)
|
||||
#define RCC_APB2ENR_AFIOEN BIT(RCC_APB2ENR_AFIOEN_BIT)
|
||||
|
||||
/* APB1 peripheral clock enable register */
|
||||
|
||||
#define RCC_APB1ENR_DACEN_BIT 29
|
||||
#define RCC_APB1ENR_PWREN_BIT 28
|
||||
#define RCC_APB1ENR_BKPEN_BIT 27
|
||||
#define RCC_APB1ENR_CANEN_BIT 25
|
||||
#define RCC_APB1ENR_USBEN_BIT 23
|
||||
#define RCC_APB1ENR_I2C2EN_BIT 22
|
||||
#define RCC_APB1ENR_I2C1EN_BIT 21
|
||||
#define RCC_APB1ENR_UART5EN_BIT 20
|
||||
#define RCC_APB1ENR_UART4EN_BIT 19
|
||||
#define RCC_APB1ENR_USART3EN_BIT 18
|
||||
#define RCC_APB1ENR_USART2EN_BIT 17
|
||||
#define RCC_APB1ENR_SPI3EN_BIT 15
|
||||
#define RCC_APB1ENR_SPI2EN_BIT 14
|
||||
#define RCC_APB1ENR_WWDEN_BIT 11
|
||||
#define RCC_APB1ENR_TIM14EN_BIT 8
|
||||
#define RCC_APB1ENR_TIM13EN_BIT 7
|
||||
#define RCC_APB1ENR_TIM12EN_BIT 6
|
||||
#define RCC_APB1ENR_TIM7EN_BIT 5
|
||||
#define RCC_APB1ENR_TIM6EN_BIT 4
|
||||
#define RCC_APB1ENR_TIM5EN_BIT 3
|
||||
#define RCC_APB1ENR_TIM4EN_BIT 2
|
||||
#define RCC_APB1ENR_TIM3EN_BIT 1
|
||||
#define RCC_APB1ENR_TIM2EN_BIT 0
|
||||
|
||||
#define RCC_APB1ENR_DACEN BIT(RCC_APB1ENR_DACEN_BIT)
|
||||
#define RCC_APB1ENR_PWREN BIT(RCC_APB1ENR_PWREN_BIT)
|
||||
#define RCC_APB1ENR_BKPEN BIT(RCC_APB1ENR_BKPEN_BIT)
|
||||
#define RCC_APB1ENR_CANEN BIT(RCC_APB1ENR_CANEN_BIT)
|
||||
#define RCC_APB1ENR_USBEN BIT(RCC_APB1ENR_USBEN_BIT)
|
||||
#define RCC_APB1ENR_I2C2EN BIT(RCC_APB1ENR_I2C2EN_BIT)
|
||||
#define RCC_APB1ENR_I2C1EN BIT(RCC_APB1ENR_I2C1EN_BIT)
|
||||
#define RCC_APB1ENR_UART5EN BIT(RCC_APB1ENR_UART5EN_BIT)
|
||||
#define RCC_APB1ENR_UART4EN BIT(RCC_APB1ENR_UART4EN_BIT)
|
||||
#define RCC_APB1ENR_USART3EN BIT(RCC_APB1ENR_USART3EN_BIT)
|
||||
#define RCC_APB1ENR_USART2EN BIT(RCC_APB1ENR_USART2EN_BIT)
|
||||
#define RCC_APB1ENR_SPI3EN BIT(RCC_APB1ENR_SPI3EN_BIT)
|
||||
#define RCC_APB1ENR_SPI2EN BIT(RCC_APB1ENR_SPI2EN_BIT)
|
||||
#define RCC_APB1ENR_WWDEN BIT(RCC_APB1ENR_WWDEN_BIT)
|
||||
#define RCC_APB1ENR_TIM14EN BIT(RCC_APB1ENR_TIM14EN_BIT)
|
||||
#define RCC_APB1ENR_TIM13EN BIT(RCC_APB1ENR_TIM13EN_BIT)
|
||||
#define RCC_APB1ENR_TIM12EN BIT(RCC_APB1ENR_TIM12EN_BIT)
|
||||
#define RCC_APB1ENR_TIM7EN BIT(RCC_APB1ENR_TIM7EN_BIT)
|
||||
#define RCC_APB1ENR_TIM6EN BIT(RCC_APB1ENR_TIM6EN_BIT)
|
||||
#define RCC_APB1ENR_TIM5EN BIT(RCC_APB1ENR_TIM5EN_BIT)
|
||||
#define RCC_APB1ENR_TIM4EN BIT(RCC_APB1ENR_TIM4EN_BIT)
|
||||
#define RCC_APB1ENR_TIM3EN BIT(RCC_APB1ENR_TIM3EN_BIT)
|
||||
#define RCC_APB1ENR_TIM2EN BIT(RCC_APB1ENR_TIM2EN_BIT)
|
||||
|
||||
/* Backup domain control register */
|
||||
|
||||
#define RCC_BDCR_BDRST_BIT 16
|
||||
#define RCC_BDCR_RTCEN_BIT 15
|
||||
#define RCC_BDCR_LSEBYP_BIT 2
|
||||
#define RCC_BDCR_LSERDY_BIT 1
|
||||
#define RCC_BDCR_LSEON_BIT 0
|
||||
|
||||
#define RCC_BDCR_BDRST BIT(RCC_BDCR_BDRST_BIT)
|
||||
#define RCC_BDCR_RTCEN BIT(RCC_BDCR_RTCEN_BI)
|
||||
#define RCC_BDCR_RTCSEL (0x3 << 8)
|
||||
#define RCC_BDCR_RTCSEL_NONE (0x0 << 8)
|
||||
#define RCC_BDCR_RTCSEL_LSE (0x1 << 8)
|
||||
#define RCC_BDCR_RTCSEL_LSI (0x2 << 8)
|
||||
#define RCC_BDCR_RTCSEL_HSE (0x3 << 8)
|
||||
#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT)
|
||||
#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT)
|
||||
#define RCC_BDCR_LSEON BIT(RCC_BDCR_LSEON_BIT)
|
||||
|
||||
/* Control/status register */
|
||||
|
||||
#define RCC_CSR_LPWRRSTF_BIT 31
|
||||
#define RCC_CSR_WWDGRSTF_BIT 30
|
||||
#define RCC_CSR_IWDGRSTF_BIT 29
|
||||
#define RCC_CSR_SFTRSTF_BIT 28
|
||||
#define RCC_CSR_PORRSTF_BIT 27
|
||||
#define RCC_CSR_PINRSTF_BIT 26
|
||||
#define RCC_CSR_RMVF_BIT 24
|
||||
#define RCC_CSR_LSIRDY_BIT 1
|
||||
#define RCC_CSR_LSION_BIT 0
|
||||
|
||||
#define RCC_CSR_LPWRRSTF BIT(RCC_CSR_LPWRRSTF_BIT)
|
||||
#define RCC_CSR_WWDGRSTF BIT(RCC_CSR_WWDGRSTF_BIT)
|
||||
#define RCC_CSR_IWDGRSTF BIT(RCC_CSR_IWDGRSTF_BIT)
|
||||
#define RCC_CSR_SFTRSTF BIT(RCC_CSR_SFTRSTF_BIT)
|
||||
#define RCC_CSR_PORRSTF BIT(RCC_CSR_PORRSTF_BIT)
|
||||
#define RCC_CSR_PINRSTF BIT(RCC_CSR_PINRSTF_BIT)
|
||||
#define RCC_CSR_RMVF BIT(RCC_CSR_RMVF_BIT)
|
||||
#define RCC_CSR_LSIRDY BIT(RCC_CSR_LSIRDY_BIT)
|
||||
#define RCC_CSR_LSION BIT(RCC_CSR_LSION_BIT)
|
||||
|
||||
/*
|
||||
* Convenience routines
|
||||
*/
|
||||
|
||||
/**
|
||||
* SYSCLK sources
|
||||
* @see rcc_clk_init()
|
||||
*/
|
||||
typedef enum rcc_sysclk_src {
|
||||
RCC_CLKSRC_HSI = 0x0,
|
||||
RCC_CLKSRC_HSE = 0x1,
|
||||
RCC_CLKSRC_PLL = 0x2,
|
||||
} rcc_sysclk_src;
|
||||
|
||||
/**
|
||||
* PLL entry clock source
|
||||
* @see rcc_clk_init()
|
||||
*/
|
||||
typedef enum rcc_pllsrc {
|
||||
RCC_PLLSRC_HSE = (0x1 << 16),
|
||||
RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
|
||||
} rcc_pllsrc;
|
||||
|
||||
/**
|
||||
* PLL multipliers
|
||||
* @see rcc_clk_init()
|
||||
*/
|
||||
typedef enum rcc_pll_multiplier {
|
||||
RCC_PLLMUL_2 = (0x0 << 18),
|
||||
RCC_PLLMUL_3 = (0x1 << 18),
|
||||
RCC_PLLMUL_4 = (0x2 << 18),
|
||||
RCC_PLLMUL_5 = (0x3 << 18),
|
||||
RCC_PLLMUL_6 = (0x4 << 18),
|
||||
RCC_PLLMUL_7 = (0x5 << 18),
|
||||
RCC_PLLMUL_8 = (0x6 << 18),
|
||||
RCC_PLLMUL_9 = (0x7 << 18),
|
||||
RCC_PLLMUL_10 = (0x8 << 18),
|
||||
RCC_PLLMUL_11 = (0x9 << 18),
|
||||
RCC_PLLMUL_12 = (0xA << 18),
|
||||
RCC_PLLMUL_13 = (0xB << 18),
|
||||
RCC_PLLMUL_14 = (0xC << 18),
|
||||
RCC_PLLMUL_15 = (0xD << 18),
|
||||
RCC_PLLMUL_16 = (0xE << 18),
|
||||
} rcc_pll_multiplier;
|
||||
|
||||
/**
|
||||
* @brief Identifies bus and clock line for a peripheral.
|
||||
*
|
||||
* Also generally useful as a unique identifier for that peripheral
|
||||
* (or its corresponding device struct).
|
||||
*/
|
||||
typedef enum rcc_clk_id {
|
||||
RCC_GPIOA,
|
||||
RCC_GPIOB,
|
||||
RCC_GPIOC,
|
||||
RCC_GPIOD,
|
||||
RCC_AFIO,
|
||||
RCC_ADC1,
|
||||
RCC_ADC2,
|
||||
RCC_ADC3,
|
||||
RCC_USART1,
|
||||
RCC_USART2,
|
||||
RCC_USART3,
|
||||
RCC_TIMER1,
|
||||
RCC_TIMER2,
|
||||
RCC_TIMER3,
|
||||
RCC_TIMER4,
|
||||
RCC_SPI1,
|
||||
RCC_SPI2,
|
||||
RCC_DMA1,
|
||||
RCC_PWR,
|
||||
RCC_BKP,
|
||||
RCC_I2C1,
|
||||
RCC_I2C2,
|
||||
RCC_CRC,
|
||||
RCC_FLITF,
|
||||
RCC_SRAM,
|
||||
RCC_USB,
|
||||
#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
|
||||
RCC_GPIOE,
|
||||
RCC_GPIOF,
|
||||
RCC_GPIOG,
|
||||
RCC_UART4,
|
||||
RCC_UART5,
|
||||
RCC_TIMER5,
|
||||
RCC_TIMER6,
|
||||
RCC_TIMER7,
|
||||
RCC_TIMER8,
|
||||
RCC_FSMC,
|
||||
RCC_DAC,
|
||||
RCC_DMA2,
|
||||
RCC_SDIO,
|
||||
RCC_SPI3,
|
||||
#endif
|
||||
#ifdef STM32_XL_DENSITY
|
||||
RCC_TIMER9,
|
||||
RCC_TIMER10,
|
||||
RCC_TIMER11,
|
||||
RCC_TIMER12,
|
||||
RCC_TIMER13,
|
||||
RCC_TIMER14,
|
||||
#endif
|
||||
} rcc_clk_id;
|
||||
|
||||
void rcc_clk_init(rcc_sysclk_src sysclk_src,
|
||||
rcc_pllsrc pll_src,
|
||||
rcc_pll_multiplier pll_mul);
|
||||
void rcc_clk_enable(rcc_clk_id device);
|
||||
void rcc_reset_dev(rcc_clk_id device);
|
||||
|
||||
typedef enum rcc_clk_domain {
|
||||
RCC_APB1,
|
||||
RCC_APB2,
|
||||
RCC_AHB
|
||||
} rcc_clk_domain;
|
||||
|
||||
rcc_clk_domain rcc_dev_clk(rcc_clk_id device);
|
||||
|
||||
/**
|
||||
* Prescaler identifiers
|
||||
* @see rcc_set_prescaler()
|
||||
*/
|
||||
typedef enum rcc_prescaler {
|
||||
RCC_PRESCALER_AHB,
|
||||
RCC_PRESCALER_APB1,
|
||||
RCC_PRESCALER_APB2,
|
||||
RCC_PRESCALER_USB,
|
||||
RCC_PRESCALER_ADC
|
||||
} rcc_prescaler;
|
||||
|
||||
/**
|
||||
* ADC prescaler dividers
|
||||
* @see rcc_set_prescaler()
|
||||
*/
|
||||
typedef enum rcc_adc_divider {
|
||||
RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
|
||||
RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
|
||||
RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
|
||||
RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
|
||||
} rcc_adc_divider;
|
||||
|
||||
/**
|
||||
* APB1 prescaler dividers
|
||||
* @see rcc_set_prescaler()
|
||||
*/
|
||||
typedef enum rcc_apb1_divider {
|
||||
RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
|
||||
RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
|
||||
RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
|
||||
RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
|
||||
RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
|
||||
} rcc_apb1_divider;
|
||||
|
||||
/**
|
||||
* APB2 prescaler dividers
|
||||
* @see rcc_set_prescaler()
|
||||
*/
|
||||
typedef enum rcc_apb2_divider {
|
||||
RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
|
||||
RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
|
||||
RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
|
||||
RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
|
||||
RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
|
||||
} rcc_apb2_divider;
|
||||
|
||||
/**
|
||||
* AHB prescaler dividers
|
||||
* @see rcc_set_prescaler()
|
||||
*/
|
||||
typedef enum rcc_ahb_divider {
|
||||
RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
|
||||
RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
|
||||
RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
|
||||
RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
|
||||
RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
|
||||
RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
|
||||
RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
|
||||
RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
|
||||
RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
|
||||
RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
|
||||
} rcc_ahb_divider;
|
||||
|
||||
void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
|
||||
|
||||
/**
|
||||
* @brief Start the low speed internal oscillatior
|
||||
*/
|
||||
static inline void rcc_start_lsi(void) {
|
||||
*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
|
||||
while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the low speed internal oscillatior
|
||||
*/
|
||||
static inline void rcc_stop_lsi(void) {
|
||||
*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the low speed external oscillatior
|
||||
*/
|
||||
static inline void rcc_start_lse(void) {
|
||||
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
|
||||
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
|
||||
while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the low speed external oscillatior
|
||||
*/
|
||||
static inline void rcc_stop_lse(void) {
|
||||
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the high speed external oscillatior
|
||||
*/
|
||||
static inline void rcc_start_hse(void) {
|
||||
// *bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
|
||||
while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the high speed external oscillatior
|
||||
*/
|
||||
static inline void rcc_stop_hse(void) {
|
||||
// *bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
# Standard things
|
||||
sp := $(sp).x
|
||||
dirstack_$(sp) := $(d)
|
||||
d := $(dir)
|
||||
BUILDDIRS += $(BUILD_PATH)/$(d)
|
||||
|
||||
# Local flags
|
||||
CFLAGS_$(d) := $(WIRISH_INCLUDES) $(LIBMAPLE_INCLUDES)
|
||||
|
||||
# Local rules and targets
|
||||
cSRCS_$(d) := utility/rtc_util.c
|
||||
|
||||
cppSRCS_$(d) := RTClock.cpp
|
||||
|
||||
cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%)
|
||||
cppFILES_$(d) := $(cppSRCS_$(d):%=$(d)/%)
|
||||
|
||||
OBJS_$(d) := $(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) \
|
||||
$(cppFILES_$(d):%.cpp=$(BUILD_PATH)/%.o)
|
||||
DEPS_$(d) := $(OBJS_$(d):%.o=%.d)
|
||||
|
||||
$(OBJS_$(d)): TGT_CFLAGS := $(CFLAGS_$(d))
|
||||
|
||||
TGT_BIN += $(OBJS_$(d))
|
||||
|
||||
# Standard things
|
||||
-include $(DEPS_$(d))
|
||||
d := $(dirstack_$(sp))
|
||||
sp := $(basename $(sp))
|
||||
|
|
@ -91,7 +91,8 @@ recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={b
|
|||
recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{build.path}/{archive_file}" "{object_file}"
|
||||
|
||||
## Combine gc-sections, archives, and objects
|
||||
recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group {object_files} "{build.path}/{archive_file}" -Wl,--end-group
|
||||
#recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group {object_files} "{build.path}/{archive_file}" -Wl,--end-group
|
||||
recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group {object_files} -Wl,--whole-archive "{build.path}/{archive_file}" -Wl,--no-whole-archive -Wl,--end-group
|
||||
|
||||
## Create eeprom
|
||||
recipe.objcopy.eep.pattern=
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ extern "C"{
|
|||
#endif
|
||||
|
||||
#include <libmaple/libmaple_types.h>
|
||||
#include <libmaple/bitband.h>
|
||||
|
||||
/*
|
||||
* Register map
|
||||
|
|
@ -356,6 +357,7 @@ typedef struct rcc_reg_map {
|
|||
#define RCC_BDCR_RTCSEL (0x3 << 8)
|
||||
#define RCC_BDCR_RTCSEL_NONE (0x0 << 8)
|
||||
#define RCC_BDCR_RTCSEL_LSE (0x1 << 8)
|
||||
#define RCC_BDCR_RTCSEL_LSI (0x2 << 8) // added to support RTClock
|
||||
#define RCC_BDCR_RTCSEL_HSE (0x3 << 8)
|
||||
#define RCC_BDCR_LSEBYP (1U << RCC_BDCR_LSEBYP_BIT)
|
||||
#define RCC_BDCR_LSERDY (1U << RCC_BDCR_LSERDY_BIT)
|
||||
|
|
@ -522,6 +524,14 @@ typedef enum rcc_ahb_divider {
|
|||
RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
|
||||
} rcc_ahb_divider;
|
||||
|
||||
/**
|
||||
* @brief Start the low speed internal oscillatior
|
||||
*/
|
||||
static inline void rcc_start_lsi(void) {
|
||||
*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
|
||||
while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STM32F1 clock sources.
|
||||
*/
|
||||
|
|
@ -563,6 +573,14 @@ typedef enum rcc_pll_multiplier {
|
|||
} rcc_pll_multiplier;
|
||||
|
||||
/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */
|
||||
/**
|
||||
* @brief Start the low speed external oscillatior
|
||||
*/
|
||||
static inline void rcc_start_lse(void) {
|
||||
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
|
||||
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
|
||||
while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief STM32F1 PLL configuration values.
|
||||
|
|
@ -576,6 +594,10 @@ typedef struct stm32f1_rcc_pll_data {
|
|||
/*
|
||||
* Deprecated bits.
|
||||
*/
|
||||
static inline void rcc_start_hse(void) { // Added to support RTClock
|
||||
// *bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
|
||||
while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deprecated; STM32F1 only.
|
||||
|
|
|
|||
Loading…
Reference in New Issue