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Updated HAL library with the latest files exported from the Cube. Also enabled as many interfaces as possible. Note CAN bus interferes with USB, so has been commented out in stm32f1xx_hal_conf.h

This commit is contained in:
Roger Clark 2016-06-21 15:18:28 +10:00
parent d62cf1a35a
commit 772174fed1
55 changed files with 100371 additions and 42797 deletions
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2
STM32F1/libraries/HAL/examples/HAL_GPIO/HAL_GPIO.ino
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@ -25,7 +25,7 @@ void setup()
void loop()
{
// Serial.println(c++);
Serial.println(c++);
HAL_GPIO_WritePin(LED_PORT,LED_PIN,GPIO_PIN_SET);

248
STM32F1/libraries/HAL/src/Legacy/stm32_hal_legacy.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -129,7 +129,6 @@
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@ -144,6 +143,62 @@
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
@ -384,6 +439,7 @@
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
* @}
*/
@ -424,8 +480,14 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
#endif
/**
* @}
*/
@ -482,6 +544,11 @@
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
#define NAND_AddressTypedef NAND_AddressTypeDef
#define __ARRAY_ADDRESS ARRAY_ADDRESS
@ -545,6 +612,9 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
*/
@ -640,7 +710,7 @@
*/
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
@ -658,7 +728,7 @@
* @}
*/
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
@ -842,11 +912,85 @@
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
/**
* @}
*/
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -904,7 +1048,10 @@
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
@ -929,8 +1076,10 @@
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
/**
@ -1031,7 +1180,7 @@
*/
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
@ -1406,10 +1555,28 @@
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
@ -2453,7 +2620,7 @@
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
@ -2567,6 +2734,34 @@
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2856,21 +3051,7 @@
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3))
#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))
#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
((STATE) == TIM_OUTPUTNSTATE_ENABLE))
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
((STATE) == TIM_OUTPUTSTATE_ENABLE))
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/
@ -2910,14 +3091,15 @@
#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
#define SAI_STREOMODE SAI_STEREOMODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
/**
* @}
*/

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STM32F1/libraries/HAL/src/stm32f1xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
* @version V4.0.2
* @date 18-December-2015
* @version V4.1.0
* @date 29-April-2016
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -108,16 +108,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.0.2
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
* @brief CMSIS Device version number
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/**
* @}

4
STM32F1/libraries/HAL/src/stm32f1xx_hal.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_adc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_adc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention

56
STM32F1/libraries/HAL/src/stm32f1xx_hal_conf.h
View File

@ -51,36 +51,36 @@
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
//#define HAL_CAN_MODULE_ENABLED
//#define HAL_CEC_MODULE_ENABLED
//#define HAL_CORTEX_MODULE_ENABLED
//#define HAL_CRC_MODULE_ENABLED
//#define HAL_DAC_MODULE_ENABLED
//#define HAL_DMA_MODULE_ENABLED
//#define HAL_ETH_MODULE_ENABLED
//#define HAL_FLASH_MODULE_ENABLED
/*#define HAL_CAN_MODULE_ENABLED*/
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_CORTEX_MODULE_ENABLED */
#define HAL_CRC_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
/*#define HAL_DMA_MODULE_ENABLED */
/*#define HAL_ETH_MODULE_ENABLED */
/*#define HAL_FLASH_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
//#define HAL_I2S_MODULE_ENABLED
//#define HAL_IRDA_MODULE_ENABLED
//#define HAL_IWDG_MODULE_ENABLED
//#define HAL_NOR_MODULE_ENABLED
//#define HAL_NAND_MODULE_ENABLED
//#define HAL_PCCARD_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
//#define HAL_HCD_MODULE_ENABLED
//#define HAL_PWR_MODULE_ENABLED
//#define HAL_RCC_MODULE_ENABLED
//#define HAL_RTC_MODULE_ENABLED
//#define HAL_SD_MODULE_ENABLED
//#define HAL_SDRAM_MODULE_ENABLED
//#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_PWR_MODULE_ENABLED */
/*#define HAL_RCC_MODULE_ENABLED */
#define HAL_RTC_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
//#define HAL_SRAM_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
//#define HAL_USART_MODULE_ENABLED
//#define HAL_WWDG_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
#define HAL_WWDG_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
@ -122,7 +122,7 @@
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
@ -163,8 +163,8 @@
/* Section 2: PHY configuration section */
/* DP83848 PHY Address*/
#define DP83848_PHY_ADDRESS 0x01
/* DP83848_PHY_ADDRESS Address*/
#define DP83848_PHY_ADDRESS 0x01U
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
/* PHY Configuration delay */

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_cortex.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_cortex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_def.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_def.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************

12
STM32F1/libraries/HAL/src/stm32f1xx_hal_dma.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_dma.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@ -350,6 +350,14 @@ typedef struct __DMA_HandleTypeDef
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__: DMA handle
*
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_dma_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_flash.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_flash_ex.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Extended FLASH HAL module driver.
*
* This file provides firmware functions to manage the following

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_flash_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_gpio.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_gpio.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_gpio.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_gpio.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_gpio_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_i2c.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_i2c.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_i2c.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_i2c.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_pcd.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Extended PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_pcd_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of Extended PCD HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pwr.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief PWR HAL module driver.
*
* This file provides firmware functions to manage the following

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_pwr.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_pwr.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention

372
STM32F1/libraries/HAL/src/stm32f1xx_hal_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -18,8 +18,8 @@
After reset the device is running from Internal High Speed oscillator
(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
and all peripherals are off except internal SRAM, Flash and JTAG.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
all peripherals mapped on these busses are running at HSI speed.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
all peripherals mapped on these buses are running at HSI speed.
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
@ -27,7 +27,7 @@
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers
(+) Configure the AHB and APB buses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals whose clocks are not
derived from the System clock (I2S, RTC, ADC, USB OTG FS)
@ -75,7 +75,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
@ -96,6 +96,10 @@
/** @defgroup RCC_Private_Constants RCC Private Constants
* @{
*/
/* Bits position in in the CFGR register */
#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
/**
* @}
*/
@ -116,7 +120,6 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
@ -184,7 +187,13 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
(#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
@endverbatim
* @{
*/
/*
Additional consideration on the SYSCLK based on Latency settings:
+-----------------------------------------------+
| Latency | SYSCLK clock frequency (MHz) |
|---------------|-------------------------------|
@ -194,8 +203,6 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
|---------------|-------------------------------|
|2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
+-----------------------------------------------+
@endverbatim
* @{
*/
/**
@ -206,9 +213,9 @@ const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4,
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS and MCO1 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @note This function does not modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval None
*/
void HAL_RCC_DeInit(void)
@ -235,6 +242,9 @@ void HAL_RCC_DeInit(void)
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HSI_VALUE;
}
/**
@ -244,6 +254,12 @@ void HAL_RCC_DeInit(void)
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
* supported by this macro. User should request a transition to LSE Off
* first and then LSE On or LSE Bypass.
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@ -271,21 +287,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
@ -310,7 +311,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
@ -409,7 +410,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
return HAL_TIMEOUT;
}
}
/* To have a fully stabilized clock in the specified range, a software temporization of 1ms
/* To have a fully stabilized clock in the specified range, a software delay of 1ms
should be added.*/
HAL_Delay(1);
}
@ -436,39 +437,24 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@ -694,12 +680,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
* startup from Reset, wake-up from STOP and STANDBY mode, or in case
* start-up from Reset, wake-up from STOP and STANDBY mode, or in case
* of failure of the HSE used directly or indirectly as system clock
* (if the Clock Security System CSS is enabled).
*
* @note A switch from one clock source to another occurs only if the target
* clock source is ready (clock stable after startup delay or PLL locked).
* clock source is ready (clock stable after start-up delay or PLL locked).
* If a clock source which is not yet ready is selected, the switch will
* occur when the clock source will be ready.
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
@ -720,7 +706,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
(HCLK) of the device. */
#if defined(FLASH_ACR_LATENCY)
/* Increasing the CPU frequency */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
@ -732,164 +718,88 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
return HAL_ERROR;
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick */
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
#if defined(FLASH_ACR_LATENCY)
}
/* Decreasing the CPU frequency */
else
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick */
tickstart = HAL_GetTick();
/*------------------------- SYSCLK Configuration -------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_ERROR;
return HAL_TIMEOUT;
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_ERROR;
return HAL_TIMEOUT;
}
}
/* HSI is selected as System Clock Source */
else
}
else
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_ERROR;
return HAL_TIMEOUT;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick */
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
}
}
#if defined(FLASH_ACR_LATENCY)
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
@ -899,9 +809,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
return HAL_ERROR;
}
}
}
#endif /* FLASH_ACR_LATENCY */
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
@ -916,6 +826,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@ -926,8 +839,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @}
*/
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
* @brief RCC clocks control functions
*
@verbatim
===============================================================================
@ -946,26 +859,26 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
* @note MCO pin should be configured in alternate function mode.
* @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO Clock source to output on MCO1 pin(PA8).
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
* @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected
* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected
* @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
@if STM32F105xC
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
@endif
@if STM32F107xC
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
@endif
* @param RCC_MCODiv specifies the MCO DIV.
* This parameter can be one of the following values:
@ -981,14 +894,15 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
/* MCO Clock Enable */
/* Configure the MCO1 pin in alternate function mode */
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
gpio.Pull = GPIO_NOPULL;
gpio.Pin = MCO1_PIN;
/* MCO1 Clock Enable */
MCO1_CLK_ENABLE();
/* Configure the MCO1 pin in alternate function mode */
gpio.Pin = MCO1_PIN;
gpio.Mode = GPIO_MODE_AF_PP;
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
gpio.Pull = GPIO_NOPULL;
HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
/* Configure the MCO clock source */
@ -1040,7 +954,7 @@ void HAL_RCC_DisableCSS(void)
* value for HSE crystal.
*
* @note This function can be used by the user application to compute the
* baudrate for the communication peripherals or configure other parameters.
* baud-rate for the communication peripherals or configure other parameters.
*
* @note Each time SYSCLK changes, this function must be called to update the
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
@ -1143,7 +1057,6 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
return SystemCoreClock;
}
@ -1156,7 +1069,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
}
/**
@ -1168,7 +1081,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
}
/**
@ -1243,6 +1156,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{

92
STM32F1/libraries/HAL/src/stm32f1xx_hal_rcc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@ -68,11 +68,10 @@
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */
#define LSI_VALUE ((uint32_t)40000) /* 40kHz */
/**
* @}
*/
@ -246,23 +245,23 @@ typedef struct
This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
} RCC_PLLInitTypeDef;
/**
/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */
uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
This parameter can be a value of @ref RCC_System_Clock_Source */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_AHB_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
} RCC_ClkInitTypeDef;
@ -323,8 +322,8 @@ typedef struct
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
@ -421,8 +420,8 @@ typedef struct
* @{
*/
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
/**
* @}
@ -451,12 +450,12 @@ typedef struct
/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
/**
* @}
*/
@ -477,7 +476,6 @@ typedef struct
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_RMVF_BIT_NUMBER)) /*!< Remove reset flag */
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
@ -803,7 +801,7 @@ typedef struct
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
@ -831,7 +829,7 @@ typedef struct
* @brief Force or release APB2 peripheral reset.
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
@ -928,7 +926,7 @@ typedef struct
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the Clock security system(CSS)
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* @param __STATE__ specifies the new state of the HSE.
@ -1039,25 +1037,25 @@ typedef struct
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
* This parameter can be one of the following values:
* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
* @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
* @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
@if STM32F105xC
* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
@elseif STM32F107xC
* @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
@else
* @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 (*)
* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 (*)
* @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
* @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
* @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
* @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
* @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
* @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
* @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
* @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
* @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
* @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
* @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
* @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
* @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
* @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
@endif
* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
* @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
* @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
*
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
@ -1081,14 +1079,14 @@ typedef struct
/**
* @brief Macro to configure the system clock source.
* @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
* @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
*/
#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
@ -1111,7 +1109,7 @@ typedef struct
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
@ -1128,7 +1126,7 @@ typedef struct
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
@ -1247,7 +1245,7 @@ typedef struct
* @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
@endif
*/
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
/** @brief Clear the RCC's interrupt pending bits.
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
@ -1309,9 +1307,9 @@ typedef struct
@endif
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
* @arg @ref RCC_FLAG_PINRST Pin reset.
* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
* @arg @ref RCC_FLAG_SFTRST Software reset.
* @arg @ref RCC_FLAG_PINRST Pin reset.
* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
* @arg @ref RCC_FLAG_SFTRST Software reset.
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
@ -1319,7 +1317,7 @@ typedef struct
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
/**
* @}

15
STM32F1/libraries/HAL/src/stm32f1xx_hal_rcc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Extended RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@ -92,7 +92,7 @@
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
select the RTC clock source; in this case the Backup domain will be reset in
order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) and RCC_BDCR register are set to their reset values.
the backup registers) are set to their reset values.
@endverbatim
* @{
@ -148,8 +148,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@ -160,7 +161,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
RCC->BDCR = temp_reg;
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
{
/* Get timeout */
tickstart = HAL_GetTick();
@ -174,8 +175,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*------------------------------ ADC clock Configuration ------------------*/

6
STM32F1/libraries/HAL/src/stm32f1xx_hal_rcc_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_rcc_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@ -1402,7 +1402,7 @@ typedef struct
* @brief Force or release AHB peripheral reset.
* @{
*/
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
#if defined(STM32F107xC)
#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))

82
STM32F1/libraries/HAL/src/stm32f1xx_hal_spi.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_spi.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief SPI HAL module driver.
*
* This file provides firmware functions to manage the following
@ -53,7 +53,38 @@
(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
[..]
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*
Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
the following table resume the max SPI frequency reached with data size 8bits/16bits,
according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
@ -108,43 +139,16 @@
| | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 |
+--------------------------------------------------------------------------------------------------+
@note The max SPI frequency depend on SPI data size (8bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@note
(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
note:
The max SPI frequency depend on SPI data size (8bits, 16bits),
SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
note:
TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_spi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_spi.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_spi_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_spi_ex.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Extended SPI HAL module driver.
*
* This file provides firmware functions to manage the following

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_tim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief TIM HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_tim.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_tim_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim_ex.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer Extended peripheral:

4
STM32F1/libraries/HAL/src/stm32f1xx_hal_tim_ex.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention

38
STM32F1/libraries/HAL/src/stm32f1xx_hal_uart.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_uart.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@ -209,21 +209,7 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
(++) Baud Rate
(++) Word Length
(++) Stop Bit
(++) Parity: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
the possible UART frame formats are as listed in the following table:
(+++) +-------------------------------------------------------------+
(+++) | M bit | PCE bit | UART frame |
(+++) |---------------------|---------------------------------------|
(+++) | 0 | 0 | | SB | 8 bit data | STB | |
(+++) |---------|-----------|---------------------------------------|
(+++) | 0 | 1 | | SB | 7 bit data | PB | STB | |
(+++) |---------|-----------|---------------------------------------|
(+++) | 1 | 0 | | SB | 9 bit data | STB | |
(+++) |---------|-----------|---------------------------------------|
(+++) | 1 | 1 | | SB | 8 bit data | PB | STB | |
(+++) +-------------------------------------------------------------+
(++) Parity
(++) Hardware flow control
(++) Receiver/transmitter modes
[..]
@ -237,6 +223,24 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart,
* @{
*/
/*
Additionnal remark: If the parity is enabled, then the MSB bit of the data written
in the data register is transmitted but is changed by the parity bit.
Depending on the frame length defined by the M bit (8-bits or 9-bits),
the possible UART frame formats are as listed in the following table:
+-------------------------------------------------------------+
| M bit | PCE bit | UART frame |
|---------------------|---------------------------------------|
| 0 | 0 | | SB | 8 bit data | STB | |
|---------|-----------|---------------------------------------|
| 0 | 1 | | SB | 7 bit data | PB | STB | |
|---------|-----------|---------------------------------------|
| 1 | 0 | | SB | 9 bit data | STB | |
|---------|-----------|---------------------------------------|
| 1 | 1 | | SB | 8 bit data | PB | STB | |
+-------------------------------------------------------------+
*/
/**
* @brief Initializes the UART mode according to the specified parameters in
* the UART_InitTypeDef and create the associated handle.

11
STM32F1/libraries/HAL/src/stm32f1xx_hal_uart.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_uart.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@ -591,8 +591,11 @@ do{ \
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_)))
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
/* UART BRR = mantissa + overflow + fraction
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
((LENGTH) == UART_WORDLENGTH_9B))
#define IS_UART_LIN_WORD_LENGTH(LENGTH) ((LENGTH) == UART_WORDLENGTH_8B)

4
STM32F1/libraries/HAL/src/stm32f1xx_ll_usb.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_ll_usb.c
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following

4
STM32F1/libraries/HAL/src/stm32f1xx_ll_usb.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_ll_usb.h
* @author MCD Application Team
* @version V1.0.3
* @date 11-January-2016
* @version V1.0.4
* @date 29-April-2016
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention

8
STM32F1/libraries/HAL/src/system_stm32f1xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @version V4.0.2
* @date 18-December-2015
* @version V4.1.0
* @date 29-April-2016
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -67,6 +67,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}