noisymime
/
Arduino_STM32
mirror of https://github.com/noisymime/Arduino_STM32.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #1 from rogerclarkmelbourne/master 

update
This commit is contained in:
arpruss 2018-06-13 10:36:53 -05:00 committed by GitHub
parent 18d1654195 4db3994d1c
commit 823744fb6c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
290 changed files with 1086 additions and 32526 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
STM32F1/boards.txt
View File

@ -38,13 +38,13 @@ mapleMini.menu.bootloader_version.bootloader20.upload.maximum_data_size=20480
mapleMini.menu.bootloader_version.bootloader20.upload.altID=2
#-- CPU Clock frequency
mapleMini.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
mapleMini.menu.cpu_speed.speed_72mhz=72MHz (Normal)
mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
mapleMini.menu.cpu_speed.speed_48mhz=48MHz (Slow - with USB)
mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
mapleMini.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
mapleMini.menu.cpu_speed.speed_128mhz=Overclocked 128MHz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
mapleMini.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
#-- Optimizations

53
STM32F1/cores/maple/HardwareSerial.cpp
View File

@ -37,59 +37,6 @@
#include <libmaple/timer.h>
#include <libmaple/usart.h>
#if 0
#define DEFINE_HWSERIAL(name, n) \
HardwareSerial name(USART##n, \
BOARD_USART##n##_TX_PIN, \
BOARD_USART##n##_RX_PIN)
#define DEFINE_HWSERIAL_UART(name, n) \
HardwareSerial name(UART##n, \
BOARD_USART##n##_TX_PIN, \
BOARD_USART##n##_RX_PIN)
#ifdef SERIAL_USB
#if BOARD_HAVE_USART1
DEFINE_HWSERIAL(Serial1, 1);
#endif
#if BOARD_HAVE_USART2
DEFINE_HWSERIAL(Serial2, 2);
#endif
#if BOARD_HAVE_USART3
DEFINE_HWSERIAL(Serial3, 3);
#endif
#if BOARD_HAVE_UART4
DEFINE_HWSERIAL_UART(Serial4, 4);
#endif
#if BOARD_HAVE_UART5
DEFINE_HWSERIAL_UART(Serial5, 5);
#endif
#if BOARD_HAVE_USART6
DEFINE_HWSERIAL_UART(Serial6, 6);
#endif
#else
#if BOARD_HAVE_USART1
DEFINE_HWSERIAL(Serial, 1);
#endif
#if BOARD_HAVE_USART2
DEFINE_HWSERIAL(Serial1, 2);
#endif
#if BOARD_HAVE_USART3
DEFINE_HWSERIAL(Serial2, 3);
#endif
#if BOARD_HAVE_UART4
DEFINE_HWSERIAL_UART(Serial3, 4);
#endif
#if BOARD_HAVE_UART5
DEFINE_HWSERIAL_UART(Serial4, 5);
#endif
#if BOARD_HAVE_USART6
DEFINE_HWSERIAL_UART(Serial5, 6);
#endif
#endif
#endif
HardwareSerial::HardwareSerial(usart_dev *usart_device,
uint8 tx_pin,
uint8 rx_pin) {

4
STM32F1/cores/maple/libmaple/adc_f1.c
View File

@ -72,7 +72,7 @@ adc_dev *ADC3 = &adc3;
adc irq routine.
Added by bubulindo.
*/
void __irq_adc() {
__weak void __irq_adc() {
//get status
uint32 adc_sr = ADC1->regs->SR;
//End Of Conversion
@ -107,7 +107,7 @@ void __irq_adc() {
added by bubulindo
*/
#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
void __irq_adc3() {
__weak void __irq_adc3() {
//get status
uint32 adc_sr = ADC3->regs->SR;
//End Of Conversion

22
STM32F1/cores/maple/libmaple/dma_f1.c
View File

@ -360,48 +360,48 @@ void dma_setup_transfer(dma_dev *dev,
* IRQ handlers
*/
void __irq_dma1_channel1(void) {
__weak void __irq_dma1_channel1(void) {
dma_irq_handler(DMA1, DMA_CH1);
}
void __irq_dma1_channel2(void) {
__weak void __irq_dma1_channel2(void) {
dma_irq_handler(DMA1, DMA_CH2);
}
void __irq_dma1_channel3(void) {
__weak void __irq_dma1_channel3(void) {
dma_irq_handler(DMA1, DMA_CH3);
}
void __irq_dma1_channel4(void) {
__weak void __irq_dma1_channel4(void) {
dma_irq_handler(DMA1, DMA_CH4);
}
void __irq_dma1_channel5(void) {
__weak void __irq_dma1_channel5(void) {
dma_irq_handler(DMA1, DMA_CH5);
}
void __irq_dma1_channel6(void) {
__weak void __irq_dma1_channel6(void) {
dma_irq_handler(DMA1, DMA_CH6);
}
void __irq_dma1_channel7(void) {
__weak void __irq_dma1_channel7(void) {
dma_irq_handler(DMA1, DMA_CH7);
}
#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
void __irq_dma2_channel1(void) {
__weak void __irq_dma2_channel1(void) {
dma_irq_handler(DMA2, DMA_CH1);
}
void __irq_dma2_channel2(void) {
__weak void __irq_dma2_channel2(void) {
dma_irq_handler(DMA2, DMA_CH2);
}
void __irq_dma2_channel3(void) {
__weak void __irq_dma2_channel3(void) {
dma_irq_handler(DMA2, DMA_CH3);
}
void __irq_dma2_channel4_5(void) {
__weak void __irq_dma2_channel4_5(void) {
if ((DMA2_BASE->CCR4 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF4)) {
dma_irq_handler(DMA2, DMA_CH4);
}

1
STM32F1/cores/maple/libmaple/exc.S
View File

@ -41,7 +41,6 @@
# SP--> r0
.text
.globl __exc_hardfault
.globl __exc_nmi
.globl __exc_hardfault
.globl __exc_memmanage

14
STM32F1/cores/maple/libmaple/exti.c
View File

@ -212,31 +212,31 @@ void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port) {
* Interrupt handlers
*/
void __irq_exti0(void) {
__weak void __irq_exti0(void) {
dispatch_single_exti(EXTI0);
}
void __irq_exti1(void) {
__weak void __irq_exti1(void) {
dispatch_single_exti(EXTI1);
}
void __irq_exti2(void) {
__weak void __irq_exti2(void) {
dispatch_single_exti(EXTI2);
}
void __irq_exti3(void) {
__weak void __irq_exti3(void) {
dispatch_single_exti(EXTI3);
}
void __irq_exti4(void) {
__weak void __irq_exti4(void) {
dispatch_single_exti(EXTI4);
}
void __irq_exti9_5(void) {
__weak void __irq_exti9_5(void) {
dispatch_extis(5, 9);
}
void __irq_exti15_10(void) {
__weak void __irq_exti15_10(void) {
dispatch_extis(10, 15);
}

8
STM32F1/cores/maple/libmaple/i2c_f1.c
View File

@ -76,19 +76,19 @@ void i2c_master_release_bus(const i2c_dev *dev) {
* IRQ handlers
*/
void __irq_i2c1_ev(void) {
__weak void __irq_i2c1_ev(void) {
_i2c_irq_handler(I2C1);
}
void __irq_i2c2_ev(void) {
__weak void __irq_i2c2_ev(void) {
_i2c_irq_handler(I2C2);
}
void __irq_i2c1_er(void) {
__weak void __irq_i2c1_er(void) {
_i2c_irq_error_handler(I2C1);
}
void __irq_i2c2_er(void) {
__weak void __irq_i2c2_er(void) {
_i2c_irq_error_handler(I2C2);
}

6
STM32F1/cores/maple/libmaple/rcc_f1.c
View File

@ -134,6 +134,12 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
cfgr |= pll_cfg->pllsrc | pll_mul;
#ifdef XTAL16M
// 16MHz crystal (HSE)
// in this case we additionally set the Bit 17 (PLLXTPRE=1) => then HSE clock is divided by 2 before PLL entry
cfgr |= RCC_CFGR_PLLXTPRE;
#endif
RCC_BASE->CFGR = cfgr;
}

268
STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S
View File

@ -76,9 +76,9 @@ __default_handler:
.weak __exc_pendsv
.globl __exc_pendsv
.set __exc_pendsv, __default_handler
.weak __exc_systick
.globl __exc_systick
.set __exc_systick, __default_handler
// .weak __exc_systick // __exc_systick() defined in STM32F1/cores/maple/libmaple/systick.c
// .globl __exc_systick
// .set __exc_systick, __default_handler
.weak __irq_wwdg
.globl __irq_wwdg
.set __irq_wwdg, __default_handler
@ -97,110 +97,110 @@ __default_handler:
.weak __irq_rcc
.globl __irq_rcc
.set __irq_rcc, __default_handler
.weak __irq_exti0
.globl __irq_exti0
.set __irq_exti0, __default_handler
.weak __irq_exti1
.globl __irq_exti1
.set __irq_exti1, __default_handler
.weak __irq_exti2
.globl __irq_exti2
.set __irq_exti2, __default_handler
.weak __irq_exti3
.globl __irq_exti3
.set __irq_exti3, __default_handler
.weak __irq_exti4
.globl __irq_exti4
.set __irq_exti4, __default_handler
.weak __irq_dma1_channel1
.globl __irq_dma1_channel1
.set __irq_dma1_channel1, __default_handler
.weak __irq_dma1_channel2
.globl __irq_dma1_channel2
.set __irq_dma1_channel2, __default_handler
.weak __irq_dma1_channel3
.globl __irq_dma1_channel3
.set __irq_dma1_channel3, __default_handler
.weak __irq_dma1_channel4
.globl __irq_dma1_channel4
.set __irq_dma1_channel4, __default_handler
.weak __irq_dma1_channel5
.globl __irq_dma1_channel5
.set __irq_dma1_channel5, __default_handler
.weak __irq_dma1_channel6
.globl __irq_dma1_channel6
.set __irq_dma1_channel6, __default_handler
.weak __irq_dma1_channel7
.globl __irq_dma1_channel7
.set __irq_dma1_channel7, __default_handler
.weak __irq_adc
.globl __irq_adc
.set __irq_adc, __default_handler
// .weak __irq_exti0 // __irq_exti0() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti0
// .set __irq_exti0, __default_handler
// .weak __irq_exti1 // __irq_exti1() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti1
// .set __irq_exti1, __default_handler
// .weak __irq_exti2 // __irq_exti2() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti2
// .set __irq_exti2, __default_handler
// .weak __irq_exti3 // __irq_exti3() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti3
// .set __irq_exti3, __default_handler
// .weak __irq_exti4 // __irq_exti4() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti4
// .set __irq_exti4, __default_handler
// .weak __irq_dma1_channel1 // __irq_dma1_channel1() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel1
// .set __irq_dma1_channel1, __default_handler
// .weak __irq_dma1_channel2 // __irq_dma1_channel2() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel2
// .set __irq_dma1_channel2, __default_handler
// .weak __irq_dma1_channel3 // __irq_dma1_channel3() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel3
// .set __irq_dma1_channel3, __default_handler
// .weak __irq_dma1_channel4 // __irq_dma1_channel4() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel4
// .set __irq_dma1_channel4, __default_handler
// .weak __irq_dma1_channel5 // __irq_dma1_channel5() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel5
// .set __irq_dma1_channel5, __default_handler
// .weak __irq_dma1_channel6 // __irq_dma1_channel6() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel6
// .set __irq_dma1_channel6, __default_handler
// .weak __irq_dma1_channel7 // __irq_dma1_channel7() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma1_channel7
// .set __irq_dma1_channel7, __default_handler
// .weak __irq_adc // __irq_adc() defined in STM32F1/cores/maple/libmaple/adc_f1.c
// .globl __irq_adc
// .set __irq_adc, __default_handler
.weak __irq_usb_hp_can_tx
.globl __irq_usb_hp_can_tx
.set __irq_usb_hp_can_tx, __default_handler
.weak __irq_usb_lp_can_rx0
.globl __irq_usb_lp_can_rx0
.set __irq_usb_lp_can_rx0, __default_handler
// .weak __irq_usb_lp_can_rx0 // __irq_usb_lp_can_rx0() defined in STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
// .globl __irq_usb_lp_can_rx0
// .set __irq_usb_lp_can_rx0, __default_handler
.weak __irq_can_rx1
.globl __irq_can_rx1
.set __irq_can_rx1, __default_handler
.weak __irq_can_sce
.globl __irq_can_sce
.set __irq_can_sce, __default_handler
.weak __irq_exti9_5
.globl __irq_exti9_5
.set __irq_exti9_5, __default_handler
.weak __irq_tim1_brk
.globl __irq_tim1_brk
.set __irq_tim1_brk, __default_handler
.weak __irq_tim1_up
.globl __irq_tim1_up
.set __irq_tim1_up, __default_handler
.weak __irq_tim1_trg_com
.globl __irq_tim1_trg_com
.set __irq_tim1_trg_com, __default_handler
.weak __irq_tim1_cc
.globl __irq_tim1_cc
.set __irq_tim1_cc, __default_handler
.weakref __irq_tim2, __default_handler
.globl __irq_tim2
.weakref __irq_tim3, __default_handler
.globl __irq_tim3
.weakref __irq_tim4, __default_handler
.globl __irq_tim4
.weak __irq_i2c1_ev
.globl __irq_i2c1_ev
.set __irq_i2c1_ev, __default_handler
.weak __irq_i2c1_er
.globl __irq_i2c1_er
.set __irq_i2c1_er, __default_handler
.weak __irq_i2c2_ev
.globl __irq_i2c2_ev
.set __irq_i2c2_ev, __default_handler
.weak __irq_i2c2_er
.globl __irq_i2c2_er
.set __irq_i2c2_er, __default_handler
// .weak __irq_exti9_5 // __irq_exti9_5() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti9_5
// .set __irq_exti9_5, __default_handler
// .weak __irq_tim1_brk // __irq_tim1_brk() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim1_brk
// .set __irq_tim1_brk, __default_handler
// .weak __irq_tim1_up // __irq_tim1_up() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim1_up
// .set __irq_tim1_up, __default_handler
// .weak __irq_tim1_trg_com // __irq_tim1_trg_com() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim1_trg_com
// .set __irq_tim1_trg_com, __default_handler
// .weak __irq_tim1_cc // __irq_tim1_cc() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim1_cc
// .set __irq_tim1_cc, __default_handler
//
// .weakref __irq_tim2, __default_handler // __irq_tim2() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim2
// .weakref __irq_tim3, __default_handler // __irq_tim3() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim3
// .weakref __irq_tim4, __default_handler // __irq_tim4() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim4
//
// .weak __irq_i2c1_ev // __irq_i2c1_ev() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
// .globl __irq_i2c1_ev
// .set __irq_i2c1_ev, __default_handler
// .weak __irq_i2c1_er // __irq_i2c1_er() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
// .globl __irq_i2c1_er
// .set __irq_i2c1_er, __default_handler
// .weak __irq_i2c2_ev // __irq_i2c2_ev() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
// .globl __irq_i2c2_ev
// .set __irq_i2c2_ev, __default_handler
// .weak __irq_i2c2_er // __irq_i2c2_er() defined in STM32F1/cores/maple/libmaple/i2c_f1.c
// .globl __irq_i2c2_er
// .set __irq_i2c2_er, __default_handler
.weak __irq_spi1
.globl __irq_spi1
.set __irq_spi1, __default_handler
.weak __irq_spi2
.globl __irq_spi2
.set __irq_spi2, __default_handler
.weak __irq_usart1
.globl __irq_usart1
.set __irq_usart1, __default_handler
.weak __irq_usart2
.globl __irq_usart2
.set __irq_usart2, __default_handler
.weak __irq_usart3
.globl __irq_usart3
.set __irq_usart3, __default_handler
.weak __irq_exti15_10
.globl __irq_exti15_10
.set __irq_exti15_10, __default_handler
// .weak __irq_usart1 // __irq_usart1() defined in STM32F1/cores/maple/libmaple/usart_f1.c
// .globl __irq_usart1
// .set __irq_usart1, __default_handler
// .weak __irq_usart2 // __irq_usart2() defined in STM32F1/cores/maple/libmaple/usart_f1.c
// .globl __irq_usart2
// .set __irq_usart2, __default_handler
// .weak __irq_usart3 // __irq_usart3() defined in STM32F1/cores/maple/libmaple/usart_f1.c
// .globl __irq_usart3
// .set __irq_usart3, __default_handler
// .weak __irq_exti15_10 // __irq_exti15_10() defined in STM32F1/cores/maple/libmaple/exti.c
// .globl __irq_exti15_10
// .set __irq_exti15_10, __default_handler
.weak __irq_rtcalarm
.globl __irq_rtcalarm
.set __irq_rtcalarm, __default_handler
@ -208,55 +208,55 @@ __default_handler:
.globl __irq_usbwakeup
.set __irq_usbwakeup, __default_handler
#if defined (STM32_HIGH_DENSITY)
.weak __irq_tim8_brk
.globl __irq_tim8_brk
.set __irq_tim8_brk, __default_handler
.weak __irq_tim8_up
.globl __irq_tim8_up
.set __irq_tim8_up, __default_handler
.weak __irq_tim8_trg_com
.globl __irq_tim8_trg_com
.set __irq_tim8_trg_com, __default_handler
.weak __irq_tim8_cc
.globl __irq_tim8_cc
.set __irq_tim8_cc, __default_handler
.weak __irq_adc3
.globl __irq_adc3
.set __irq_adc3, __default_handler
// .weak __irq_tim8_brk // __irq_tim8_brk() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim8_brk
// .set __irq_tim8_brk, __default_handler
// .weak __irq_tim8_up // __irq_tim8_up() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim8_up
// .set __irq_tim8_up, __default_handler
// .weak __irq_tim8_trg_com // __irq_tim8_trg_com() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim8_trg_com
// .set __irq_tim8_trg_com, __default_handler
// .weak __irq_tim8_cc // __irq_tim8_cc() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim8_cc
// .set __irq_tim8_cc, __default_handler
// .weak __irq_adc3 // __irq_adc3() defined in STM32F1/cores/maple/libmaple/adc_f1.c
// .globl __irq_adc3
// .set __irq_adc3, __default_handler
.weak __irq_fsmc
.globl __irq_fsmc
.set __irq_fsmc, __default_handler
.weak __irq_sdio
.globl __irq_sdio
.set __irq_sdio, __default_handler
.weak __irq_tim5
.globl __irq_tim5
.set __irq_tim5, __default_handler
// .weak __irq_tim5 // __irq_tim5() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim5
// .set __irq_tim5, __default_handler
.weak __irq_spi3
.globl __irq_spi3
.set __irq_spi3, __default_handler
.weak __irq_uart4
.globl __irq_uart4
.set __irq_uart4, __default_handler
.weak __irq_uart5
.globl __irq_uart5
.set __irq_uart5, __default_handler
.weak __irq_tim6
.globl __irq_tim6
.set __irq_tim6, __default_handler
.weak __irq_tim7
.globl __irq_tim7
.set __irq_tim7, __default_handler
.weak __irq_dma2_channel1
.globl __irq_dma2_channel1
.set __irq_dma2_channel1, __default_handler
.weak __irq_dma2_channel2
.globl __irq_dma2_channel2
.set __irq_dma2_channel2, __default_handler
.weak __irq_dma2_channel3
.globl __irq_dma2_channel3
.set __irq_dma2_channel3, __default_handler
.weak __irq_dma2_channel4_5
.globl __irq_dma2_channel4_5
.set __irq_dma2_channel4_5, __default_handler
// .weak __irq_uart4 // __irq_uart4() defined in STM32F1/cores/maple/libmaple/usart_f1.c
// .globl __irq_uart4
// .set __irq_uart4, __default_handler
// .weak __irq_uart5 // __irq_uart5() defined in STM32F1/cores/maple/libmaple/usart_f1.c
// .globl __irq_uart5
// .set __irq_uart5, __default_handler
// .weak __irq_tim6 // __irq_tim6() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim6
// .set __irq_tim6, __default_handler
// .weak __irq_tim7 // __irq_tim7() defined in STM32F1/cores/maple/libmaple/timer.c
// .globl __irq_tim7
// .set __irq_tim7, __default_handler
// .weak __irq_dma2_channel1 // __irq_dma2_channel1() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma2_channel1
// .set __irq_dma2_channel1, __default_handler
// .weak __irq_dma2_channel2 // __irq_dma2_channel2() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma2_channel2
// .set __irq_dma2_channel2, __default_handler
// .weak __irq_dma2_channel3 // __irq_dma2_channel3() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma2_channel3
// .set __irq_dma2_channel3, __default_handler
// .weak __irq_dma2_channel4_5 // __irq_dma2_channel4_5() defined in STM32F1/cores/maple/libmaple/dma_f1.c
// .globl __irq_dma2_channel4_5
// .set __irq_dma2_channel4_5, __default_handler
#endif /* STM32_HIGH_DENSITY */

2
STM32F1/cores/maple/libmaple/systick.c
View File

@ -80,7 +80,7 @@ void systick_attach_callback(void (*callback)(void)) {
* SysTick ISR
*/
void __exc_systick(void) {
__weak void __exc_systick(void) {
systick_uptime_millis++;
if (systick_user_callback) {
systick_user_callback();

28
STM32F1/cores/maple/libmaple/timer.c
View File

@ -478,78 +478,78 @@ static void enable_bas_gen_irq(timer_dev *dev) {
* file.
*/
void __irq_tim1_brk(void) {
__weak void __irq_tim1_brk(void) {
dispatch_adv_brk(TIMER1);
#if STM32_HAVE_TIMER(9)
dispatch_tim_9_12(TIMER9);
#endif
}
void __irq_tim1_up(void) {
__weak void __irq_tim1_up(void) {
dispatch_adv_up(TIMER1);
#if STM32_HAVE_TIMER(10)
dispatch_tim_10_11_13_14(TIMER10);
#endif
}
void __irq_tim1_trg_com(void) {
__weak void __irq_tim1_trg_com(void) {
dispatch_adv_trg_com(TIMER1);
#if STM32_HAVE_TIMER(11)
dispatch_tim_10_11_13_14(TIMER11);
#endif
}
void __irq_tim1_cc(void) {
__weak void __irq_tim1_cc(void) {
dispatch_adv_cc(TIMER1);
}
void __irq_tim2(void) {
__weak void __irq_tim2(void) {
dispatch_general(TIMER2);
}
void __irq_tim3(void) {
__weak void __irq_tim3(void) {
dispatch_general(TIMER3);
}
void __irq_tim4(void) {
__weak void __irq_tim4(void) {
dispatch_general(TIMER4);
}
#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
void __irq_tim5(void) {
__weak void __irq_tim5(void) {
dispatch_general(TIMER5);
}
void __irq_tim6(void) {
__weak void __irq_tim6(void) {
dispatch_basic(TIMER6);
}
void __irq_tim7(void) {
__weak void __irq_tim7(void) {
dispatch_basic(TIMER7);
}
void __irq_tim8_brk(void) {
__weak void __irq_tim8_brk(void) {
dispatch_adv_brk(TIMER8);
#if STM32_HAVE_TIMER(12)
dispatch_tim_9_12(TIMER12);
#endif
}
void __irq_tim8_up(void) {
__weak void __irq_tim8_up(void) {
dispatch_adv_up(TIMER8);
#if STM32_HAVE_TIMER(13)
dispatch_tim_10_11_13_14(TIMER13);
#endif
}
void __irq_tim8_trg_com(void) {
__weak void __irq_tim8_trg_com(void) {
dispatch_adv_trg_com(TIMER8);
#if STM32_HAVE_TIMER(14)
dispatch_tim_10_11_13_14(TIMER14);
#endif
}
void __irq_tim8_cc(void) {
__weak void __irq_tim8_cc(void) {
dispatch_adv_cc(TIMER8);
}
#endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */

10
STM32F1/cores/maple/libmaple/usart_f1.c
View File

@ -200,24 +200,24 @@ void usart_foreach(void (*fn)(usart_dev*)) {
* Interrupt handlers.
*/
void __irq_usart1(void) {
__weak void __irq_usart1(void) {
usart_irq(&usart1_rb, &usart1_wb, USART1_BASE);
}
void __irq_usart2(void) {
__weak void __irq_usart2(void) {
usart_irq(&usart2_rb, &usart2_wb, USART2_BASE);
}
void __irq_usart3(void) {
__weak void __irq_usart3(void) {
usart_irq(&usart3_rb, &usart3_wb, USART3_BASE);
}
#ifdef STM32_HIGH_DENSITY
void __irq_uart4(void) {
__weak void __irq_uart4(void) {
usart_irq(&uart4_rb, &uart4_wb, UART4_BASE);
}
void __irq_uart5(void) {
__weak void __irq_uart5(void) {
usart_irq(&uart5_rb, &uart5_wb, UART5_BASE);
}
#endif

2
STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
View File

@ -190,7 +190,7 @@ static void usb_resume(RESUME_STATE eResumeSetVal) {
}
#define SUSPEND_ENABLED 1
void __irq_usb_lp_can_rx0(void) {
__weak void __irq_usb_lp_can_rx0(void) {
uint16 istr = USB_BASE->ISTR;
/* Use USB_ISR_MSK to only include code for bits we care about. */

5
STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
View File

@ -456,6 +456,11 @@ uint8 usb_cdcacm_is_transmitting(void) {
return ( transmitting>0 ? transmitting : 0);
}
int usb_cdcacm_tx_available()
{
return CDC_SERIAL_TX_BUFFER_SIZE - usb_cdcacm_get_pending() - 1;
}
uint16 usb_cdcacm_get_pending(void) {
return (tx_head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
}

51
STM32F1/cores/maple/sdio.cpp
View File

@ -32,8 +32,8 @@
sdio_dev * SDIO = SDIO_BASE;
#define DELAY_LONG 10
#define DELAY_SHORT 1
#define DELAY_LONG 20
#define DELAY_SHORT 2
uint8_t dly = DELAY_LONG; // microseconds delay after accessing registers
@ -43,9 +43,13 @@ uint8_t dly = DELAY_LONG; // microseconds delay after accessing registers
void sdio_gpios_init(void)
{
gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_AF_OUTPUT_PP);
/* gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_AF_OUTPUT_PP);
*/
gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_AF_OUTPUT_PP);
/*
@ -63,12 +67,12 @@ void sdio_gpios_init(void)
void sdio_gpios_deinit(void)
{
gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_INPUT_PU);
gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_INPUT_PU);
/*
* Todo just remove it, not needed for F1.
@ -110,19 +114,35 @@ void sdio_power_off(void)
void sdio_set_clock(uint32_t clk)
{
if (clk>24000000UL) clk = 24000000UL; // limit the SDIO master clock to 24MHz
/*
* limit the SDIO master clock to 8/3 of PCLK2.See RM 22.3
* Also limited to no more than 48Mhz
*/
clk = min(clk,(SDIOCLK/3)*8);
clk = min(clk,36000000);
if (clk<1000000) dly = DELAY_LONG;
else dly = DELAY_SHORT;
/*
* round up divider, so we don't run the card over the speed supported.
*/
uint32 div = SDIOCLK/clk + (SDIOCLK % clk != 0) - 2;
sdio_disable();
SDIO->CLKCR = (SDIO->CLKCR & (~(SDIO_CLKCR_CLKDIV|SDIO_CLKCR_BYPASS))) | SDIO_CLKCR_CLKEN | (((SDIOCLK/clk)-2)&SDIO_CLKCR_CLKDIV);
//Serial.println(div,DEC);
SDIO->CLKCR = (SDIO->CLKCR & (~(SDIO_CLKCR_CLKDIV|SDIO_CLKCR_BYPASS))) | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_HWFC_EN | SDIO_CLKCR_CLKEN | (div & SDIO_CLKCR_CLKDIV);
delay_us(dly);
}
void sdio_set_dbus_width(uint16_t bus_w)
{
SDIO->CLKCR = (SDIO->CLKCR & (~SDIO_CLKCR_WIDBUS)) | bus_w;
gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_AF_OUTPUT_PP);
delay_us(dly);
}
@ -149,9 +169,10 @@ void sdio_disable(void)
*/
void sdio_begin(void)
{
sdio_gpios_init();
sdio_init();
sdio_power_on();
sdio_gpios_init();
// Set initial SCK rate.
sdio_set_clock(400000);
delay_us(200); // generate 80 pulses at 400kHz
@ -162,11 +183,11 @@ void sdio_begin(void)
*/
void sdio_end(void)
{
sdio_disable();
while ( sdio_cmd_xfer_ongoing() );
while ( sdio_cmd_xfer_ongoing() );
sdio_disable();
sdio_gpios_deinit();
sdio_power_off();
rcc_clk_disable(RCC_SDIO);
sdio_gpios_deinit();
}
/**

51
STM32F1/cores/maple/usb_serial.cpp
View File

@ -37,7 +37,7 @@
#include <libmaple/usb_cdcacm.h>
#include <libmaple/usb.h>
#include <libmaple/iwdg.h>
#include <libmaple/bkp.h>
#include "wirish.h"
/*
@ -148,6 +148,8 @@ int USBSerial::peek(void)
}
}
int USBSerial::availableForWrite(void) { return usb_cdcacm_tx_available(); }
void USBSerial::flush(void)
{
/*Roger Clark. Rather slow method. Need to improve this */
@ -263,20 +265,12 @@ static void ifaceSetupHook(unsigned hook __attribute__((unused)), void *requestv
break;
}
#endif
#if defined(BOOTLOADER_robotis)
uint8 dtr = usb_cdcacm_get_dtr();
uint8 rts = usb_cdcacm_get_rts();
if (rts && !dtr) {
reset_state = DTR_NEGEDGE;
}
#endif
#if false
if ((usb_cdcacm_get_baud() == 1200) && (reset_state == DTR_NEGEDGE)) {
iwdg_init(IWDG_PRE_4, 10);
while (1);
}
#endif
}
#define RESET_DELAY 100000
@ -287,41 +281,40 @@ static void wait_reset(void) {
}
#endif
#define STACK_TOP 0x20000800
#define EXC_RETURN 0xFFFFFFF9
#define DEFAULT_CPSR 0x61000000
static void rxHook(unsigned hook __attribute__((unused)), void *ignored __attribute__((unused))) {
static const uint8 magic[4] = {'1', 'E', 'A', 'F'};
/* FIXME this is mad buggy; we need a new reset sequence. E.g. NAK
* after each RX means you can't reset if any bytes are waiting. */
if (reset_state == DTR_NEGEDGE) {
reset_state = DTR_LOW;
if (usb_cdcacm_data_available() >= 4) {
// The magic reset sequence is "1EAF".
#ifdef SERIAL_USB
static const uint8 magic[4] = {'1', 'E', 'A', 'F'};
#else
#if defined(BOOTLOADER_robotis)
static const uint8 magic[4] = {'C', 'M', '9', 'X'};
#else
static const uint8 magic[4] = {'1', 'E', 'A', 'F'};
#endif
#endif
if (usb_cdcacm_data_available() >= 4)
{
uint8 chkBuf[4];
// Peek at the waiting bytes, looking for reset sequence,
// bailing on mismatch.
usb_cdcacm_peek_ex(chkBuf, usb_cdcacm_data_available() - 4, 4);
for (unsigned i = 0; i < sizeof(magic); i++) {
if (chkBuf[i] != magic[i]) {
if (chkBuf[i] != magic[i])
{
reset_state = DTR_LOW;
return;
}
}
#ifdef SERIAL_USB
// The magic reset sequence is "1EAF".
// Got the magic sequence -> reset, presumably into the bootloader.
// Return address is wait_reset, but we must set the thumb bit.
bkp_init();
bkp_enable_writes();
bkp_write(10, 0x424C);
bkp_disable_writes();
uintptr_t target = (uintptr_t)wait_reset | 0x1;
asm volatile("mov r0, %[stack_top] \n\t" // Reset stack
"mov sp, r0 \n\t"
@ -345,15 +338,9 @@ static void rxHook(unsigned hook __attribute__((unused)), void *ignored __attrib
[cpsr] "r" (DEFAULT_CPSR)
: "r0", "r1", "r2");
#endif
#if defined(BOOTLOADER_robotis)
iwdg_init(IWDG_PRE_4, 10);
#endif
/* Can't happen. */
ASSERT_FAULT(0);
}
}
}
#endif // BOARD_HAVE_SERIALUSB
#endif // BOARD_HAVE_SERIALUSB

0
STM32F1/libraries/FreeRTOS/MapleFreeRTOS.cpp → STM32F1/libraries/FreeRTOS701/MapleFreeRTOS.cpp
View File

0
STM32F1/libraries/FreeRTOS/MapleFreeRTOS.h → STM32F1/libraries/FreeRTOS701/MapleFreeRTOS.h
View File

0
STM32F1/libraries/FreeRTOS/keywords.txt → STM32F1/libraries/FreeRTOS701/keywords.txt
View File

0
STM32F1/libraries/FreeRTOS/rules.mk → STM32F1/libraries/FreeRTOS701/rules.mk
View File

0
STM32F1/libraries/FreeRTOS/utility/FreeRTOS.h → STM32F1/libraries/FreeRTOS701/utility/FreeRTOS.h
View File

0
STM32F1/libraries/FreeRTOS/utility/FreeRTOSConfig.h → STM32F1/libraries/FreeRTOS701/utility/FreeRTOSConfig.h
View File

0
STM32F1/libraries/FreeRTOS/utility/StackMacros.h → STM32F1/libraries/FreeRTOS701/utility/StackMacros.h
View File

0
STM32F1/libraries/FreeRTOS/utility/croutine.c → STM32F1/libraries/FreeRTOS701/utility/croutine.c
View File

0
STM32F1/libraries/FreeRTOS/utility/croutine.h → STM32F1/libraries/FreeRTOS701/utility/croutine.h
View File

0
STM32F1/libraries/FreeRTOS/utility/heap_2.c → STM32F1/libraries/FreeRTOS701/utility/heap_2.c
View File

0
STM32F1/libraries/FreeRTOS/utility/list.c → STM32F1/libraries/FreeRTOS701/utility/list.c
View File

0
STM32F1/libraries/FreeRTOS/utility/list.h → STM32F1/libraries/FreeRTOS701/utility/list.h
View File

0
STM32F1/libraries/FreeRTOS/utility/mpu_wrappers.h → STM32F1/libraries/FreeRTOS701/utility/mpu_wrappers.h
View File

0
STM32F1/libraries/FreeRTOS/utility/port.c → STM32F1/libraries/FreeRTOS701/utility/port.c
View File

0
STM32F1/libraries/FreeRTOS/utility/portable.h → STM32F1/libraries/FreeRTOS701/utility/portable.h
View File

0
STM32F1/libraries/FreeRTOS/utility/portmacro.h → STM32F1/libraries/FreeRTOS701/utility/portmacro.h
View File

0
STM32F1/libraries/FreeRTOS/utility/projdefs.h → STM32F1/libraries/FreeRTOS701/utility/projdefs.h
View File

0
STM32F1/libraries/FreeRTOS/utility/queue.c → STM32F1/libraries/FreeRTOS701/utility/queue.c
View File

0
STM32F1/libraries/FreeRTOS/utility/queue.h → STM32F1/libraries/FreeRTOS701/utility/queue.h
View File

0
STM32F1/libraries/FreeRTOS/utility/semphr.h → STM32F1/libraries/FreeRTOS701/utility/semphr.h
View File

0
STM32F1/libraries/FreeRTOS/utility/task.h → STM32F1/libraries/FreeRTOS701/utility/task.h
View File

0
STM32F1/libraries/FreeRTOS/utility/tasks.c → STM32F1/libraries/FreeRTOS701/utility/tasks.c
View File

0
STM32F1/libraries/FreeRTOS/utility/timers.c → STM32F1/libraries/FreeRTOS701/utility/timers.c
View File

0
STM32F1/libraries/FreeRTOS/utility/timers.h → STM32F1/libraries/FreeRTOS701/utility/timers.h
View File

2
STM32F1/libraries/RTClock/examples/BluePill-RTClock-test/BluePill-RTClock-test.ino
View File

@ -40,7 +40,7 @@ uint8_t AlarmExchange = 0;
bool dispflag = true;
//-----------------------------------------------------------------------------
const char * weekdays[] = {"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"};
const char * weekdays[] = {"Mon", "Tue", "Wed", "Thu", "Fri", "Sat", "Sun"};
const char * months[] = {"Dummy", "Jan", "Feb", "Mar", "Apr", "May", "Jun", "Jul", "Aug", "Sep", "Oct", "Nov", "Dec" };
//-----------------------------------------------------------------------------
uint8_t str2month(const char * d)

2
STM32F1/libraries/RTClock/src/RTClock.cpp
View File

@ -39,7 +39,7 @@
}//end RTC
RTClock::RTClock(rtc_clk_src src, uint16 prescaler ) {
RTClock::RTClock(rtc_clk_src src, uint32 prescaler ) {
switch (src) {
case RTCSEL_LSE : {

2
STM32F1/libraries/RTClock/src/RTClock.h
View File

@ -41,7 +41,7 @@ class RTClock {
public:
RTClock();
RTClock(rtc_clk_src src );
RTClock(rtc_clk_src src, uint16 prescaler );
RTClock(rtc_clk_src src, uint32 prescaler );
//~RTClock(); //to implement
void breakTime(time_t epoch_time, tm_t & tmm);

14
STM32F1/libraries/RTClock/src/utility/rtc_util.c
View File

@ -168,8 +168,10 @@ uint32 rtc_get_count() {
rtc_clear_sync();
rtc_wait_sync();
rtc_wait_finished();
h = RTC->regs->CNTH & 0xffff;
l = RTC->regs->CNTL & 0xffff;
do {
h = RTC->regs->CNTH & 0xffff;
l = RTC->regs->CNTL & 0xffff;
} while (h != (RTC->regs->CNTH & 0xffff));
return (h << 16) | l;
}
@ -182,10 +184,8 @@ void rtc_set_count(uint32 value) {
rtc_wait_sync();
rtc_wait_finished();
rtc_enter_config_mode();
do {
h = RTC->regs->CNTH & 0xffff;
l = RTC->regs->CNTL & 0xffff;
} while (h ^ (RTC->regs->CNTH & 0xffff));
RTC->regs->CNTH = (value >> 16) & 0xffff;
RTC->regs->CNTL = value & 0xffff;
rtc_exit_config_mode();
rtc_wait_finished();
}
@ -216,7 +216,7 @@ uint32 rtc_get_divider() {
do {
h = RTC->regs->DIVH & 0x000f;
l = RTC->regs->DIVL & 0xffff;
} while (h ^ (RTC->regs->DIVH & 0x000f));
} while (h != (RTC->regs->DIVH & 0x000f));
return (h << 16) | l;
}

735
STM32F1/libraries/SDIO/SdioF1.cpp
View File

File diff suppressed because it is too large Load Diff

4
STM32F1/libraries/SDIO/SdioF1.h
View File

@ -1,6 +1,6 @@
#ifndef _SDIOF4_H_
#define _SDIOF4_H_
#ifndef _SDIOF1_H_
#define _SDIOF1_H_
#include <SdFat.h>

37
STM32F1/libraries/SPI/examples/spi_slave/spi_slave.ino Normal file
View File

@ -0,0 +1,37 @@
// SPI full-duplex slave example
// STM32 acts as a SPI slave and reads 8 bit data frames over SPI.
// Master also gets a reply from the slave, which is a a simple count (0, 1, 2, 3)
// that is incremented each time a data frame is received.
// Serial output is here for debug
#include <SPI.h>
#include <cstdint>
void setupSPI(void)
{
// The clock value is not used
// SPI1 is selected by default
// MOSI, MISO, SCK and NSS PINs are set by the library
SPI.beginTransactionSlave(SPISettings(18000000, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT));
}
void setup()
{
Serial.begin(115200);
delay(100);
setupSPI();
}
uint8_t count = 0;
void loop()
{
// Blocking call to read SPI message
uint8_t msg = SPI.transfer(++count);
Serial.print("Received = 0b");
Serial.print(msg, BIN);
Serial.print(", 0x");
Serial.print(msg, HEX);
Serial.print(", ");
Serial.println(msg);
}

2
STM32F1/libraries/Wire/Wire.cpp
View File

@ -50,7 +50,7 @@ uint8 TwoWire::process(uint8 stop) {
res = EOTHER;
}
i2c_disable(sel_hard);
i2c_master_enable(sel_hard, (I2C_BUS_RESET | dev_flags));
i2c_master_enable(sel_hard, dev_flags);
}
return res;
}

24
STM32F1/libraries/Wire/utility/WireBase.cpp
View File

@ -71,7 +71,7 @@ uint8 WireBase::endTransmission(bool stop) {
}
uint8 WireBase::endTransmission(){
endTransmission(true);
return endTransmission(true);
}
//TODO: Add the ability to queue messages (adding a boolean to end of function
@ -95,27 +95,33 @@ uint8 WireBase::requestFrom(int address, int numBytes) {
return WireBase::requestFrom((uint8)address, numBytes);
}
void WireBase::write(uint8 value) {
size_t WireBase::write(uint8 value) {
if (tx_buf_idx == BUFFER_LENGTH) {
tx_buf_overflow = true;
return;
return 0;
}
tx_buf[tx_buf_idx++] = value;
itc_msg.length++;
return 1;
}
void WireBase::write(uint8* buf, int len) {
size_t WireBase::write(uint8* buf, int len) {
for (uint8 i = 0; i < len; i++) {
write(buf[i]);
if (!write(buf[i]))
{
return i;
}
}
return len;
}
void WireBase::write(int value) {
write((uint8)value);
size_t WireBase::write(int value) {
return write((uint8)value);
}
void WireBase::write(int* buf, int len) {
write((uint8*)buf, (uint8)len);
size_t WireBase::write(int* buf, int len) {
return write((uint8*)buf, (uint8)len);
}
void WireBase::write(char* buf) {

8
STM32F1/libraries/Wire/utility/WireBase.h
View File

@ -108,22 +108,22 @@ public:
/*
* Stack up bytes to be sent when transmitting
*/
void write(uint8);
size_t write(uint8);
/*
* Stack up bytes from the array to be sent when transmitting
*/
void write(uint8*, int);
size_t write(uint8*, int);
/*
* Ensure that a sending data will only be 8-bit bytes
*/
void write(int);
size_t write(int);
/*
* Ensure that an array sending data will only be 8-bit bytes
*/
void write(int*, int);
size_t write(int*, int);
/*
* Stack up bytes from a string to be sent when transmitting

16
STM32F1/platform.txt
View File

@ -36,7 +36,7 @@ compiler.define=-DARDUINO=
# this can be overriden in boards.txt
build.f_cpu=72000000L
build.mcu=cortex-m3
build.common_flags=-mthumb -march=armv7-m -D__STM32F1__
build.common_flags=-mthumb -march=armv7-m -D__STM32F1__ -DARDUINO_ARCH_STM32
build.variant_system_lib=libmaple.a
## LED stuff is not really used but is still required in the code
build.error_led_port=GPIOB
@ -87,7 +87,7 @@ recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={b
recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
## Combine gc-sections, archives, and objects
recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group {object_files} "{build.path}/{archive_file}" -Wl,--end-group
recipe.c.combine.pattern="{compiler.path}{compiler.c.elf.cmd}" {compiler.c.elf.flags} -mcpu={build.mcu} "-T{build.variant.path}/{build.ldscript}" "-Wl,-Map,{build.path}/{build.project_name}.map" {compiler.c.elf.extra_flags} -o "{build.path}/{build.project_name}.elf" "-L{build.path}" -lm -lgcc -mthumb -Wl,--cref -Wl,--check-sections -Wl,--gc-sections -Wl,--unresolved-symbols=report-all -Wl,--warn-common -Wl,--warn-section-align -Wl,--warn-unresolved-symbols -Wl,--start-group {object_files} "{archive_file_path}" -Wl,--end-group
## Create eeprom
recipe.objcopy.eep.pattern=
@ -161,3 +161,15 @@ tools.jlink_upload.path.linux64={runtime.hardware.path}/tools/linux64
tools.jlink_upload.upload.params.verbose=-d
tools.jlink_upload.upload.params.quiet=n
tools.jlink_upload.upload.pattern="{path}/{cmd}" "{build.path}/{build.project_name}.bin"
# HID upload
tools.hid_upload.cmd=hid_upload
tools.hid_upload.cmd.windows=hid_upload.bat
tools.hid_upload.cmd.macosx=hid_upload
tools.hid_upload.path={runtime.hardware.path}/tools/win
tools.hid_upload.path.macosx={runtime.hardware.path}/tools/macosx
tools.hid_upload.path.linux={runtime.hardware.path}/tools/linux
tools.hid_upload.path.linux64={runtime.hardware.path}/tools/linux64
tools.hid_upload.upload.params.verbose=-d
tools.hid_upload.upload.params.quiet=n
tools.hid_upload.upload.pattern="{path}/{cmd}" {serial.port.file} {upload.altID} {upload.usbID} "{build.path}/{build.project_name}.bin"

26
STM32F1/system/libmaple/include/libmaple/sdio.h
View File

@ -52,19 +52,19 @@ extern "C" {
// SDIO register map type
typedef struct sdio_reg_map {
__io uint32 POWER; // 0x00
__io uint32 CLKCR; // 0x04
__io uint32 ARG; // 0x08
__io uint32 CMD; // 0x0C
__io uint32 RESPCMD; // 0x10 (0x3F)
__io const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response.
__io uint32 DTIMER; // 0x24 - contains the data timeout period, in card bus clock periods.
__io uint32 DLEN; // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
__io uint32 DCTRL; // 0x2C
__io uint32 DCOUNT; // 0x30 (0x01FF FFFF)
__io uint32 STA; // 0x34
__io uint32 ICR; // 0x38
__io uint32 MASK; // 0x3C
__IO uint32 POWER; // 0x00
__IO uint32 CLKCR; // 0x04
__IO uint32 ARG; // 0x08
__IO uint32 CMD; // 0x0C
__IO uint32 RESPCMD; // 0x10 (0x3F)
__IO const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response.
__IO uint32 DTIMER; // 0x24 - contains the data timeout period, in card bus clock periods.
__IO uint32 DLEN; // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
__IO uint32 DCTRL; // 0x2C
__IO uint32 DCOUNT; // 0x30 (0x01FF FFFF)
__IO uint32 STA; // 0x34
__IO uint32 ICR; // 0x38
__IO uint32 MASK; // 0x3C
const uint32 RESERVED1[2];
__IO uint32 FIFOCNT; // 0x48 (0x01FF FFFF)
const uint32 RESERVED2[13];

3
STM32F1/system/libmaple/include/libmaple/timer.h
View File

@ -843,7 +843,8 @@ static inline void timer_dma_disable_req(timer_dev *dev, uint8 channel) {
*/
static inline void timer_enable_irq(timer_dev *dev, uint8 interrupt) {
// clear interrupt flag, use different masks for reserved bits
*bb_perip(&(dev->regs).adv->SR, interrupt) = 0; // clear interrupt flag
(dev->regs).adv->SR = (~BIT(interrupt)) & ( (dev->type==TIMER_ADVANCED) ? 0x1EFF :
( (dev->type==TIMER_GENERAL) ? 0x1E5F : 0x0001) );
*bb_perip(&(dev->regs).adv->DIER, interrupt) = 1;
}

3
STM32F1/system/libmaple/include/libmaple/usb_cdcacm.h
View File

@ -129,10 +129,13 @@ uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len);
uint32 usb_cdcacm_data_available(void); /* in RX buffer */
uint16 usb_cdcacm_get_pending(void);
uint8 usb_cdcacm_is_transmitting(void);
int usb_cdcacm_tx_available();
uint8 usb_cdcacm_get_dtr(void);
uint8 usb_cdcacm_get_rts(void);
typedef struct usb_cdcacm_line_coding {
uint32 dwDTERate; /* Baud rate */

2
STM32F1/system/libmaple/stm32f1/include/series/flash.h
View File

@ -132,7 +132,7 @@ typedef struct flash_reg_map {
* Series-specific configuration values.
*/
#define FLASH_SAFE_WAIT_STATES FLASH_WAIT_STATE_2
#define FLASH_SAFE_WAIT_STATES (F_CPU > 48000000 ? FLASH_WAIT_STATE_2 : F_CPU > 24000000 ? FLASH_WAIT_STATE_1 : FLASH_WAIT_STATE_0)
/* Flash memory features available via ACR */
enum {

2
STM32F1/system/libmaple/usb/usb_lib/usb_type.h
View File

@ -62,7 +62,7 @@ typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
//typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */

6
STM32F1/variants/STM32VLD/wirish/boards.cpp
View File

@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_gd32f103c/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

9
STM32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp
View File

@ -46,6 +46,7 @@
// Additionally the GD32 has a 4 USB PLL divider settings, rather than the 2 settings in the STM32, which allow it to operate on frequencies of 48,72,96 and 120Mhz and still have USB functioning
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==120000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_10
#elif F_CPU==96000000
@ -53,14 +54,20 @@
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

10
STM32F1/variants/generic_stm32f103c/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

10
STM32F1/variants/generic_stm32f103r/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

10
STM32F1/variants/generic_stm32f103r8/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

10
STM32F1/variants/generic_stm32f103t/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

10
STM32F1/variants/generic_stm32f103v/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -153,11 +153,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

8
STM32F3/variants/discovery_f3/ld/flash.ld → STM32F1/variants/generic_stm32f103vb/ld/stm32f103veDFU.ld
View File

@ -14,15 +14,17 @@
* use this file to use any of libmaple's memory-related hooks (like
* where the heap should live).
*/
INCLUDE mem-flash.inc
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
rom (rx) : ORIGIN = 0x08002000, LENGTH = 504K
}
/* Provide memory region aliases for common.inc */
REGION_ALIAS("REGION_TEXT", rom);
REGION_ALIAS("REGION_DATA", ram);
REGION_ALIAS("REGION_BSS", ram);
REGION_ALIAS("REGION_RODATA", rom);
REGION_ALIAS("REGION_CCM", ccm);
/* Let common.inc handle the real work. */
INCLUDE common.inc

10
STM32F1/variants/generic_stm32f103vb/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -153,11 +153,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103vb/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

10
STM32F1/variants/generic_stm32f103z/wirish/boards.cpp
View File

@ -120,12 +120,12 @@ static void setup_clocks(void) {
// Clear clock readiness interrupt flags and turn off clock
// readiness interrupts.
RCC_BASE->CIR = 0x00000000;
#if !USE_HSI_CLOCK
// Enable HSE, and wait until it's ready.
rcc_turn_on_clk(RCC_CLK_HSE);
while (!rcc_is_clk_ready(RCC_CLK_HSE))
;
#endif
// Configure AHBx, APBx, etc. prescalers and the main PLL.
wirish::priv::board_setup_clock_prescalers();
rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

10
STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
View File

@ -48,20 +48,30 @@
// works for F103 performance line MCUs, which is all that LeafLabs
// currently officially supports).
#ifndef BOARD_RCC_PLLMUL
#if !USE_HSI_CLOCK
#if F_CPU==128000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#elif F_CPU==72000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#else
#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
#endif
#endif
namespace wirish {
namespace priv {
static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
#if !USE_HSI_CLOCK
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
#else
__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
#endif
__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;

6
STM32F1/variants/hytiny_stm32f103t/wirish/boards.cpp
View File

@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

2
STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
View File

@ -54,6 +54,8 @@
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#endif

6
STM32F1/variants/maple/wirish/boards.cpp
View File

@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

2
STM32F1/variants/maple/wirish/boards_setup.cpp
View File

@ -54,6 +54,8 @@
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#endif

6
STM32F1/variants/maple_mini/wirish/boards.cpp
View File

@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

2
STM32F1/variants/maple_mini/wirish/boards_setup.cpp
View File

@ -54,6 +54,8 @@
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#endif

12
STM32F1/variants/maple_ret6/board/board.h
View File

@ -102,6 +102,16 @@
#define BOARD_USB_DISC_DEV GPIOC
#define BOARD_USB_DISC_BIT 12
/*
* SDIO Pins
*/
#define BOARD_SDIO_D0 PC8
#define BOARD_SDIO_D1 PC9
#define BOARD_SDIO_D2 PC10
#define BOARD_SDIO_D3 PC11
#define BOARD_SDIO_CLK PC12
#define BOARD_SDIO_CMD PD2
/* Pin aliases: these give the GPIO port/bit for each pin as an
* enum. These are optional, but recommended. They make it easier to
* write code using low-level GPIO functionality. */
@ -117,4 +127,4 @@ enum {
//15 16 17 18 19 20 21 22 23 24 25 26 27 28
//29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
//29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

6
STM32F1/variants/maple_ret6/wirish/boards.cpp
View File

@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

2
STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
View File

@ -54,6 +54,8 @@
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#endif

6
STM32F1/variants/microduino/wirish/boards.cpp
View File

@ -147,11 +147,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

2
STM32F1/variants/microduino/wirish/boards_setup.cpp
View File

@ -54,6 +54,8 @@
#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
#elif F_CPU==48000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
#elif F_CPU==16000000
#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
#endif
#endif

6
STM32F1/variants/nucleo_f103rb/wirish/boards.cpp
View File

@ -149,11 +149,7 @@ static void setup_clocks(void) {
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#else
#if defined(BOOTLOADER_robotis)
#define USER_ADDR_ROM 0x08003000
#else
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;

45
STM32F3/README.md
View File

@ -1,45 +0,0 @@
STM32F3 files have been supplied by Frank-Michael Krause.
The API is not as up to date as in the STM F103 files.
It looks like this port is as the F103 files orginally were when I started work on the project.
The API is for pre- Arduino 1.0 and doesn't include a lot of functions in the 1.0 API, and the class inheritance will
be different in a number of places, most importantly in the Serial class.
Specifically Stream.cpp / .h are not present in this port.
-------------------- Details from Frank-Michael ----------------------------
This port of libmaple for Arduino-IDE is based on the inofficial F3 branch
of libmaple found on
https://github.com/ventosus/libmaple/tree/F3
and supports at the moment the STM32F3Discovery board with programming via ST-link.
Linker is configured for linking to flash, not to RAM
Changes by Frank-Michael Krause (mich dot krause at web dot de):
- renaming some stm32f3 related files because the Arduino build system copy all objects to same directory so the source file names must be different
- selected the correct startup modules and linker scripts for board variant stm32f3discovery
Notes:
- the pin names as noted on stm32f3discovery board (PA0, PA1, ..., PF10) can be used as pin id
- usb is untested because I haven't used it really
- There are some libraries and examples related to the STM32F3discovery board.
They are commented mostly in german only because I wrote them for use at robotic club of a secondary school
and the kids like to have the documentation in german.
gyro: Interface library for the gyro-chip of the stm32f3discovery, setup the gyro in FIFO mode and so
requiring update calls only every < 120ms
lsm303: Interface library for Acceleration sensor of the stm32f3discovery, magnetometer not yet supported (writing this driver is currently under work by a student at school)
ringbuffer: Class impelentig a ringbuffer with functions for adding time stampes per added element, averaging functions, accessing the stored data like an array
roboter: several functionalities needed to program a robot:
- dc motor control as known from Lego NXC language
- support for HC-SR04 ultrasonic sensors driven by interrupt or blocking direct measurement
- function timers based on timer interrupt
- modul for interfacing a 24Cxx I2C eeprom chip

62
STM32F3/boards.txt
View File

@ -1,62 +0,0 @@
#
menu.opt=Optimize
##############################################################
discovery_f3.name=STM32F3Discovery
discovery_f3.upload.tool=stlink
discovery_f3.upload.protocol=stlink
#discovery_f407.upload.use_1200bps_touch=false
discovery_f3.upload.file_type=bin
discovery_f3.upload.maximum_size=262144
discovery_f3.upload.maximum_data_size=49152
#discovery_f3.upload.usbID=1EAF:0003
#discovery_f3.upload.altID=1
#discovery_f3.upload.auto_reset=true
discovery_f3.build.mcu=cortex-m3
discovery_f3.build.f_cpu=72000000L
discovery_f3.build.core=maple
discovery_f3.build.extra_flags=-DMCU_STM32F303VC -mthumb -DSTM32_XL_DENSITY -march=armv7-m -DSTM32F3 -DF303VC -DBOARD_discovery_f3
discovery_f3.build.ldscript=ld/jtag.ld
discovery_f3.build.variant=discovery_f3
discovery_f3.build.variant_system_lib=lib_f3.a
discovery_f3.build.vect=VECT_TAB_BASE
discovery_f3.build.density=STM32_XL_DENSITY
discovery_f3.build.error_led_port=GPIOE
discovery_f3.build.error_led_pin=8
discovery_f3.build.board=STM32F3Discovery
#-- Optimizations
discovery_f3.menu.opt.osstd=Smallest (default)
discovery_f3.menu.opt.osstd.build.flags.optimize=-Os
discovery_f3.menu.opt.osstd.build.flags.ldspecs=
discovery_f3.menu.opt.oslto=Smallest Code with LTO
discovery_f3.menu.opt.oslto.build.flags.optimize=-Os -flto
discovery_f3.menu.opt.oslto.build.flags.ldspecs=-flto
discovery_f3.menu.opt.o1std=Fast (-O1)
discovery_f3.menu.opt.o1std.build.flags.optimize=-O1
discovery_f3.menu.opt.o1std.build.flags.ldspecs=
discovery_f3.menu.opt.o1lto=Fast (-O1) with LTO
discovery_f3.menu.opt.o1lto.build.flags.optimize=-O1 -flto
discovery_f3.menu.opt.o1lto.build.flags.ldspecs=-flto
discovery_f3.menu.opt.o2std=Faster (-O2)
discovery_f3.menu.opt.o2std.build.flags.optimize=-O2
discovery_f3.menu.opt.o2std.build.flags.ldspecs=
discovery_f3.menu.opt.o2lto=Faster (-O2) with LTO
discovery_f3.menu.opt.o2lto.build.flags.optimize=-O2 -flto
discovery_f3.menu.opt.o2lto.build.flags.ldspecs=-flto
discovery_f3.menu.opt.o3std=Fastest (-O3)
discovery_f3.menu.opt.o3std.build.flags.optimize=-O3
discovery_f3.menu.opt.o3std.build.flags.ldspecs=
discovery_f3.menu.opt.o3lto=Fastest (-O3) with LTO
discovery_f3.menu.opt.o3lto.build.flags.optimize=-O3 -flto
discovery_f3.menu.opt.o3lto.build.flags.ldspecs=-flto
discovery_f3.menu.opt.ogstd=Debug (-g)
discovery_f3.menu.opt.ogstd.build.flags.optimize=-Og
discovery_f3.menu.opt.ogstd.build.flags.ldspecs=
##############################################################

4
STM32F3/cores/maple/Arduino.h
View File

@ -1,4 +0,0 @@
#ifndef Arduino_h
#define Arduino_h
#include "WProgram.h"
#endif

35
STM32F3/cores/maple/WProgram.h
View File

@ -1,35 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 LeafLabs LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
#ifndef _WIRISH_WPROGRAM_H_
#define _WIRISH_WPROGRAM_H_
#include <wirish/wirish.h>
void setup();
void loop();
#endif

52
STM32F3/cores/maple/libmaple/adc.c
View File

@ -1,52 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
* Copyright (c) 2011, 2012 LeafLabs, LLC.
* Copyright (c) 2013 OpenMusicKontrollers.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/adc.c
* @author Marti Bolivar <mbolivar@leaflabs.com>,
* Perry Hung <perry@leaflabs.com>,
* F3-port by Hanspeter Portner <dev@open-music-kontrollers.ch>
* @brief Analog to digital converter routines
*/
#include <libmaple/adc.h>
#include <libmaple/libmaple.h>
#include <libmaple/rcc.h>
/**
* @brief Initialize an ADC peripheral.
*
* Initializes the RCC clock line for the given peripheral. Resets
* ADC device registers.
*
* @param dev ADC peripheral to initialize
*/
void adc_init(const adc_dev *dev) {
rcc_clk_enable(dev->clk_id);
rcc_reset_dev(dev->clk_id);
}

69
STM32F3/cores/maple/libmaple/bkp.c
View File

@ -1,69 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 LeafLabs, LLC.
* Copyright (c) 2013 OpenMusicKontrollers.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/bkp.c
* @author F3-port by Hanspeter Portner <dev@open-music-kontrollers.ch>
* @brief Backup register support (STM32F1 & STM32F3 only).
*/
#include <libmaple/pwr.h>
#include <libmaple/bkp.h>
#include <libmaple/bitband.h>
bkp_dev bkp = {
.regs = BKP_BASE,
};
/** Backup device. */
const bkp_dev *BKP = &bkp;
void bkp_enable_writes(void) {
*bb_perip(&PWR_BASE->CR, PWR_CR_DBP_BIT) = 1;
}
void bkp_disable_writes(void) {
*bb_perip(&PWR_BASE->CR, PWR_CR_DBP_BIT) = 0;
}
uint16 bkp_read(uint8 reg) {
__IO uint32* dr = bkp_data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return 0;
}
return (uint16)*dr;
}
void bkp_write(uint8 reg, uint16 val) {
__IO uint32* dr = bkp_data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return;
}
*dr = (uint32)val;
}

120
STM32F3/cores/maple/libmaple/dac.c
View File

@ -1,120 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Bryan Newbold.
* Copyright (c) 2011, 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/dac.c
* @brief Digital to analog converter support.
*/
#include <libmaple/dac.h>
#include <libmaple/libmaple.h>
#include <libmaple/gpio.h>
#if STM32_HAVE_DAC
dac_dev dac = {
.regs = DAC_BASE,
};
const dac_dev *DAC = &dac;
#endif
/**
* @brief Initialize the digital to analog converter
* @param dev DAC device
* @param flags Flags:
* DAC_CH1: Enable channel 1
* DAC_CH2: Enable channel 2
* @sideeffect May set PA4 or PA5 to INPUT_ANALOG
*/
void dac_init(const dac_dev *dev, uint32 flags) {
/* First turn on the clock */
rcc_clk_enable(RCC_DAC);
rcc_reset_dev(RCC_DAC);
if (flags & DAC_CH1) {
dac_enable_channel(dev, 1);
}
if (flags & DAC_CH2) {
dac_enable_channel(dev, 2);
}
}
/**
* @brief Write a 12-bit value to the DAC to output
* @param dev DAC device
* @param channel channel to select (1 or 2)
* @param val value to write
*/
void dac_write_channel(const dac_dev *dev, uint8 channel, uint16 val) {
switch(channel) {
case 1:
dev->regs->DHR12R1 = DAC_DHR12R1_DACC1DHR & val;
break;
case 2:
dev->regs->DHR12R2 = DAC_DHR12R2_DACC2DHR & val;
break;
}
}
/**
* @brief Enable a DAC channel
* @param dev DAC device
* @param channel channel to enable, either 1 or 2
* @sideeffect May change pin mode of PA4 or PA5
*/
void dac_enable_channel(const dac_dev *dev, uint8 channel) {
/*
* Setup ANALOG mode on PA4 and PA5. This mapping is consistent
* across all supported STM32s with a DAC.
*/
switch (channel) {
case 1:
gpio_set_mode(GPIOA, 4, GPIO_MODE_ANALOG);
dev->regs->CR |= DAC_CR_EN1;
break;
case 2:
gpio_set_mode(GPIOA, 5, GPIO_MODE_ANALOG);
dev->regs->CR |= DAC_CR_EN2;
break;
}
}
/**
* @brief Disable a DAC channel
* @param dev DAC device
* @param channel channel to disable, either 1 or 2
*/
void dac_disable_channel(const dac_dev *dev, uint8 channel) {
switch (channel) {
case 1:
dev->regs->CR &= ~DAC_CR_EN1;
break;
case 2:
dev->regs->CR &= ~DAC_CR_EN2;
break;
}
}

82
STM32F3/cores/maple/libmaple/dma.c
View File

@ -1,82 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Michael Hope.
* Copyright (c) 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/dma.c
* @author Marti Bolivar <mbolivar@leaflabs.com>;
* Original implementation by Michael Hope
* @brief Portable DMA routines.
*/
#include <libmaple/dma.h>
#include "dma_private.h"
#include "stm32_private.h"
/*
* Convenience routines
*/
/**
* @brief Initialize a DMA device.
* @param dev Device to initialize.
*/
void dma_init(dma_dev *dev) {
rcc_clk_enable(dev->clk_id);
}
/*
* Private API
*/
enum dma_atype _dma_addr_type(__IO void *addr) {
switch (stm32_block_purpose((void*)addr)) {
/* Notice we're treating the code block as memory here. That's
* correct for addresses in Flash and in [0x0, 0x7FFFFFF]
* (provided that those addresses are aliased to Flash, SRAM, or
* FSMC, depending on BOOT[01] and possibly SYSCFG_MEMRMP). It's
* not correct for other addresses in the code block, but those
* will (hopefully) just fail-fast with transfer or bus errors. If
* lots of people get confused, it might be worth being more
* careful here. */
case STM32_BLOCK_CODE: /* Fall through */
case STM32_BLOCK_SRAM: /* ... */
case STM32_BLOCK_FSMC_1_2: /* ... */
case STM32_BLOCK_FSMC_3_4:
return DMA_ATYPE_MEM;
case STM32_BLOCK_PERIPH:
return DMA_ATYPE_PER;
case STM32_BLOCK_FSMC_REG: /* Fall through */
/* Is this right? I can't think of a reason to DMA into or out
* of the FSMC registers. [mbolivar] */
case STM32_BLOCK_UNUSED: /* ... */
case STM32_BLOCK_CORTEX_INTERNAL: /* ... */
return DMA_ATYPE_OTHER;
default:
ASSERT(0); /* Can't happen */
return DMA_ATYPE_OTHER;
}
}

61
STM32F3/cores/maple/libmaple/dma_private.h
View File

@ -1,61 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
#ifndef _LIBMAPLE_DMA_PRIVATE_H_
#define _LIBMAPLE_DMA_PRIVATE_H_
#include <libmaple/dma.h>
#include <libmaple/libmaple_types.h>
/*
* IRQ handling
*/
/* Wrap this in an ifdef to shut up GCC. (We provide DMA_GET_HANDLER
* in the series support files, which need dma_irq_handler().) */
#ifdef DMA_GET_HANDLER
static __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) {
void (*handler)(void) = DMA_GET_HANDLER(dev, tube);
if (handler) {
handler();
dma_clear_isr_bits(dev, tube); /* in case handler doesn't */
}
}
#endif
/*
* Conveniences for dealing with tube sources/destinations
*/
enum dma_atype {
DMA_ATYPE_MEM,
DMA_ATYPE_PER,
DMA_ATYPE_OTHER,
};
enum dma_atype _dma_addr_type(__IO void *addr);
#endif

101
STM32F3/cores/maple/libmaple/exc.S
View File

@ -1,101 +0,0 @@
/* *****************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
* ****************************************************************************/
# On an exception, push a fake stack thread mode stack frame and redirect
# thread execution to a thread mode error handler
# From RM008:
# The SP is decremented by eight words by the completion of the stack push.
# Figure 5-1 shows the contents of the stack after an exception pre-empts the
# current program flow.
#
# Old SP--> <previous>
# xPSR
# PC
# LR
# r12
# r3
# r2
# r1
# SP--> r0
.text
.globl __exc_hardfault
.globl __exc_nmi
.globl __exc_hardfault
.globl __exc_memmanage
.globl __exc_busfault
.globl __exc_usagefault
.code 16
.thumb_func
__exc_nmi:
mov r0, #1
b __default_exc
.thumb_func
__exc_hardfault:
mov r0, #2
b __default_exc
.thumb_func
__exc_memmanage:
mov r0, #3
b __default_exc
.thumb_func
__exc_busfault:
mov r0, #4
b __default_exc
.thumb_func
__exc_usagefault:
mov r0, #5
b __default_exc
.thumb_func
__default_exc:
ldr r2, NVIC_CCR @ Enable returning to thread mode even if there are
mov r1 ,#1 @ pending exceptions. See flag NONEBASETHRDENA.
str r1, [r2]
cpsid i @ Disable global interrupts
ldr r2, SYSTICK_CSR @ Disable systick handler
mov r1, #0
str r1, [r2]
ldr r1, CPSR_MASK @ Set default CPSR
push {r1}
ldr r1, TARGET_PC @ Set target pc
push {r1}
sub sp, sp, #24 @ Don't care
ldr r1, EXC_RETURN @ Return to thread mode
mov lr, r1
bx lr @ Exception exit
.align 4
CPSR_MASK: .word 0x61000000
EXC_RETURN: .word 0xFFFFFFF9
TARGET_PC: .word __error
NVIC_CCR: .word 0xE000ED14 @ NVIC configuration control register
SYSTICK_CSR: .word 0xE000E010 @ Systick control register

293
STM32F3/cores/maple/libmaple/exti.c
View File

@ -1,293 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
* Copyright (c) 2011, 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/exti.c
* @brief External interrupt control routines
*/
#include <libmaple/exti.h>
#include <libmaple/libmaple.h>
#include <libmaple/nvic.h>
#include <libmaple/bitband.h>
static inline void dispatch_single_exti(uint32 exti_num);
static inline void dispatch_extis(uint32 start, uint32 stop);
/*
* Internal state
*/
typedef struct exti_channel {
void (*handler)(void *);
void *arg;
} exti_channel;
static exti_channel exti_channels[] = {
{ .handler = NULL, .arg = NULL }, // EXTI0
{ .handler = NULL, .arg = NULL }, // EXTI1
{ .handler = NULL, .arg = NULL }, // EXTI2
{ .handler = NULL, .arg = NULL }, // EXTI3
{ .handler = NULL, .arg = NULL }, // EXTI4
{ .handler = NULL, .arg = NULL }, // EXTI5
{ .handler = NULL, .arg = NULL }, // EXTI6
{ .handler = NULL, .arg = NULL }, // EXTI7
{ .handler = NULL, .arg = NULL }, // EXTI8
{ .handler = NULL, .arg = NULL }, // EXTI9
{ .handler = NULL, .arg = NULL }, // EXTI10
{ .handler = NULL, .arg = NULL }, // EXTI11
{ .handler = NULL, .arg = NULL }, // EXTI12
{ .handler = NULL, .arg = NULL }, // EXTI13
{ .handler = NULL, .arg = NULL }, // EXTI14
{ .handler = NULL, .arg = NULL }, // EXTI15
};
/*
* Portable routines
*/
/**
* @brief Register a handler to run upon external interrupt.
*
* This function assumes that the interrupt request corresponding to
* the given external interrupt is masked.
*
* @param num External interrupt line number.
* @param port Port to use as source input for external interrupt.
* @param handler Function handler to execute when interrupt is triggered.
* @param mode Type of transition to trigger on, one of:
* EXTI_RISING, EXTI_FALLING, EXTI_RISING_FALLING.
* @see exti_num
* @see exti_cfg
* @see voidFuncPtr
* @see exti_trigger_mode
*/
void exti_attach_interrupt(exti_num num,
exti_cfg port,
voidFuncPtr handler,
exti_trigger_mode mode) {
// Call callback version with arg being null
exti_attach_callback(num, port, (voidArgumentFuncPtr)handler, NULL, mode);
}
/**
* @brief Register a handler with an argument to run upon external interrupt.
*
* This function assumes that the interrupt request corresponding to
* the given external interrupt is masked.
*
* @param num External interrupt line number.
* @param port Port to use as source input for external interrupt.
* @param handler Function handler to execute when interrupt is triggered.
* @param arg Argument to pass to the interrupt handler.
* @param mode Type of transition to trigger on, one of:
* EXTI_RISING, EXTI_FALLING, EXTI_RISING_FALLING.
* @see exti_num
* @see exti_cfg
* @see voidFuncPtr
* @see exti_trigger_mode
*/
void exti_attach_callback(exti_num num,
exti_cfg port,
voidArgumentFuncPtr handler,
void *arg,
exti_trigger_mode mode) {
ASSERT(handler);
/* Register the handler */
exti_channels[num].handler = handler;
exti_channels[num].arg = arg;
/* Set trigger mode */
switch (mode) {
case EXTI_RISING:
bb_peri_set_bit(&EXTI_BASE->RTSR, num, 1);
break;
case EXTI_FALLING:
bb_peri_set_bit(&EXTI_BASE->FTSR, num, 1);
break;
case EXTI_RISING_FALLING:
bb_peri_set_bit(&EXTI_BASE->RTSR, num, 1);
bb_peri_set_bit(&EXTI_BASE->FTSR, num, 1);
break;
}
/* Use the chip-specific exti_select() to map num to port */
exti_select(num, port);
/* Unmask external interrupt request */
bb_peri_set_bit(&EXTI_BASE->IMR, num, 1);
/* Enable the interrupt line */
switch(num)
{
case EXTI0:
nvic_irq_enable(NVIC_EXTI0);
break;
case EXTI1:
nvic_irq_enable(NVIC_EXTI1);
break;
case EXTI2:
nvic_irq_enable(NVIC_EXTI2);
break;
case EXTI3:
nvic_irq_enable(NVIC_EXTI3);
break;
case EXTI4:
nvic_irq_enable(NVIC_EXTI4);
break;
case EXTI5:
case EXTI6:
case EXTI7:
case EXTI8:
case EXTI9:
nvic_irq_enable(NVIC_EXTI_9_5);
break;
case EXTI10:
case EXTI11:
case EXTI12:
case EXTI13:
case EXTI14:
case EXTI15:
nvic_irq_enable(NVIC_EXTI_15_10);
break;
}
}
/**
* @brief Unregister an external interrupt handler
* @param num External interrupt line to disable.
* @see exti_num
*/
void exti_detach_interrupt(exti_num num) {
/* First, mask the interrupt request */
bb_peri_set_bit(&EXTI_BASE->IMR, num, 0);
/* Then, clear the trigger selection registers */
bb_peri_set_bit(&EXTI_BASE->FTSR, num, 0);
bb_peri_set_bit(&EXTI_BASE->RTSR, num, 0);
/* Finally, unregister the user's handler */
exti_channels[num].handler = NULL;
exti_channels[num].arg = NULL;
}
/*
* Private routines
*/
void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port) {
uint32 shift = 4 * (num % 4);
uint32 cr = *exti_cr;
cr &= ~(0xF << shift);
cr |= port << shift;
*exti_cr = cr;
}
/*
* Interrupt handlers
*/
void __irq_exti0(void) {
dispatch_single_exti(EXTI0);
}
void __irq_exti1(void) {
dispatch_single_exti(EXTI1);
}
void __irq_exti2(void) {
dispatch_single_exti(EXTI2);
// FIXME handle capatitive touch IRQ on F302/303
}
void __irq_exti3(void) {
dispatch_single_exti(EXTI3);
}
void __irq_exti4(void) {
dispatch_single_exti(EXTI4);
}
void __irq_exti9_5(void) {
dispatch_extis(5, 9);
}
void __irq_exti15_10(void) {
dispatch_extis(10, 15);
}
/*
* Auxiliary functions
*/
/* Clear the pending bits for EXTIs whose bits are set in exti_msk.
*
* If a pending bit is cleared as the last instruction in an ISR, it
* won't actually be cleared in time and the ISR will fire again. To
* compensate, this function NOPs for 2 cycles after clearing the
* pending bits to ensure it takes effect. */
static __always_inline void clear_pending_msk(uint32 exti_msk) {
EXTI_BASE->PR = exti_msk;
asm volatile("nop");
asm volatile("nop");
}
/* This dispatch routine is for non-multiplexed EXTI lines only; i.e.,
* it doesn't check EXTI_PR. */
static __always_inline void dispatch_single_exti(uint32 exti) {
voidArgumentFuncPtr handler = exti_channels[exti].handler;
if (!handler) {
return;
}
handler(exti_channels[exti].arg);
clear_pending_msk(1U << exti);
}
/* Dispatch routine for EXTIs which share an IRQ. */
static __always_inline void dispatch_extis(uint32 start, uint32 stop) {
uint32 pr = EXTI_BASE->PR;
uint32 handled_msk = 0;
uint32 exti;
/* Dispatch user handlers for pending EXTIs. */
for (exti = start; exti <= stop; exti++) {
uint32 eb = (1U << exti);
if (pr & eb) {
voidArgumentFuncPtr handler = exti_channels[exti].handler;
if (handler) {
handler(exti_channels[exti].arg);
handled_msk |= eb;
}
}
}
/* Clear the pending bits for handled EXTIs. */
clear_pending_msk(handled_msk);
}

34
STM32F3/cores/maple/libmaple/exti_private.h
View File

@ -1,34 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
#ifndef _LIBMAPLE_EXTI_PRIVATE_H_
#define _LIBMAPLE_EXTI_PRIVATE_H_
#include <libmaple/exti.h>
void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port);
#endif

55
STM32F3/cores/maple/libmaple/flash.c
View File

@ -1,55 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
* Copyright (c) 2011, 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/flash.c
* @brief Flash management functions
*/
#include <libmaple/libmaple_types.h>
#include <libmaple/flash.h>
/**
* @brief Set flash wait states
*
* Note that not all wait states are available on every MCU. See the
* Flash programming manual for your MCU for restrictions on the
* allowed value of wait_states for a given system clock (SYSCLK)
* frequency.
*
* @param wait_states number of wait states (one of
* FLASH_WAIT_STATE_0, FLASH_WAIT_STATE_1,
* ..., FLASH_WAIT_STATE_7).
*/
void flash_set_latency(uint32 wait_states) {
uint32 val = FLASH_BASE->ACR;
val &= ~FLASH_ACR_LATENCY;
val |= wait_states;
FLASH_BASE->ACR = val;
}

50
STM32F3/cores/maple/libmaple/gpio.c
View File

@ -1,50 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 Perry Hung.
* Copyright (c) 2011, 2012 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file libmaple/gpio.c
* @brief Generic STM32 GPIO support.
*/
#include <libmaple/gpio.h>
#include <libmaple/rcc.h>
/*
* GPIO routines
*/
/**
* Initialize a GPIO device.
*
* Enables the clock for and resets the given device.
*
* @param dev GPIO device to initialize.
*/
void gpio_init(gpio_dev *dev) {
rcc_clk_enable(dev->clk_id);
rcc_reset_dev(dev->clk_id);
}

Some files were not shown because too many files have changed in this diff Show More