From 2b6e1398847561b5604b397c245b01535e1168a3 Mon Sep 17 00:00:00 2001 From: lacklustrlabs Date: Fri, 1 Dec 2017 11:43:42 +0100 Subject: [PATCH 1/2] According to STM32F103 RM0008: TIMx_CCMR1::CC2S=01 -> channel is configured as input, IC2 is mapped on TI2. --- STM32F1/system/libmaple/include/libmaple/timer.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/STM32F1/system/libmaple/include/libmaple/timer.h b/STM32F1/system/libmaple/include/libmaple/timer.h index 2c83e5e..ea7484e 100644 --- a/STM32F1/system/libmaple/include/libmaple/timer.h +++ b/STM32F1/system/libmaple/include/libmaple/timer.h @@ -394,8 +394,8 @@ extern timer_dev timer14; #define TIMER_CCMR1_IC2PSC (0x3 << 10) #define TIMER_CCMR1_CC2S (0x3 << 8) #define TIMER_CCMR1_CC2S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) -#define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI1 << 8) -#define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI2 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI1 << 8) #define TIMER_CCMR1_CC2S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) #define TIMER_CCMR1_OC1CE (1U << TIMER_CCMR1_OC1CE_BIT) #define TIMER_CCMR1_OC1M (0x3 << 4) From 388995efbba555b742ba7652399c05c1ce1678d3 Mon Sep 17 00:00:00 2001 From: lacklustrlabs Date: Fri, 1 Dec 2017 15:55:27 +0100 Subject: [PATCH 2/2] Adhere to the format of #323 --- STM32F1/system/libmaple/include/libmaple/timer.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/STM32F1/system/libmaple/include/libmaple/timer.h b/STM32F1/system/libmaple/include/libmaple/timer.h index ea7484e..64f458f 100644 --- a/STM32F1/system/libmaple/include/libmaple/timer.h +++ b/STM32F1/system/libmaple/include/libmaple/timer.h @@ -393,10 +393,10 @@ extern timer_dev timer14; #define TIMER_CCMR1_OC2FE (1U << TIMER_CCMR1_OC2FE_BIT) #define TIMER_CCMR1_IC2PSC (0x3 << 10) #define TIMER_CCMR1_CC2S (0x3 << 8) -#define TIMER_CCMR1_CC2S_OUTPUT (TIMER_CCMR_CCS_OUTPUT << 8) -#define TIMER_CCMR1_CC2S_INPUT_TI1 (TIMER_CCMR_CCS_INPUT_TI2 << 8) -#define TIMER_CCMR1_CC2S_INPUT_TI2 (TIMER_CCMR_CCS_INPUT_TI1 << 8) -#define TIMER_CCMR1_CC2S_INPUT_TRC (TIMER_CCMR_CCS_INPUT_TRC << 8) +#define TIMER_CCMR1_CC2S_OUTPUT (0x0 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI2 (0x1 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TI1 (0x2 << 8) +#define TIMER_CCMR1_CC2S_INPUT_TRC (0x3 << 8) #define TIMER_CCMR1_OC1CE (1U << TIMER_CCMR1_OC1CE_BIT) #define TIMER_CCMR1_OC1M (0x3 << 4) #define TIMER_CCMR1_IC1F (0xF << 4)