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Merge branch 'aster94-master'

This commit is contained in:
Roger Clark 2018-04-01 15:03:36 +10:00
parent 178cd5529e eede5aba0e
commit 845508ee19
118 changed files with 1256 additions and 1252 deletions
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4
STM32F1/cores/maple/libmaple/adc_f1.c
View File

@ -175,8 +175,8 @@ void adc_attach_interrupt(adc_dev *dev,
* @param dev adc device
*/
void adc_calibrate(adc_dev *dev) {
__io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
__io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
__IO uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
__IO uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
*rstcal_bit = 1;
while (*rstcal_bit)

8
STM32F1/cores/maple/libmaple/bkp_f1.c
View File

@ -34,7 +34,7 @@
#include <libmaple/rcc.h>
#include <libmaple/bitband.h>
static inline __io uint32* data_register(uint8 reg);
static inline __IO uint32* data_register(uint8 reg);
bkp_dev bkp = {
.regs = BKP_BASE,
@ -78,7 +78,7 @@ void bkp_disable_writes(void) {
* medium-density devices, 42 on high-density devices).
*/
uint16 bkp_read(uint8 reg) {
__io uint32* dr = data_register(reg);
__IO uint32* dr = data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return 0;
@ -97,7 +97,7 @@ uint16 bkp_read(uint8 reg) {
* @see bkp_enable_writes()
*/
void bkp_write(uint8 reg, uint16 val) {
__io uint32* dr = data_register(reg);
__IO uint32* dr = data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return;
@ -112,7 +112,7 @@ void bkp_write(uint8 reg, uint16 val) {
*/
#define NR_LOW_DRS 10
static inline __io uint32* data_register(uint8 reg) {
static inline __IO uint32* data_register(uint8 reg) {
if (reg < 1 || reg > BKP_NR_DATA_REGS) {
return 0;
}

2
STM32F1/cores/maple/libmaple/dma.c
View File

@ -52,7 +52,7 @@ void dma_init(dma_dev *dev) {
* Private API
*/
enum dma_atype _dma_addr_type(__io void *addr) {
enum dma_atype _dma_addr_type(__IO void *addr) {
switch (stm32_block_purpose((void*)addr)) {
/* Notice we're treating the code block as memory here. That's
* correct for addresses in Flash and in [0x0, 0x7FFFFFF]

10
STM32F1/cores/maple/libmaple/dma_f1.c
View File

@ -86,7 +86,7 @@ static int cfg_dev_ok(dma_dev *dev, dma_tube_config *cfg) {
}
/* Is addr acceptable for use as DMA src/dst? */
static int cfg_mem_ok(__io void *addr) {
static int cfg_mem_ok(__IO void *addr) {
enum dma_atype atype = _dma_addr_type(addr);
return atype == DMA_ATYPE_MEM || atype == DMA_ATYPE_PER;
}
@ -293,7 +293,7 @@ dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
return DMA_TRANSFER_ERROR;
}
void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __IO void *addr) {
dma_channel_reg_map *chan_regs;
ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
@ -302,7 +302,7 @@ void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
chan_regs->CMAR = (uint32)addr;
}
void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
void dma_set_per_addr(dma_dev *dev, dma_channel channel, __IO void *addr) {
dma_channel_reg_map *chan_regs;
ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
@ -343,9 +343,9 @@ void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
*/
void dma_setup_transfer(dma_dev *dev,
dma_channel channel,
__io void *peripheral_address,
__IO void *peripheral_address,
dma_xfer_size peripheral_size,
__io void *memory_address,
__IO void *memory_address,
dma_xfer_size memory_size,
uint32 mode) {
dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);

2
STM32F1/cores/maple/libmaple/exti.c
View File

@ -200,7 +200,7 @@ void exti_detach_interrupt(exti_num num) {
* Private routines
*/
void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port) {
void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port) {
uint32 shift = 4 * (num % 4);
uint32 cr = *exti_cr;
cr &= ~(0xF << shift);

4
STM32F1/cores/maple/libmaple/gpio_f1.c
View File

@ -123,7 +123,7 @@ void gpio_init_all(void) {
*/
void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
gpio_reg_map *regs = dev->regs;
__io uint32 *cr = &regs->CRL + (pin >> 3);
__IO uint32 *cr = &regs->CRL + (pin >> 3);
uint32 shift = (pin & 0x7) * 4;
uint32 tmp = *cr;
@ -140,7 +140,7 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
gpio_pin_mode gpio_get_mode(gpio_dev *dev, uint8 pin) {
gpio_reg_map *regs = dev->regs;
__io uint32 *cr = &regs->CRL + (pin >> 3);
__IO uint32 *cr = &regs->CRL + (pin >> 3);
uint32 shift = (pin & 0x7) * 4;
uint32 crMode = (*cr>>shift) & 0x0F;

4
STM32F1/cores/maple/libmaple/rcc.c
View File

@ -94,8 +94,8 @@ void rcc_switch_sysclk(rcc_sysclk_src sysclk_src) {
* won't work for you. */
/* Returns the RCC register which controls the clock source. */
static inline __io uint32* rcc_clk_reg(rcc_clk clock) {
return (__io uint32*)((__io uint8*)RCC_BASE + (clock >> 8));
static inline __IO uint32* rcc_clk_reg(rcc_clk clock) {
return (__IO uint32*)((__IO uint8*)RCC_BASE + (clock >> 8));
}
/* Returns a mask in rcc_clk_reg(clock) to be used for turning the

6
STM32F1/cores/maple/libmaple/rcc_f1.c
View File

@ -136,7 +136,7 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
}
void rcc_clk_enable(rcc_clk_id id) {
static __io uint32* enable_regs[] = {
static __IO uint32* enable_regs[] = {
[APB1] = &RCC_BASE->APB1ENR,
[APB2] = &RCC_BASE->APB2ENR,
[AHB] = &RCC_BASE->AHBENR,
@ -145,7 +145,7 @@ void rcc_clk_enable(rcc_clk_id id) {
}
void rcc_reset_dev(rcc_clk_id id) {
static __io uint32* reset_regs[] = {
static __IO uint32* reset_regs[] = {
[APB1] = &RCC_BASE->APB1RSTR,
[APB2] = &RCC_BASE->APB2RSTR,
};
@ -164,7 +164,7 @@ void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
}
void rcc_clk_disable(rcc_clk_id id) {
static __io uint32* enable_regs[] = {
static __IO uint32* enable_regs[] = {
[APB1] = &RCC_BASE->APB1ENR,
[APB2] = &RCC_BASE->APB2ENR,
[AHB] = &RCC_BASE->AHBENR,

2
STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
View File

@ -33,7 +33,7 @@ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
// pulse width measuring loop and achieve finer resolution. calling
// digitalRead() instead yields much coarser resolution.
__io uint32_t * const idr = portInputRegister(digitalPinToPort(pin));
__IO uint32_t * const idr = portInputRegister(digitalPinToPort(pin));
const uint32_t bit = digitalPinToBitMask(pin);
const uint32_t stateMask = (state ? bit:0);

4
STM32F1/libraries/A_STM32_Examples/keywords.txt
View File

@ -10,3 +10,7 @@
# Constants (LITERAL1)
#######################################
OUTPUT_OPEN_DRAIN LITERAL1
INPUT_ANALOG LITERAL1
INPUT_PULLDOWN LITERAL1
PWM LITERAL1

42
STM32F1/libraries/EEPROM/EEPROM.cpp
View File

@ -13,10 +13,10 @@ uint16 EEPROMClass::EE_CheckPage(uint32 pageBase, uint16 status)
uint32 pageEnd = pageBase + (uint32)PageSize;
// Page Status not EEPROM_ERASED and not a "state"
if ((*(__io uint16*)pageBase) != EEPROM_ERASED && (*(__io uint16*)pageBase) != status)
if ((*(__IO uint16*)pageBase) != EEPROM_ERASED && (*(__IO uint16*)pageBase) != status)
return EEPROM_BAD_FLASH;
for(pageBase += 4; pageBase < pageEnd; pageBase += 4)
if ((*(__io uint32*)pageBase) != 0xFFFFFFFF) // Verify if slot is empty
if ((*(__IO uint32*)pageBase) != 0xFFFFFFFF) // Verify if slot is empty
return EEPROM_BAD_FLASH;
return EEPROM_OK;
}
@ -31,9 +31,9 @@ uint16 EEPROMClass::EE_CheckPage(uint32 pageBase, uint16 status)
FLASH_Status EEPROMClass::EE_ErasePage(uint32 pageBase)
{
FLASH_Status FlashStatus;
uint16 data = (*(__io uint16*)(pageBase));
uint16 data = (*(__IO uint16*)(pageBase));
if ((data == EEPROM_ERASED) || (data == EEPROM_VALID_PAGE) || (data == EEPROM_RECEIVE_DATA))
data = (*(__io uint16*)(pageBase + 2)) + 1;
data = (*(__IO uint16*)(pageBase + 2)) + 1;
else
data = 0;
@ -73,8 +73,8 @@ uint16 EEPROMClass::EE_CheckErasePage(uint32 pageBase, uint16 status)
*/
uint32 EEPROMClass::EE_FindValidPage(void)
{
uint16 status0 = (*(__io uint16*)PageBase0); // Get Page0 actual status
uint16 status1 = (*(__io uint16*)PageBase1); // Get Page1 actual status
uint16 status0 = (*(__IO uint16*)PageBase0); // Get Page0 actual status
uint16 status1 = (*(__IO uint16*)PageBase1); // Get Page1 actual status
if (status0 == EEPROM_VALID_PAGE && status1 == EEPROM_ERASED)
return PageBase0;
@ -100,14 +100,14 @@ uint16 EEPROMClass::EE_GetVariablesCount(uint32 pageBase, uint16 skipAddress)
for (pageBase += 6; pageBase < pageEnd; pageBase += 4)
{
varAddress = (*(__io uint16*)pageBase);
varAddress = (*(__IO uint16*)pageBase);
if (varAddress == 0xFFFF || varAddress == skipAddress)
continue;
count++;
for(idx = pageBase + 4; idx < pageEnd; idx += 4)
{
nextAddress = (*(__io uint16*)idx);
nextAddress = (*(__IO uint16*)idx);
if (nextAddress == varAddress)
{
count--;
@ -140,7 +140,7 @@ uint16 EEPROMClass::EE_PageTransfer(uint32 newPage, uint32 oldPage, uint16 SkipA
// Find first free element in new page
for (newIdx = newPage + 4; newIdx < newEnd; newIdx += 4)
if ((*(__io uint32*)newIdx) == 0xFFFFFFFF) // Verify if element
if ((*(__IO uint32*)newIdx) == 0xFFFFFFFF) // Verify if element
break; // contents are 0xFFFFFFFF
if (newIdx >= newEnd)
return EEPROM_OUT_SIZE;
@ -150,13 +150,13 @@ uint16 EEPROMClass::EE_PageTransfer(uint32 newPage, uint32 oldPage, uint16 SkipA
for (; oldIdx > oldEnd; oldIdx -= 4)
{
address = *(__io uint16*)oldIdx;
address = *(__IO uint16*)oldIdx;
if (address == 0xFFFF || address == SkipAddress)
continue; // it's means that power off after write data
found = 0;
for (idx = newPage + 6; idx < newIdx; idx += 4)
if ((*(__io uint16*)(idx)) == address)
if ((*(__IO uint16*)(idx)) == address)
{
found = 1;
break;
@ -167,7 +167,7 @@ uint16 EEPROMClass::EE_PageTransfer(uint32 newPage, uint32 oldPage, uint16 SkipA
if (newIdx < newEnd)
{
data = (*(__io uint16*)(oldIdx - 2));
data = (*(__IO uint16*)(oldIdx - 2));
FlashStatus = FLASH_ProgramHalfWord(newIdx, data);
if (FlashStatus != FLASH_COMPLETE)
@ -223,9 +223,9 @@ uint16 EEPROMClass::EE_VerifyPageFullWriteVariable(uint16 Address, uint16 Data)
for (idx = pageEnd - 2; idx > pageBase; idx -= 4)
{
if ((*(__io uint16*)idx) == Address) // Find last value for address
if ((*(__IO uint16*)idx) == Address) // Find last value for address
{
count = (*(__io uint16*)(idx - 2)); // Read last data
count = (*(__IO uint16*)(idx - 2)); // Read last data
if (count == Data)
return EEPROM_OK;
if (count == 0xFFFF)
@ -240,7 +240,7 @@ uint16 EEPROMClass::EE_VerifyPageFullWriteVariable(uint16 Address, uint16 Data)
// Check each active page address starting from begining
for (idx = pageBase + 4; idx < pageEnd; idx += 4)
if ((*(__io uint32*)idx) == 0xFFFFFFFF) // Verify if element
if ((*(__IO uint32*)idx) == 0xFFFFFFFF) // Verify if element
{ // contents are 0xFFFFFFFF
FlashStatus = FLASH_ProgramHalfWord(idx, Data); // Set variable data
if (FlashStatus != FLASH_COMPLETE)
@ -303,8 +303,8 @@ uint16 EEPROMClass::init(void)
FLASH_Unlock();
Status = EEPROM_NO_VALID_PAGE;
status0 = (*(__io uint16 *)PageBase0);
status1 = (*(__io uint16 *)PageBase1);
status0 = (*(__IO uint16 *)PageBase0);
status1 = (*(__IO uint16 *)PageBase1);
switch (status0)
{
@ -407,7 +407,7 @@ uint16 EEPROMClass::format(void)
status = EE_CheckErasePage(PageBase0, EEPROM_VALID_PAGE);
if (status != EEPROM_OK)
return status;
if ((*(__io uint16*)PageBase0) == EEPROM_ERASED)
if ((*(__IO uint16*)PageBase0) == EEPROM_ERASED)
{
// Set Page0 as valid page: Write VALID_PAGE at Page0 base address
FlashStatus = FLASH_ProgramHalfWord(PageBase0, EEPROM_VALID_PAGE);
@ -437,7 +437,7 @@ uint16 EEPROMClass::erases(uint16 *Erases)
if (pageBase == 0)
return EEPROM_NO_VALID_PAGE;
*Erases = (*(__io uint16*)pageBase+2);
*Erases = (*(__IO uint16*)pageBase+2);
return EEPROM_OK;
}
@ -485,9 +485,9 @@ uint16 EEPROMClass::read(uint16 Address, uint16 *Data)
// Check each active page address starting from end
for (pageBase += 6; pageEnd >= pageBase; pageEnd -= 4)
if ((*(__io uint16*)pageEnd) == Address) // Compare the read address with the virtual address
if ((*(__IO uint16*)pageEnd) == Address) // Compare the read address with the virtual address
{
*Data = (*(__io uint16*)(pageEnd - 2)); // Get content of Address-2 which is variable value
*Data = (*(__IO uint16*)(pageEnd - 2)); // Get content of Address-2 which is variable value
return EEPROM_OK;
}

4
STM32F1/libraries/EEPROM/flash_stm32.c
View File

@ -17,7 +17,7 @@
*/
static void delay(void)
{
__io uint32 i = 0;
__IO uint32 i = 0;
for(i = 0xFF; i != 0; i--) { }
}
@ -122,7 +122,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32 Address, uint16 Data)
{
/* if the previous operation is completed, proceed to program the new data */
FLASH_BASE->CR |= FLASH_CR_PG;
*(__io uint16*)Address = Data;
*(__IO uint16*)Address = Data;
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)

20
STM32F1/libraries/RTClock/src/utility/rtc_util.h
View File

@ -52,16 +52,16 @@ extern "C" {
#endif
typedef struct rtc_reg_map {
__io uint32 CRH; /**< Control register high */
__io uint32 CRL; /**< Control register high */
__io uint32 PRLH; /**< Prescaler load register high */
__io uint32 PRLL; /**< Prescaler load register low */
__io uint32 DIVH; /**< Prescaler divider register high */
__io uint32 DIVL; /**< Prescaler divider register low */
__io uint32 CNTH; /**< Counter register high */
__io uint32 CNTL; /**< Counter register low */
__io uint32 ALRH; /**< Alarm register high */
__io uint32 ALRL; /**< Alarm register low */
__IO uint32 CRH; /**< Control register high */
__IO uint32 CRL; /**< Control register high */
__IO uint32 PRLH; /**< Prescaler load register high */
__IO uint32 PRLL; /**< Prescaler load register low */
__IO uint32 DIVH; /**< Prescaler divider register high */
__IO uint32 DIVL; /**< Prescaler divider register low */
__IO uint32 CNTH; /**< Counter register high */
__IO uint32 CNTL; /**< Counter register low */
__IO uint32 ALRH; /**< Alarm register high */
__IO uint32 ALRL; /**< Alarm register low */
} rtc_reg_map;
/** RTC register map base pointer */

18
STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h
View File

@ -84,15 +84,15 @@ extern "C" {
/** I2C register map type */
typedef struct i2c_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 OAR1; /**< Own address register 1 */
__io uint32 OAR2; /**< Own address register 2 */
__io uint32 DR; /**< Data register */
__io uint32 SR1; /**< Status register 1 */
__io uint32 SR2; /**< Status register 2 */
__io uint32 CCR; /**< Clock control register */
__io uint32 TRISE; /**< TRISE (rise time) register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 OAR1; /**< Own address register 1 */
__IO uint32 OAR2; /**< Own address register 2 */
__IO uint32 DR; /**< Data register */
__IO uint32 SR1; /**< Status register 1 */
__IO uint32 SR2; /**< Status register 2 */
__IO uint32 CCR; /**< Clock control register */
__IO uint32 TRISE; /**< TRISE (rise time) register */
} i2c_reg_map;
/**

2
STM32F1/system/libmaple/dma_private.h
View File

@ -57,6 +57,6 @@ enum dma_atype {
DMA_ATYPE_OTHER,
};
enum dma_atype _dma_addr_type(__io void *addr);
enum dma_atype _dma_addr_type(__IO void *addr);
#endif

2
STM32F1/system/libmaple/exti_private.h
View File

@ -29,6 +29,6 @@
#include <libmaple/exti.h>
void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port);
void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port);
#endif

40
STM32F1/system/libmaple/include/libmaple/adc.h
View File

@ -52,26 +52,26 @@ extern "C"{
/** ADC register map type. */
typedef struct adc_reg_map {
__io uint32 SR; ///< Status register
__io uint32 CR1; ///< Control register 1
__io uint32 CR2; ///< Control register 2
__io uint32 SMPR1; ///< Sample time register 1
__io uint32 SMPR2; ///< Sample time register 2
__io uint32 JOFR1; ///< Injected channel data offset register 1
__io uint32 JOFR2; ///< Injected channel data offset register 2
__io uint32 JOFR3; ///< Injected channel data offset register 3
__io uint32 JOFR4; ///< Injected channel data offset register 4
__io uint32 HTR; ///< Watchdog high threshold register
__io uint32 LTR; ///< Watchdog low threshold register
__io uint32 SQR1; ///< Regular sequence register 1
__io uint32 SQR2; ///< Regular sequence register 2
__io uint32 SQR3; ///< Regular sequence register 3
__io uint32 JSQR; ///< Injected sequence register
__io uint32 JDR1; ///< Injected data register 1
__io uint32 JDR2; ///< Injected data register 2
__io uint32 JDR3; ///< Injected data register 3
__io uint32 JDR4; ///< Injected data register 4
__io uint32 DR; ///< Regular data register
__IO uint32 SR; ///< Status register
__IO uint32 CR1; ///< Control register 1
__IO uint32 CR2; ///< Control register 2
__IO uint32 SMPR1; ///< Sample time register 1
__IO uint32 SMPR2; ///< Sample time register 2
__IO uint32 JOFR1; ///< Injected channel data offset register 1
__IO uint32 JOFR2; ///< Injected channel data offset register 2
__IO uint32 JOFR3; ///< Injected channel data offset register 3
__IO uint32 JOFR4; ///< Injected channel data offset register 4
__IO uint32 HTR; ///< Watchdog high threshold register
__IO uint32 LTR; ///< Watchdog low threshold register
__IO uint32 SQR1; ///< Regular sequence register 1
__IO uint32 SQR2; ///< Regular sequence register 2
__IO uint32 SQR3; ///< Regular sequence register 3
__IO uint32 JSQR; ///< Injected sequence register
__IO uint32 JDR1; ///< Injected data register 1
__IO uint32 JDR2; ///< Injected data register 2
__IO uint32 JDR3; ///< Injected data register 3
__IO uint32 JDR4; ///< Injected data register 4
__IO uint32 DR; ///< Regular data register
} adc_reg_map;

90
STM32F1/system/libmaple/include/libmaple/bkp.h
View File

@ -47,54 +47,54 @@ extern "C" {
/** Backup peripheral register map type. */
typedef struct bkp_reg_map {
const uint32 RESERVED1; ///< Reserved
__io uint32 DR1; ///< Data register 1
__io uint32 DR2; ///< Data register 2
__io uint32 DR3; ///< Data register 3
__io uint32 DR4; ///< Data register 4
__io uint32 DR5; ///< Data register 5
__io uint32 DR6; ///< Data register 6
__io uint32 DR7; ///< Data register 7
__io uint32 DR8; ///< Data register 8
__io uint32 DR9; ///< Data register 9
__io uint32 DR10; ///< Data register 10
__io uint32 RTCCR; ///< RTC control register
__io uint32 CR; ///< Control register
__io uint32 CSR; ///< Control and status register
__IO uint32 DR1; ///< Data register 1
__IO uint32 DR2; ///< Data register 2
__IO uint32 DR3; ///< Data register 3
__IO uint32 DR4; ///< Data register 4
__IO uint32 DR5; ///< Data register 5
__IO uint32 DR6; ///< Data register 6
__IO uint32 DR7; ///< Data register 7
__IO uint32 DR8; ///< Data register 8
__IO uint32 DR9; ///< Data register 9
__IO uint32 DR10; ///< Data register 10
__IO uint32 RTCCR; ///< RTC control register
__IO uint32 CR; ///< Control register
__IO uint32 CSR; ///< Control and status register
#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
const uint32 RESERVED2; ///< Reserved
const uint32 RESERVED3; ///< Reserved
__io uint32 DR11; ///< Data register 11
__io uint32 DR12; ///< Data register 12
__io uint32 DR13; ///< Data register 13
__io uint32 DR14; ///< Data register 14
__io uint32 DR15; ///< Data register 15
__io uint32 DR16; ///< Data register 16
__io uint32 DR17; ///< Data register 17
__io uint32 DR18; ///< Data register 18
__io uint32 DR19; ///< Data register 19
__io uint32 DR20; ///< Data register 20
__io uint32 DR21; ///< Data register 21
__io uint32 DR22; ///< Data register 22
__io uint32 DR23; ///< Data register 23
__io uint32 DR24; ///< Data register 24
__io uint32 DR25; ///< Data register 25
__io uint32 DR26; ///< Data register 26
__io uint32 DR27; ///< Data register 27
__io uint32 DR28; ///< Data register 28
__io uint32 DR29; ///< Data register 29
__io uint32 DR30; ///< Data register 30
__io uint32 DR31; ///< Data register 31
__io uint32 DR32; ///< Data register 32
__io uint32 DR33; ///< Data register 33
__io uint32 DR34; ///< Data register 34
__io uint32 DR35; ///< Data register 35
__io uint32 DR36; ///< Data register 36
__io uint32 DR37; ///< Data register 37
__io uint32 DR38; ///< Data register 38
__io uint32 DR39; ///< Data register 39
__io uint32 DR40; ///< Data register 40
__io uint32 DR41; ///< Data register 41
__io uint32 DR42; ///< Data register 42
__IO uint32 DR11; ///< Data register 11
__IO uint32 DR12; ///< Data register 12
__IO uint32 DR13; ///< Data register 13
__IO uint32 DR14; ///< Data register 14
__IO uint32 DR15; ///< Data register 15
__IO uint32 DR16; ///< Data register 16
__IO uint32 DR17; ///< Data register 17
__IO uint32 DR18; ///< Data register 18
__IO uint32 DR19; ///< Data register 19
__IO uint32 DR20; ///< Data register 20
__IO uint32 DR21; ///< Data register 21
__IO uint32 DR22; ///< Data register 22
__IO uint32 DR23; ///< Data register 23
__IO uint32 DR24; ///< Data register 24
__IO uint32 DR25; ///< Data register 25
__IO uint32 DR26; ///< Data register 26
__IO uint32 DR27; ///< Data register 27
__IO uint32 DR28; ///< Data register 28
__IO uint32 DR29; ///< Data register 29
__IO uint32 DR30; ///< Data register 30
__IO uint32 DR31; ///< Data register 31
__IO uint32 DR32; ///< Data register 32
__IO uint32 DR33; ///< Data register 33
__IO uint32 DR34; ///< Data register 34
__IO uint32 DR35; ///< Data register 35
__IO uint32 DR36; ///< Data register 36
__IO uint32 DR37; ///< Data register 37
__IO uint32 DR38; ///< Data register 38
__IO uint32 DR39; ///< Data register 39
__IO uint32 DR40; ///< Data register 40
__IO uint32 DR41; ///< Data register 41
__IO uint32 DR42; ///< Data register 42
#endif
} bkp_reg_map;

8
STM32F1/system/libmaple/include/libmaple/dma.h
View File

@ -139,12 +139,12 @@ void dma_init(dma_dev *dev);
*/
typedef struct dma_tube_config {
/** Source of data */
__io void *tube_src;
__IO void *tube_src;
/** Source transfer size */
dma_xfer_size tube_src_size;
/** Destination of data */
__io void *tube_dst;
__IO void *tube_dst;
/** Destination transfer size */
dma_xfer_size tube_dst_size;
@ -283,7 +283,7 @@ extern void dma_set_num_transfers(dma_dev *dev, dma_tube tube,
* @param tube Tube whose base memory address to set.
* @param address Memory base address to use.
*/
extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *address);
extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __IO void *address);
/**
* @brief Set the base peripheral address where data will be read from
@ -299,7 +299,7 @@ extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *address);
* @param tube Tube whose peripheral data register base address to set.
* @param address Peripheral memory base address to use.
*/
extern void dma_set_per_addr(dma_dev *dev, dma_tube tube, __io void *address);
extern void dma_set_per_addr(dma_dev *dev, dma_tube tube, __IO void *address);
/* Interrupt handling */

12
STM32F1/system/libmaple/include/libmaple/exti.h
View File

@ -48,12 +48,12 @@ extern "C"{
/** EXTI register map type */
typedef struct exti_reg_map {
__io uint32 IMR; /**< Interrupt mask register */
__io uint32 EMR; /**< Event mask register */
__io uint32 RTSR; /**< Rising trigger selection register */
__io uint32 FTSR; /**< Falling trigger selection register */
__io uint32 SWIER; /**< Software interrupt event register */
__io uint32 PR; /**< Pending register */
__IO uint32 IMR; /**< Interrupt mask register */
__IO uint32 EMR; /**< Event mask register */
__IO uint32 RTSR; /**< Rising trigger selection register */
__IO uint32 FTSR; /**< Falling trigger selection register */
__IO uint32 SWIER; /**< Software interrupt event register */
__IO uint32 PR; /**< Pending register */
} exti_reg_map;
/*

60
STM32F1/system/libmaple/include/libmaple/fsmc.h
View File

@ -53,42 +53,42 @@ extern "C"{
/** FSMC register map type */
typedef struct fsmc_reg_map {
__io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
__io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
__io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
__io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
__io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
__io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
__io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
__io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
__IO uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
__IO uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
__IO uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
__IO uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
__IO uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
__IO uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
__IO uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
__IO uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
const uint8 RESERVED1[64]; /**< Reserved */
__io uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
__io uint32 SR2; /**< FIFO status and interrupt register 2 */
__io uint32 PMEM2; /**< Common memory space timing register 2 */
__io uint32 PATT2; /**< Attribute memory space timing register 2 */
__IO uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
__IO uint32 SR2; /**< FIFO status and interrupt register 2 */
__IO uint32 PMEM2; /**< Common memory space timing register 2 */
__IO uint32 PATT2; /**< Attribute memory space timing register 2 */
const uint8 RESERVED2[4]; /**< Reserved */
__io uint32 ECCR2; /**< ECC result register 2 */
__IO uint32 ECCR2; /**< ECC result register 2 */
const uint8 RESERVED3[2];
__io uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
__io uint32 SR3; /**< FIFO status and interrupt register 3 */
__io uint32 PMEM3; /**< Common memory space timing register 3 */
__io uint32 PATT3; /**< Attribute memory space timing register 3 */
__IO uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
__IO uint32 SR3; /**< FIFO status and interrupt register 3 */
__IO uint32 PMEM3; /**< Common memory space timing register 3 */
__IO uint32 PATT3; /**< Attribute memory space timing register 3 */
const uint32 RESERVED4; /**< Reserved */
__io uint32 ECCR3; /**< ECC result register 3 */
__IO uint32 ECCR3; /**< ECC result register 3 */
const uint8 RESERVED5[8]; /**< Reserved */
__io uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
__io uint32 SR4; /**< FIFO status and interrupt register 4 */
__io uint32 PMEM4; /**< Common memory space timing register 4 */
__io uint32 PATT4; /**< Attribute memory space timing register 4 */
__io uint32 PIO4; /**< I/O space timing register 4 */
__IO uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
__IO uint32 SR4; /**< FIFO status and interrupt register 4 */
__IO uint32 PMEM4; /**< Common memory space timing register 4 */
__IO uint32 PATT4; /**< Attribute memory space timing register 4 */
__IO uint32 PIO4; /**< I/O space timing register 4 */
const uint8 RESERVED6[80]; /**< Reserved */
__io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
__IO uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
const uint32 RESERVED7; /**< Reserved */
__io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
__IO uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
const uint32 RESERVED8; /**< Reserved */
__io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
__IO uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
const uint32 RESERVED9; /**< Reserved */
__io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
__IO uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
} __attribute__((packed)) fsmc_reg_map;
#define __FSMCB 0xA0000000
@ -98,10 +98,10 @@ typedef struct fsmc_reg_map {
/** FSMC NOR/PSRAM register map type */
typedef struct fsmc_nor_psram_reg_map {
__io uint32 BCR; /**< Chip-select control register */
__io uint32 BTR; /**< Chip-select timing register */
__IO uint32 BCR; /**< Chip-select control register */
__IO uint32 BTR; /**< Chip-select timing register */
const uint8 RESERVED[252]; /**< Reserved */
__io uint32 BWTR; /**< Write timing register */
__IO uint32 BWTR; /**< Write timing register */
} fsmc_nor_psram_reg_map;
/** FSMC NOR/PSRAM base pointer 1 */

18
STM32F1/system/libmaple/include/libmaple/i2c.h
View File

@ -75,15 +75,15 @@ extern "C" {
/** I2C register map type */
typedef struct i2c_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 OAR1; /**< Own address register 1 */
__io uint32 OAR2; /**< Own address register 2 */
__io uint32 DR; /**< Data register */
__io uint32 SR1; /**< Status register 1 */
__io uint32 SR2; /**< Status register 2 */
__io uint32 CCR; /**< Clock control register */
__io uint32 TRISE; /**< TRISE (rise time) register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 OAR1; /**< Own address register 1 */
__IO uint32 OAR2; /**< Own address register 2 */
__IO uint32 DR; /**< Data register */
__IO uint32 SR1; /**< Status register 1 */
__IO uint32 SR2; /**< Status register 2 */
__IO uint32 CCR; /**< Clock control register */
__IO uint32 TRISE; /**< TRISE (rise time) register */
} i2c_reg_map;
/**

8
STM32F1/system/libmaple/include/libmaple/iwdg.h
View File

@ -53,10 +53,10 @@ extern "C"{
/** Independent watchdog register map type. */
typedef struct iwdg_reg_map {
__io uint32 KR; /**< Key register. */
__io uint32 PR; /**< Prescaler register. */
__io uint32 RLR; /**< Reload register. */
__io uint32 SR; /**< Status register */
__IO uint32 KR; /**< Key register. */
__IO uint32 PR; /**< Prescaler register. */
__IO uint32 RLR; /**< Reload register. */
__IO uint32 SR; /**< Status register */
} iwdg_reg_map;
/** Independent watchdog base pointer */

2
STM32F1/system/libmaple/include/libmaple/libmaple_types.h
View File

@ -52,7 +52,7 @@ typedef long long int64;
typedef void (*voidFuncPtr)(void);
typedef void (*voidArgumentFuncPtr)(void *);
#define __io volatile
#define __IO volatile
#define __attr_flash __attribute__((section (".USER_FLASH")))
#define __packed __attribute__((__packed__))
#define __deprecated __attribute__((__deprecated__))

14
STM32F1/system/libmaple/include/libmaple/nvic.h
View File

@ -55,31 +55,31 @@ extern "C"{
/** NVIC register map type. */
typedef struct nvic_reg_map {
__io uint32 ISER[8]; /**< Interrupt Set Enable Registers */
__IO uint32 ISER[8]; /**< Interrupt Set Enable Registers */
/** Reserved */
uint32 RESERVED0[24];
__io uint32 ICER[8]; /**< Interrupt Clear Enable Registers */
__IO uint32 ICER[8]; /**< Interrupt Clear Enable Registers */
/** Reserved */
uint32 RESERVED1[24];
__io uint32 ISPR[8]; /**< Interrupt Set Pending Registers */
__IO uint32 ISPR[8]; /**< Interrupt Set Pending Registers */
/** Reserved */
uint32 RESERVED2[24];
__io uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */
__IO uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */
/** Reserved */
uint32 RESERVED3[24];
__io uint32 IABR[8]; /**< Interrupt Active bit Registers */
__IO uint32 IABR[8]; /**< Interrupt Active bit Registers */
/** Reserved */
uint32 RESERVED4[56];
__io uint8 IP[240]; /**< Interrupt Priority Registers */
__IO uint8 IP[240]; /**< Interrupt Priority Registers */
/** Reserved */
uint32 RESERVED5[644];
__io uint32 STIR; /**< Software Trigger Interrupt Registers */
__IO uint32 STIR; /**< Software Trigger Interrupt Registers */
} nvic_reg_map;
/** NVIC register map base pointer. */

4
STM32F1/system/libmaple/include/libmaple/pwr.h
View File

@ -43,8 +43,8 @@ extern "C" {
/** Power interface register map. */
typedef struct pwr_reg_map {
__io uint32 CR; /**< Control register */
__io uint32 CSR; /**< Control and status register */
__IO uint32 CR; /**< Control register */
__IO uint32 CSR; /**< Control and status register */
} pwr_reg_map;
/** Power peripheral register map base pointer. */

2
STM32F1/system/libmaple/include/libmaple/ring_buffer.h
View File

@ -81,7 +81,7 @@ static inline void rb_init(ring_buffer *rb, uint16 size, uint8 *buf) {
* @param rb Buffer whose elements to count.
*/
static inline uint16 rb_full_count(ring_buffer *rb) {
__io ring_buffer *arb = rb;
__IO ring_buffer *arb = rb;
int32 size = arb->tail - arb->head;
if (arb->tail < arb->head) {
size += arb->size + 1;

38
STM32F1/system/libmaple/include/libmaple/scb.h
View File

@ -49,37 +49,37 @@ extern "C" {
/** System control block register map type */
typedef struct scb_reg_map {
__io uint32 CPUID; /**< CPU ID Base Register */
__io uint32 ICSR; /**< Interrupt Control State Register */
__io uint32 VTOR; /**< Vector Table Offset Register */
__io uint32 AIRCR; /**< Application Interrupt / Reset Control Register */
__io uint32 SCR; /**< System Control Register */
__io uint32 CCR; /**< Configuration and Control Register */
__io uint8 SHP[12]; /**< System Handler Priority Registers
__IO uint32 CPUID; /**< CPU ID Base Register */
__IO uint32 ICSR; /**< Interrupt Control State Register */
__IO uint32 VTOR; /**< Vector Table Offset Register */
__IO uint32 AIRCR; /**< Application Interrupt / Reset Control Register */
__IO uint32 SCR; /**< System Control Register */
__IO uint32 CCR; /**< Configuration and Control Register */
__IO uint8 SHP[12]; /**< System Handler Priority Registers
(4-7, 8-11, 12-15) */
__io uint32 SHCSR; /**< System Handler Control and State Register */
__io uint32 CFSR; /**< Configurable Fault Status Register */
__io uint32 HFSR; /**< Hard Fault Status Register */
__IO uint32 SHCSR; /**< System Handler Control and State Register */
__IO uint32 CFSR; /**< Configurable Fault Status Register */
__IO uint32 HFSR; /**< Hard Fault Status Register */
/* DFSR is not documented by ST in PM0056 (as of Revision 4), but
* there's a 4 byte hole in the SCB register map docs right where
* it belongs. Since it's specified as "always implemented" in
* the ARM v7-M ARM, I'm assuming its absence is a bug in the ST
* doc, but I haven't proven it. [mbolivar] */
__io uint32 DFSR; /**< Debug Fault Status Register */
__io uint32 MMFAR; /**< Mem Manage Address Register */
__io uint32 BFAR; /**< Bus Fault Address Register */
__IO uint32 DFSR; /**< Debug Fault Status Register */
__IO uint32 MMFAR; /**< Mem Manage Address Register */
__IO uint32 BFAR; /**< Bus Fault Address Register */
#if 0
/* The following registers are implementation-defined according to
* ARM v7-M, and I can't find evidence of their existence in ST's
* docs. I'm removing them. Feel free to yell at me if they do
* exist. [mbolivar]
*/
__io uint32 AFSR; /**< Auxiliary Fault Status Register */
__io uint32 PFR[2]; /**< Processor Feature Register */
__io uint32 DFR; /**< Debug Feature Register */
__io uint32 AFR; /**< Auxiliary Feature Register */
__io uint32 MMFR[4]; /**< Memory Model Feature Register */
__io uint32 ISAR[5]; /**< ISA Feature Register */
__IO uint32 AFSR; /**< Auxiliary Fault Status Register */
__IO uint32 PFR[2]; /**< Processor Feature Register */
__IO uint32 DFR; /**< Debug Feature Register */
__IO uint32 AFR; /**< Auxiliary Feature Register */
__IO uint32 MMFR[4]; /**< Memory Model Feature Register */
__IO uint32 ISAR[5]; /**< ISA Feature Register */
#endif
} scb_reg_map;

28
STM32F1/system/libmaple/include/libmaple/sdio.h
View File

@ -52,23 +52,23 @@ extern "C" {
// SDIO register map type
typedef struct sdio_reg_map {
__io uint32 POWER; // 0x00
__io uint32 CLKCR; // 0x04
__io uint32 ARG; // 0x08
__io uint32 CMD; // 0x0C
__io uint32 RESPCMD; // 0x10 (0x3F)
__IO uint32 POWER; // 0x00
__IO uint32 CLKCR; // 0x04
__IO uint32 ARG; // 0x08
__IO uint32 CMD; // 0x0C
__IO uint32 RESPCMD; // 0x10 (0x3F)
const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response.
__io uint32 DTIMER; // 0x24 - contains the data timeout period, in card bus clock periods.
__io uint32 DLEN; // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
__io uint32 DCTRL; // 0x2C
__io uint32 DCOUNT; // 0x30 (0x01FF FFFF)
__io uint32 STA; // 0x34
__io uint32 ICR; // 0x38
__io uint32 MASK; // 0x3C
__IO uint32 DTIMER; // 0x24 - contains the data timeout period, in card bus clock periods.
__IO uint32 DLEN; // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
__IO uint32 DCTRL; // 0x2C
__IO uint32 DCOUNT; // 0x30 (0x01FF FFFF)
__IO uint32 STA; // 0x34
__IO uint32 ICR; // 0x38
__IO uint32 MASK; // 0x3C
const uint32 RESERVED1[2];
__io uint32 FIFOCNT; // 0x48 (0x01FF FFFF)
__IO uint32 FIFOCNT; // 0x48 (0x01FF FFFF)
const uint32 RESERVED2[13];
__io uint32 FIFO; // 0x80
__IO uint32 FIFO; // 0x80
} sdio_reg_map;
#define sdio_dev sdio_reg_map

18
STM32F1/system/libmaple/include/libmaple/spi.h
View File

@ -54,15 +54,15 @@ extern "C" {
/** SPI register map type. */
typedef struct spi_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SR; /**< Status register */
__io uint32 DR; /**< Data register */
__io uint32 CRCPR; /**< CRC polynomial register */
__io uint32 RXCRCR; /**< RX CRC register */
__io uint32 TXCRCR; /**< TX CRC register */
__io uint32 I2SCFGR; /**< I2S configuration register */
__io uint32 I2SPR; /**< I2S prescaler register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SR; /**< Status register */
__IO uint32 DR; /**< Data register */
__IO uint32 CRCPR; /**< CRC polynomial register */
__IO uint32 RXCRCR; /**< RX CRC register */
__IO uint32 TXCRCR; /**< TX CRC register */
__IO uint32 I2SCFGR; /**< I2S configuration register */
__IO uint32 I2SPR; /**< I2S prescaler register */
} spi_reg_map;
/*

8
STM32F1/system/libmaple/include/libmaple/syscfg.h
View File

@ -48,12 +48,12 @@ extern "C" {
* @brief SYSCFG register map type.
*/
typedef struct syscfg_reg_map {
__io uint32 MEMRMP; /**< Memory remap register */
__io uint32 PMC; /**< Peripheral mode configuration */
__io uint32 EXTICR[4]; /**< External interrupt configuration registers */
__IO uint32 MEMRMP; /**< Memory remap register */
__IO uint32 PMC; /**< Peripheral mode configuration */
__IO uint32 EXTICR[4]; /**< External interrupt configuration registers */
const uint32 RESERVED1;
const uint32 RESERVED2;
__io uint32 CMPCR; /**< Compensation cell control register */
__IO uint32 CMPCR; /**< Compensation cell control register */
} syscfg_reg_map;
/** SYSCFG register map base pointer */

8
STM32F1/system/libmaple/include/libmaple/systick.h
View File

@ -41,10 +41,10 @@ extern "C"{
/** SysTick register map type */
typedef struct systick_reg_map {
__io uint32 CSR; /**< Control and status register */
__io uint32 RVR; /**< Reload value register */
__io uint32 CNT; /**< Current value register ("count") */
__io uint32 CVR; /**< Calibration value register */
__IO uint32 CSR; /**< Control and status register */
__IO uint32 RVR; /**< Reload value register */
__IO uint32 CNT; /**< Current value register ("count") */
__IO uint32 CVR; /**< Calibration value register */
} systick_reg_map;
/** SysTick register map base pointer */

62
STM32F1/system/libmaple/include/libmaple/timer.h
View File

@ -50,26 +50,26 @@ extern "C"{
/** Advanced control timer register map type */
typedef struct timer_adv_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SMCR; /**< Slave mode control register */
__io uint32 DIER; /**< DMA/interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__io uint32 CCMR1; /**< Capture/compare mode register 1 */
__io uint32 CCMR2; /**< Capture/compare mode register 2 */
__io uint32 CCER; /**< Capture/compare enable register */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__io uint32 RCR; /**< Repetition counter register */
__io uint32 CCR1; /**< Capture/compare register 1 */
__io uint32 CCR2; /**< Capture/compare register 2 */
__io uint32 CCR3; /**< Capture/compare register 3 */
__io uint32 CCR4; /**< Capture/compare register 4 */
__io uint32 BDTR; /**< Break and dead-time register */
__io uint32 DCR; /**< DMA control register */
__io uint32 DMAR; /**< DMA address for full transfer */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SMCR; /**< Slave mode control register */
__IO uint32 DIER; /**< DMA/interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
__IO uint32 CCMR1; /**< Capture/compare mode register 1 */
__IO uint32 CCMR2; /**< Capture/compare mode register 2 */
__IO uint32 CCER; /**< Capture/compare enable register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
__IO uint32 RCR; /**< Repetition counter register */
__IO uint32 CCR1; /**< Capture/compare register 1 */
__IO uint32 CCR2; /**< Capture/compare register 2 */
__IO uint32 CCR3; /**< Capture/compare register 3 */
__IO uint32 CCR4; /**< Capture/compare register 4 */
__IO uint32 BDTR; /**< Break and dead-time register */
__IO uint32 DCR; /**< DMA control register */
__IO uint32 DMAR; /**< DMA address for full transfer */
} timer_adv_reg_map;
/* General purpose timer register map type: intentionally omitted.
@ -79,18 +79,18 @@ typedef struct timer_adv_reg_map {
/** Basic timer register map type */
typedef struct timer_bas_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
const uint32 RESERVED1; /**< Reserved */
__io uint32 DIER; /**< DMA/interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__IO uint32 DIER; /**< DMA/interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
const uint32 RESERVED2; /**< Reserved */
const uint32 RESERVED3; /**< Reserved */
const uint32 RESERVED4; /**< Reserved */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
} timer_bas_reg_map;
/*
@ -752,7 +752,7 @@ static inline void timer_set_reload(timer_dev *dev, uint16 arr) {
* @param channel Channel whose compare value to get.
*/
static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) {
__io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
__IO uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
return *ccr;
}
@ -765,7 +765,7 @@ static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) {
static inline void timer_set_compare(timer_dev *dev,
uint8 channel,
uint16 value) {
__io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
__IO uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
*ccr = value;
}
@ -1079,7 +1079,7 @@ static inline void timer_oc_set_mode(timer_dev *dev,
timer_oc_mode mode,
uint8 flags) {
/* channel == 1,2 -> CCMR1; channel == 3,4 -> CCMR2 */
__io uint32 *ccmr = &(dev->regs).gen->CCMR1 + (((channel - 1) >> 1) & 1);
__IO uint32 *ccmr = &(dev->regs).gen->CCMR1 + (((channel - 1) >> 1) & 1);
/* channel == 1,3 -> shift = 0, channel == 2,4 -> shift = 8 */
uint8 shift = 8 * (1 - (channel & 1));

14
STM32F1/system/libmaple/include/libmaple/usart.h
View File

@ -53,13 +53,13 @@ extern "C"{
/** USART register map type */
typedef struct usart_reg_map {
__io uint32 SR; /**< Status register */
__io uint32 DR; /**< Data register */
__io uint32 BRR; /**< Baud rate register */
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 CR3; /**< Control register 3 */
__io uint32 GTPR; /**< Guard time and prescaler register */
__IO uint32 SR; /**< Status register */
__IO uint32 DR; /**< Data register */
__IO uint32 BRR; /**< Baud rate register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 CR3; /**< Control register 3 */
__IO uint32 GTPR; /**< Guard time and prescaler register */
} usart_reg_map;
/*

12
STM32F1/system/libmaple/rcc_private.h
View File

@ -40,16 +40,16 @@ struct rcc_dev_info {
extern const struct rcc_dev_info rcc_dev_table[];
static inline void rcc_do_clk_enable(__io uint32** enable_regs,
static inline void rcc_do_clk_enable(__IO uint32** enable_regs,
rcc_clk_id id) {
__io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
__IO uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
uint8 line_num = rcc_dev_table[id].line_num;
bb_peri_set_bit(enable_reg, line_num, 1);
}
static inline void rcc_do_reset_dev(__io uint32** reset_regs,
static inline void rcc_do_reset_dev(__IO uint32** reset_regs,
rcc_clk_id id) {
__io uint32 *reset_reg = reset_regs[rcc_dev_clk(id)];
__IO uint32 *reset_reg = reset_regs[rcc_dev_clk(id)];
uint8 line_num = rcc_dev_table[id].line_num;
bb_peri_set_bit(reset_reg, line_num, 1);
bb_peri_set_bit(reset_reg, line_num, 0);
@ -64,9 +64,9 @@ static inline void rcc_do_set_prescaler(const uint32 *masks,
RCC_BASE->CFGR = cfgr;
}
static inline void rcc_do_clk_disable(__io uint32** enable_regs,
static inline void rcc_do_clk_disable(__IO uint32** enable_regs,
rcc_clk_id id) {
__io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
__IO uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
uint8 line_num = rcc_dev_table[id].line_num;
bb_peri_set_bit(enable_reg, line_num, 0);
}

26
STM32F1/system/libmaple/stm32f1/include/series/dac.h
View File

@ -40,28 +40,28 @@ extern "C"{
/** STM32F1 DAC register map type. */
typedef struct dac_reg_map {
__io uint32 CR; /**< Control register */
__io uint32 SWTRIGR; /**< Software trigger register */
__io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
__IO uint32 CR; /**< Control register */
__IO uint32 SWTRIGR; /**< Software trigger register */
__IO uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
holding register */
__io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
__IO uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
holding register */
__io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
__IO uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
holding register */
__io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
__IO uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
holding register */
__io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
__IO uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
holding register */
__io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
__IO uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
holding register */
__io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
__IO uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
holding register */
__io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
__IO uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
holding register */
__io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
__IO uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
register */
__io uint32 DOR1; /**< Channel 1 data output register */
__io uint32 DOR2; /**< Channel 2 data output register */
__IO uint32 DOR1; /**< Channel 1 data output register */
__IO uint32 DOR2; /**< Channel 2 data output register */
} dac_reg_map;
#ifdef __cplusplus

74
STM32F1/system/libmaple/stm32f1/include/series/dma.h
View File

@ -57,42 +57,42 @@ extern "C"{
* only supports channels 1--5.
*/
typedef struct dma_reg_map {
__io uint32 ISR; /**< Interrupt status register */
__io uint32 IFCR; /**< Interrupt flag clear register */
__io uint32 CCR1; /**< Channel 1 configuration register */
__io uint32 CNDTR1; /**< Channel 1 number of data register */
__io uint32 CPAR1; /**< Channel 1 peripheral address register */
__io uint32 CMAR1; /**< Channel 1 memory address register */
__IO uint32 ISR; /**< Interrupt status register */
__IO uint32 IFCR; /**< Interrupt flag clear register */
__IO uint32 CCR1; /**< Channel 1 configuration register */
__IO uint32 CNDTR1; /**< Channel 1 number of data register */
__IO uint32 CPAR1; /**< Channel 1 peripheral address register */
__IO uint32 CMAR1; /**< Channel 1 memory address register */
const uint32 RESERVED1; /**< Reserved. */
__io uint32 CCR2; /**< Channel 2 configuration register */
__io uint32 CNDTR2; /**< Channel 2 number of data register */
__io uint32 CPAR2; /**< Channel 2 peripheral address register */
__io uint32 CMAR2; /**< Channel 2 memory address register */
__IO uint32 CCR2; /**< Channel 2 configuration register */
__IO uint32 CNDTR2; /**< Channel 2 number of data register */
__IO uint32 CPAR2; /**< Channel 2 peripheral address register */
__IO uint32 CMAR2; /**< Channel 2 memory address register */
const uint32 RESERVED2; /**< Reserved. */
__io uint32 CCR3; /**< Channel 3 configuration register */
__io uint32 CNDTR3; /**< Channel 3 number of data register */
__io uint32 CPAR3; /**< Channel 3 peripheral address register */
__io uint32 CMAR3; /**< Channel 3 memory address register */
__IO uint32 CCR3; /**< Channel 3 configuration register */
__IO uint32 CNDTR3; /**< Channel 3 number of data register */
__IO uint32 CPAR3; /**< Channel 3 peripheral address register */
__IO uint32 CMAR3; /**< Channel 3 memory address register */
const uint32 RESERVED3; /**< Reserved. */
__io uint32 CCR4; /**< Channel 4 configuration register */
__io uint32 CNDTR4; /**< Channel 4 number of data register */
__io uint32 CPAR4; /**< Channel 4 peripheral address register */
__io uint32 CMAR4; /**< Channel 4 memory address register */
__IO uint32 CCR4; /**< Channel 4 configuration register */
__IO uint32 CNDTR4; /**< Channel 4 number of data register */
__IO uint32 CPAR4; /**< Channel 4 peripheral address register */
__IO uint32 CMAR4; /**< Channel 4 memory address register */
const uint32 RESERVED4; /**< Reserved. */
__io uint32 CCR5; /**< Channel 5 configuration register */
__io uint32 CNDTR5; /**< Channel 5 number of data register */
__io uint32 CPAR5; /**< Channel 5 peripheral address register */
__io uint32 CMAR5; /**< Channel 5 memory address register */
__IO uint32 CCR5; /**< Channel 5 configuration register */
__IO uint32 CNDTR5; /**< Channel 5 number of data register */
__IO uint32 CPAR5; /**< Channel 5 peripheral address register */
__IO uint32 CMAR5; /**< Channel 5 memory address register */
const uint32 RESERVED5; /**< Reserved. */
__io uint32 CCR6; /**< Channel 6 configuration register */
__io uint32 CNDTR6; /**< Channel 6 number of data register */
__io uint32 CPAR6; /**< Channel 6 peripheral address register */
__io uint32 CMAR6; /**< Channel 6 memory address register */
__IO uint32 CCR6; /**< Channel 6 configuration register */
__IO uint32 CNDTR6; /**< Channel 6 number of data register */
__IO uint32 CPAR6; /**< Channel 6 peripheral address register */
__IO uint32 CMAR6; /**< Channel 6 memory address register */
const uint32 RESERVED6; /**< Reserved. */
__io uint32 CCR7; /**< Channel 7 configuration register */
__io uint32 CNDTR7; /**< Channel 7 number of data register */
__io uint32 CPAR7; /**< Channel 7 peripheral address register */
__io uint32 CMAR7; /**< Channel 7 memory address register */
__IO uint32 CCR7; /**< Channel 7 configuration register */
__IO uint32 CNDTR7; /**< Channel 7 number of data register */
__IO uint32 CPAR7; /**< Channel 7 peripheral address register */
__IO uint32 CMAR7; /**< Channel 7 memory address register */
const uint32 RESERVED7; /**< Reserved. */
} dma_reg_map;
@ -107,10 +107,10 @@ typedef struct dma_reg_map {
* @see dma_tube_regs()
*/
typedef struct dma_tube_reg_map {
__io uint32 CCR; /**< Channel configuration register */
__io uint32 CNDTR; /**< Channel number of data register */
__io uint32 CPAR; /**< Channel peripheral address register */
__io uint32 CMAR; /**< Channel memory address register */
__IO uint32 CCR; /**< Channel configuration register */
__IO uint32 CNDTR; /**< Channel number of data register */
__IO uint32 CPAR; /**< Channel peripheral address register */
__IO uint32 CMAR; /**< Channel memory address register */
} dma_tube_reg_map;
/** DMA1 channel 1 register map base pointer */
@ -516,7 +516,7 @@ typedef enum dma_request_src {
#define DMA_CHANNEL_NREGS 5 /* accounts for reserved word */
static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube) {
__io uint32 *ccr1 = &dev->regs->CCR1;
__IO uint32 *ccr1 = &dev->regs->CCR1;
return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (tube - 1));
}
@ -561,9 +561,9 @@ typedef enum dma_mode_flags {
* this information, so this interface is too tied to the F1.) */
void dma_setup_transfer(dma_dev *dev,
dma_channel channel,
__io void *peripheral_address,
__IO void *peripheral_address,
dma_xfer_size peripheral_size,
__io void *memory_address,
__IO void *memory_address,
dma_xfer_size memory_size,
uint32 mode);

16
STM32F1/system/libmaple/stm32f1/include/series/flash.h
View File

@ -48,14 +48,14 @@ extern "C"{
/** @brief STM32F1 Flash register map type */
typedef struct flash_reg_map {
__io uint32 ACR; /**< Access control register */
__io uint32 KEYR; /**< Key register */
__io uint32 OPTKEYR; /**< OPTKEY register */
__io uint32 SR; /**< Status register */
__io uint32 CR; /**< Control register */
__io uint32 AR; /**< Address register */
__io uint32 OBR; /**< Option byte register */
__io uint32 WRPR; /**< Write protection register */
__IO uint32 ACR; /**< Access control register */
__IO uint32 KEYR; /**< Key register */
__IO uint32 OPTKEYR; /**< OPTKEY register */
__IO uint32 SR; /**< Status register */
__IO uint32 CR; /**< Control register */
__IO uint32 AR; /**< Address register */
__IO uint32 OBR; /**< Option byte register */
__IO uint32 WRPR; /**< Write protection register */
} flash_reg_map;
#define FLASH_BASE ((struct flash_reg_map*)0x40022000)

30
STM32F1/system/libmaple/stm32f1/include/series/gpio.h
View File

@ -48,13 +48,13 @@ extern "C"{
/** GPIO register map type */
typedef struct gpio_reg_map {
__io uint32 CRL; /**< Port configuration register low */
__io uint32 CRH; /**< Port configuration register high */
__io uint32 IDR; /**< Port input data register */
__io uint32 ODR; /**< Port output data register */
__io uint32 BSRR; /**< Port bit set/reset register */
__io uint32 BRR; /**< Port bit reset register */
__io uint32 LCKR; /**< Port configuration lock register */
__IO uint32 CRL; /**< Port configuration register low */
__IO uint32 CRH; /**< Port configuration register high */
__IO uint32 IDR; /**< Port input data register */
__IO uint32 ODR; /**< Port output data register */
__IO uint32 BSRR; /**< Port bit set/reset register */
__IO uint32 BRR; /**< Port bit reset register */
__IO uint32 LCKR; /**< Port configuration lock register */
} gpio_reg_map;
struct gpio_dev;
@ -145,13 +145,13 @@ typedef enum gpio_pin_mode {
/** AFIO register map */
typedef struct afio_reg_map {
__io uint32 EVCR; /**< Event control register. */
__io uint32 MAPR; /**< AF remap and debug I/O configuration register. */
__io uint32 EXTICR1; /**< External interrupt configuration register 1. */
__io uint32 EXTICR2; /**< External interrupt configuration register 2. */
__io uint32 EXTICR3; /**< External interrupt configuration register 3. */
__io uint32 EXTICR4; /**< External interrupt configuration register 4. */
__io uint32 MAPR2; /**<
__IO uint32 EVCR; /**< Event control register. */
__IO uint32 MAPR; /**< AF remap and debug I/O configuration register. */
__IO uint32 EXTICR1; /**< External interrupt configuration register 1. */
__IO uint32 EXTICR2; /**< External interrupt configuration register 2. */
__IO uint32 EXTICR3; /**< External interrupt configuration register 3. */
__IO uint32 EXTICR4; /**< External interrupt configuration register 4. */
__IO uint32 MAPR2; /**<
* AF remap and debug I/O configuration register 2. */
} afio_reg_map;
@ -404,7 +404,7 @@ typedef enum afio_debug_cfg {
* @see afio_debug_cfg
*/
static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
__io uint32 *mapr = &AFIO_BASE->MAPR;
__IO uint32 *mapr = &AFIO_BASE->MAPR;
*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
}

20
STM32F1/system/libmaple/stm32f1/include/series/rcc.h
View File

@ -46,16 +46,16 @@ extern "C"{
/** STM32F1 RCC register map type */
typedef struct rcc_reg_map {
__io uint32 CR; /**< Clock control register */
__io uint32 CFGR; /**< Clock configuration register */
__io uint32 CIR; /**< Clock interrupt register */
__io uint32 APB2RSTR; /**< APB2 peripheral reset register */
__io uint32 APB1RSTR; /**< APB1 peripheral reset register */
__io uint32 AHBENR; /**< AHB peripheral clock enable register */
__io uint32 APB2ENR; /**< APB2 peripheral clock enable register */
__io uint32 APB1ENR; /**< APB1 peripheral clock enable register */
__io uint32 BDCR; /**< Backup domain control register */
__io uint32 CSR; /**< Control/status register */
__IO uint32 CR; /**< Clock control register */
__IO uint32 CFGR; /**< Clock configuration register */
__IO uint32 CIR; /**< Clock interrupt register */
__IO uint32 APB2RSTR; /**< APB2 peripheral reset register */
__IO uint32 APB1RSTR; /**< APB1 peripheral reset register */
__IO uint32 AHBENR; /**< AHB peripheral clock enable register */
__IO uint32 APB2ENR; /**< APB2 peripheral clock enable register */
__IO uint32 APB1ENR; /**< APB1 peripheral clock enable register */
__IO uint32 BDCR; /**< Backup domain control register */
__IO uint32 CSR; /**< Control/status register */
} rcc_reg_map;
#define RCC_BASE ((struct rcc_reg_map*)0x40021000)

36
STM32F1/system/libmaple/stm32f1/include/series/timer.h
View File

@ -41,26 +41,26 @@
/** STM32F1 general purpose timer register map type */
typedef struct timer_gen_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SMCR; /**< Slave mode control register */
__io uint32 DIER; /**< DMA/Interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__io uint32 CCMR1; /**< Capture/compare mode register 1 */
__io uint32 CCMR2; /**< Capture/compare mode register 2 */
__io uint32 CCER; /**< Capture/compare enable register */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SMCR; /**< Slave mode control register */
__IO uint32 DIER; /**< DMA/Interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
__IO uint32 CCMR1; /**< Capture/compare mode register 1 */
__IO uint32 CCMR2; /**< Capture/compare mode register 2 */
__IO uint32 CCER; /**< Capture/compare enable register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
const uint32 RESERVED1; /**< Reserved */
__io uint32 CCR1; /**< Capture/compare register 1 */
__io uint32 CCR2; /**< Capture/compare register 2 */
__io uint32 CCR3; /**< Capture/compare register 3 */
__io uint32 CCR4; /**< Capture/compare register 4 */
__IO uint32 CCR1; /**< Capture/compare register 1 */
__IO uint32 CCR2; /**< Capture/compare register 2 */
__IO uint32 CCR3; /**< Capture/compare register 3 */
__IO uint32 CCR4; /**< Capture/compare register 4 */
const uint32 RESERVED2; /**< Reserved */
__io uint32 DCR; /**< DMA control register */
__io uint32 DMAR; /**< DMA address for full transfer */
__IO uint32 DCR; /**< DMA control register */
__IO uint32 DMAR; /**< DMA address for full transfer */
} timer_gen_reg_map;
struct timer_adv_reg_map;

6
STM32F1/system/libmaple/stm32f2/include/series/adc.h
View File

@ -49,9 +49,9 @@ extern const struct adc_dev *ADC3;
/** ADC common register map type */
typedef struct adc_common_reg_map {
__io uint32 CSR; /**< Common status register */
__io uint32 CCR; /**< Common control register */
__io uint32 CDR; /**<
__IO uint32 CSR; /**< Common status register */
__IO uint32 CCR; /**< Common control register */
__IO uint32 CDR; /**<
* @brief Common regular data register
* for dual and triple modes */
} adc_common_reg_map;

28
STM32F1/system/libmaple/stm32f2/include/series/dac.h
View File

@ -44,29 +44,29 @@ extern "C"{
/** STM32F2 DAC register map type. */
typedef struct dac_reg_map {
__io uint32 CR; /**< Control register */
__io uint32 SWTRIGR; /**< Software trigger register */
__io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
__IO uint32 CR; /**< Control register */
__IO uint32 SWTRIGR; /**< Software trigger register */
__IO uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
holding register */
__io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
__IO uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
holding register */
__io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
__IO uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
holding register */
__io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
__IO uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
holding register */
__io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
__IO uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
holding register */
__io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
__IO uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
holding register */
__io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
__IO uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
holding register */
__io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
__IO uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
holding register */
__io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
__IO uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
register */
__io uint32 DOR1; /**< Channel 1 data output register */
__io uint32 DOR2; /**< Channel 2 data output register */
__io uint32 SR; /**< Status register */
__IO uint32 DOR1; /**< Channel 1 data output register */
__IO uint32 DOR2; /**< Channel 2 data output register */
__IO uint32 SR; /**< Status register */
} dac_reg_map;
/*

128
STM32F1/system/libmaple/stm32f2/include/series/dma.h
View File

@ -51,66 +51,66 @@ typedef struct dma_reg_map {
/* Isn't it nice how on F1, it's CCR1, but on F2, it's S1CR? */
/* Global DMA registers */
__io uint32 LISR; /**< Low interrupt status register */
__io uint32 HISR; /**< High interrupt status register */
__io uint32 LIFCR; /**< Low interrupt flag clear register */
__io uint32 HIFCR; /**< High interrupt flag clear register */
__IO uint32 LISR; /**< Low interrupt status register */
__IO uint32 HISR; /**< High interrupt status register */
__IO uint32 LIFCR; /**< Low interrupt flag clear register */
__IO uint32 HIFCR; /**< High interrupt flag clear register */
/* Stream 0 registers */
__io uint32 S0CR; /**< Stream 0 control register */
__io uint32 S0NDTR; /**< Stream 0 number of data register */
__io uint32 S0PAR; /**< Stream 0 peripheral address register */
__io uint32 S0M0AR; /**< Stream 0 memory 0 address register */
__io uint32 S0M1AR; /**< Stream 0 memory 1 address register */
__io uint32 S0FCR; /**< Stream 0 FIFO control register */
__IO uint32 S0CR; /**< Stream 0 control register */
__IO uint32 S0NDTR; /**< Stream 0 number of data register */
__IO uint32 S0PAR; /**< Stream 0 peripheral address register */
__IO uint32 S0M0AR; /**< Stream 0 memory 0 address register */
__IO uint32 S0M1AR; /**< Stream 0 memory 1 address register */
__IO uint32 S0FCR; /**< Stream 0 FIFO control register */
/* Stream 1 registers */
__io uint32 S1CR; /**< Stream 1 control register */
__io uint32 S1NDTR; /**< Stream 1 number of data register */
__io uint32 S1PAR; /**< Stream 1 peripheral address register */
__io uint32 S1M0AR; /**< Stream 1 memory 0 address register */
__io uint32 S1M1AR; /**< Stream 1 memory 1 address register */
__io uint32 S1FCR; /**< Stream 1 FIFO control register */
__IO uint32 S1CR; /**< Stream 1 control register */
__IO uint32 S1NDTR; /**< Stream 1 number of data register */
__IO uint32 S1PAR; /**< Stream 1 peripheral address register */
__IO uint32 S1M0AR; /**< Stream 1 memory 0 address register */
__IO uint32 S1M1AR; /**< Stream 1 memory 1 address register */
__IO uint32 S1FCR; /**< Stream 1 FIFO control register */
/* Stream 2 registers */
__io uint32 S2CR; /**< Stream 2 control register */
__io uint32 S2NDTR; /**< Stream 2 number of data register */
__io uint32 S2PAR; /**< Stream 2 peripheral address register */
__io uint32 S2M0AR; /**< Stream 2 memory 0 address register */
__io uint32 S2M1AR; /**< Stream 2 memory 1 address register */
__io uint32 S2FCR; /**< Stream 2 FIFO control register */
__IO uint32 S2CR; /**< Stream 2 control register */
__IO uint32 S2NDTR; /**< Stream 2 number of data register */
__IO uint32 S2PAR; /**< Stream 2 peripheral address register */
__IO uint32 S2M0AR; /**< Stream 2 memory 0 address register */
__IO uint32 S2M1AR; /**< Stream 2 memory 1 address register */
__IO uint32 S2FCR; /**< Stream 2 FIFO control register */
/* Stream 3 registers */
__io uint32 S3CR; /**< Stream 3 control register */
__io uint32 S3NDTR; /**< Stream 3 number of data register */
__io uint32 S3PAR; /**< Stream 3 peripheral address register */
__io uint32 S3M0AR; /**< Stream 3 memory 0 address register */
__io uint32 S3M1AR; /**< Stream 3 memory 1 address register */
__io uint32 S3FCR; /**< Stream 3 FIFO control register */
__IO uint32 S3CR; /**< Stream 3 control register */
__IO uint32 S3NDTR; /**< Stream 3 number of data register */
__IO uint32 S3PAR; /**< Stream 3 peripheral address register */
__IO uint32 S3M0AR; /**< Stream 3 memory 0 address register */
__IO uint32 S3M1AR; /**< Stream 3 memory 1 address register */
__IO uint32 S3FCR; /**< Stream 3 FIFO control register */
/* Stream 4 registers */
__io uint32 S4CR; /**< Stream 4 control register */
__io uint32 S4NDTR; /**< Stream 4 number of data register */
__io uint32 S4PAR; /**< Stream 4 peripheral address register */
__io uint32 S4M0AR; /**< Stream 4 memory 0 address register */
__io uint32 S4M1AR; /**< Stream 4 memory 1 address register */
__io uint32 S4FCR; /**< Stream 4 FIFO control register */
__IO uint32 S4CR; /**< Stream 4 control register */
__IO uint32 S4NDTR; /**< Stream 4 number of data register */
__IO uint32 S4PAR; /**< Stream 4 peripheral address register */
__IO uint32 S4M0AR; /**< Stream 4 memory 0 address register */
__IO uint32 S4M1AR; /**< Stream 4 memory 1 address register */
__IO uint32 S4FCR; /**< Stream 4 FIFO control register */
/* Stream 5 registers */
__io uint32 S5CR; /**< Stream 5 control register */
__io uint32 S5NDTR; /**< Stream 5 number of data register */
__io uint32 S5PAR; /**< Stream 5 peripheral address register */
__io uint32 S5M0AR; /**< Stream 5 memory 0 address register */
__io uint32 S5M1AR; /**< Stream 5 memory 1 address register */
__io uint32 S5FCR; /**< Stream 5 FIFO control register */
__IO uint32 S5CR; /**< Stream 5 control register */
__IO uint32 S5NDTR; /**< Stream 5 number of data register */
__IO uint32 S5PAR; /**< Stream 5 peripheral address register */
__IO uint32 S5M0AR; /**< Stream 5 memory 0 address register */
__IO uint32 S5M1AR; /**< Stream 5 memory 1 address register */
__IO uint32 S5FCR; /**< Stream 5 FIFO control register */
/* Stream 6 registers */
__io uint32 S6CR; /**< Stream 6 control register */
__io uint32 S6NDTR; /**< Stream 6 number of data register */
__io uint32 S6PAR; /**< Stream 6 peripheral address register */
__io uint32 S6M0AR; /**< Stream 6 memory 0 address register */
__io uint32 S6M1AR; /**< Stream 6 memory 1 address register */
__io uint32 S6FCR; /**< Stream 6 FIFO control register */
__IO uint32 S6CR; /**< Stream 6 control register */
__IO uint32 S6NDTR; /**< Stream 6 number of data register */
__IO uint32 S6PAR; /**< Stream 6 peripheral address register */
__IO uint32 S6M0AR; /**< Stream 6 memory 0 address register */
__IO uint32 S6M1AR; /**< Stream 6 memory 1 address register */
__IO uint32 S6FCR; /**< Stream 6 FIFO control register */
/* Stream 7 registers */
__io uint32 S7CR; /**< Stream 7 control register */
__io uint32 S7NDTR; /**< Stream 7 number of data register */
__io uint32 S7PAR; /**< Stream 7 peripheral address register */
__io uint32 S7M0AR; /**< Stream 7 memory 0 address register */
__io uint32 S7M1AR; /**< Stream 7 memory 1 address register */
__io uint32 S7FCR; /**< Stream 7 FIFO control register */
__IO uint32 S7CR; /**< Stream 7 control register */
__IO uint32 S7NDTR; /**< Stream 7 number of data register */
__IO uint32 S7PAR; /**< Stream 7 peripheral address register */
__IO uint32 S7M0AR; /**< Stream 7 memory 0 address register */
__IO uint32 S7M1AR; /**< Stream 7 memory 1 address register */
__IO uint32 S7FCR; /**< Stream 7 FIFO control register */
} dma_reg_map;
/** DMA controller 1 register map base pointer */
@ -124,12 +124,12 @@ typedef struct dma_reg_map {
* @see dma_tube_regs()
*/
typedef struct dma_tube_reg_map {
__io uint32 SCR; /**< Stream configuration register */
__io uint32 SNDTR; /**< Stream number of data register */
__io uint32 SPAR; /**< Stream peripheral address register */
__io uint32 SM0AR; /**< Stream memory 0 address register */
__io uint32 SM1AR; /**< Stream memory 1 address register */
__io uint32 SFCR; /**< Stream FIFO control register */
__IO uint32 SCR; /**< Stream configuration register */
__IO uint32 SNDTR; /**< Stream number of data register */
__IO uint32 SPAR; /**< Stream peripheral address register */
__IO uint32 SM0AR; /**< Stream memory 0 address register */
__IO uint32 SM1AR; /**< Stream memory 1 address register */
__IO uint32 SFCR; /**< Stream FIFO control register */
} dma_tube_reg_map;
/** DMA1 stream 0 register map base pointer */
@ -697,7 +697,7 @@ static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) {
/* F2-only; available because of double-buffering. */
void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n,
__io void *address);
__IO void *address);
/**
* @brief Set memory 0 address.
@ -708,7 +708,7 @@ void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n,
* @param addr Address to use as memory 0
*/
static inline __always_inline void
dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __IO void *addr) {
dma_set_mem_n_addr(dev, tube, 0, addr);
}
@ -721,13 +721,13 @@ dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
* @param addr Address to use as memory 1
*/
static inline __always_inline void
dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __IO void *addr) {
dma_set_mem_n_addr(dev, tube, 1, addr);
}
/* Assume the user means SM0AR in a non-double-buffered configuration. */
static inline __always_inline void
dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
dma_set_mem_addr(dma_dev *dev, dma_tube tube, __IO void *addr) {
dma_set_mem0_addr(dev, tube, addr);
}
@ -791,13 +791,13 @@ static inline __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) {
static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) {
dma_reg_map *regs = dev->regs;
__io uint32 *isr = tube > DMA_S3 ? &regs->HISR : &regs->LISR;
__IO uint32 *isr = tube > DMA_S3 ? &regs->HISR : &regs->LISR;
return (*isr >> _dma_sr_fcr_shift(tube)) & 0x3D;
}
static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) {
dma_reg_map *regs = dev->regs;
__io uint32 *ifcr = tube > DMA_S3 ? &regs->HIFCR : &regs->LIFCR;
__IO uint32 *ifcr = tube > DMA_S3 ? &regs->HIFCR : &regs->LIFCR;
*ifcr = (0x3D << _dma_sr_fcr_shift(tube));
}

12
STM32F1/system/libmaple/stm32f2/include/series/flash.h
View File

@ -48,12 +48,12 @@ extern "C"{
/** @brief STM32F2 Flash register map type */
typedef struct flash_reg_map {
__io uint32 ACR; /**< Access control register */
__io uint32 KEYR; /**< Key register */
__io uint32 OPTKEYR; /**< Option key register */
__io uint32 SR; /**< Status register */
__io uint32 CR; /**< Control register */
__io uint32 OPTCR; /**< Option control register */
__IO uint32 ACR; /**< Access control register */
__IO uint32 KEYR; /**< Key register */
__IO uint32 OPTKEYR; /**< Option key register */
__IO uint32 SR; /**< Status register */
__IO uint32 CR; /**< Control register */
__IO uint32 OPTCR; /**< Option control register */
} flash_reg_map;
#define FLASH_BASE ((struct flash_reg_map*)0x40023C00)

20
STM32F1/system/libmaple/stm32f2/include/series/gpio.h
View File

@ -44,16 +44,16 @@ extern "C"{
/** GPIO register map type */
typedef struct gpio_reg_map {
__io uint32 MODER; /**< Mode register */
__io uint32 OTYPER; /**< Output type register */
__io uint32 OSPEEDR; /**< Output speed register */
__io uint32 PUPDR; /**< Pull-up/pull-down register */
__io uint32 IDR; /**< Input data register */
__io uint32 ODR; /**< Output data register */
__io uint32 BSRR; /**< Bit set/reset register */
__io uint32 LCKR; /**< Configuration lock register */
__io uint32 AFRL; /**< Alternate function low register */
__io uint32 AFRH; /**< Alternate function high register */
__IO uint32 MODER; /**< Mode register */
__IO uint32 OTYPER; /**< Output type register */
__IO uint32 OSPEEDR; /**< Output speed register */
__IO uint32 PUPDR; /**< Pull-up/pull-down register */
__IO uint32 IDR; /**< Input data register */
__IO uint32 ODR; /**< Output data register */
__IO uint32 BSRR; /**< Bit set/reset register */
__IO uint32 LCKR; /**< Configuration lock register */
__IO uint32 AFRL; /**< Alternate function low register */
__IO uint32 AFRH; /**< Alternate function high register */
} gpio_reg_map;
/** GPIO port A register map base pointer */

46
STM32F1/system/libmaple/stm32f2/include/series/rcc.h
View File

@ -44,46 +44,46 @@ extern "C"{
/** STM32F2 RCC register map type */
typedef struct rcc_reg_map {
__io uint32 CR; /**< Clock control register */
__io uint32 PLLCFGR; /**< PLL configuration register */
__io uint32 CFGR; /**< Clock configuration register */
__io uint32 CIR; /**< Clock interrupt register */
__io uint32 AHB1RSTR; /**< AHB1 peripheral reset register */
__io uint32 AHB2RSTR; /**< AHB2 peripheral reset register */
__io uint32 AHB3RSTR; /**< AHB3 peripheral reset register */
__IO uint32 CR; /**< Clock control register */
__IO uint32 PLLCFGR; /**< PLL configuration register */
__IO uint32 CFGR; /**< Clock configuration register */
__IO uint32 CIR; /**< Clock interrupt register */
__IO uint32 AHB1RSTR; /**< AHB1 peripheral reset register */
__IO uint32 AHB2RSTR; /**< AHB2 peripheral reset register */
__IO uint32 AHB3RSTR; /**< AHB3 peripheral reset register */
const uint32 RESERVED1; /**< Reserved */
__io uint32 APB1RSTR; /**< APB1 peripheral reset register */
__io uint32 APB2RSTR; /**< APB2 peripheral reset register */
__IO uint32 APB1RSTR; /**< APB1 peripheral reset register */
__IO uint32 APB2RSTR; /**< APB2 peripheral reset register */
const uint32 RESERVED2; /**< Reserved */
const uint32 RESERVED3; /**< Reserved */
__io uint32 AHB1ENR; /**< AHB1 peripheral clock enable register */
__io uint32 AHB2ENR; /**< AHB2 peripheral clock enable register */
__io uint32 AHB3ENR; /**< AHB3 peripheral clock enable register */
__IO uint32 AHB1ENR; /**< AHB1 peripheral clock enable register */
__IO uint32 AHB2ENR; /**< AHB2 peripheral clock enable register */
__IO uint32 AHB3ENR; /**< AHB3 peripheral clock enable register */
const uint32 RESERVED4; /**< Reserved */
__io uint32 APB1ENR; /**< APB1 peripheral clock enable register */
__io uint32 APB2ENR; /**< APB2 peripheral clock enable register */
__IO uint32 APB1ENR; /**< APB1 peripheral clock enable register */
__IO uint32 APB2ENR; /**< APB2 peripheral clock enable register */
const uint32 RESERVED5; /**< Reserved */
const uint32 RESERVED6; /**< Reserved */
__io uint32 AHB1LPENR; /**< AHB1 peripheral clock enable in
__IO uint32 AHB1LPENR; /**< AHB1 peripheral clock enable in
low power mode register */
__io uint32 AHB2LPENR; /**< AHB2 peripheral clock enable in
__IO uint32 AHB2LPENR; /**< AHB2 peripheral clock enable in
low power mode register */
__io uint32 AHB3LPENR; /**< AHB3 peripheral clock enable in
__IO uint32 AHB3LPENR; /**< AHB3 peripheral clock enable in
low power mode register */
const uint32 RESERVED7; /**< Reserved */
__io uint32 APB1LPENR; /**< APB1 peripheral clock enable in
__IO uint32 APB1LPENR; /**< APB1 peripheral clock enable in
low power mode register */
__io uint32 APB2LPENR; /**< APB2 peripheral clock enable in
__IO uint32 APB2LPENR; /**< APB2 peripheral clock enable in
low power mode register */
const uint32 RESERVED8; /**< Reserved */
const uint32 RESERVED9; /**< Reserved */
__io uint32 BDCR; /**< Backup domain control register */
__io uint32 CSR; /**< Clock control and status register */
__IO uint32 BDCR; /**< Backup domain control register */
__IO uint32 CSR; /**< Clock control and status register */
const uint32 RESERVED10; /**< Reserved */
const uint32 RESERVED11; /**< Reserved */
__io uint32 SSCGR; /**< Spread spectrum clock generation
__IO uint32 SSCGR; /**< Spread spectrum clock generation
register */
__io uint32 PLLI2SCFGR; /**< PLLI2S configuration register */
__IO uint32 PLLI2SCFGR; /**< PLLI2S configuration register */
} rcc_reg_map;
#define RCC_BASE ((struct rcc_reg_map*)0x40023800)

38
STM32F1/system/libmaple/stm32f2/include/series/timer.h
View File

@ -47,27 +47,27 @@
* registers. Consult your chip's reference manual for the details.
*/
typedef struct timer_gen_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SMCR; /**< Slave mode control register */
__io uint32 DIER; /**< DMA/Interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__io uint32 CCMR1; /**< Capture/compare mode register 1 */
__io uint32 CCMR2; /**< Capture/compare mode register 2 */
__io uint32 CCER; /**< Capture/compare enable register */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SMCR; /**< Slave mode control register */
__IO uint32 DIER; /**< DMA/Interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
__IO uint32 CCMR1; /**< Capture/compare mode register 1 */
__IO uint32 CCMR2; /**< Capture/compare mode register 2 */
__IO uint32 CCER; /**< Capture/compare enable register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
const uint32 RESERVED1; /**< Reserved */
__io uint32 CCR1; /**< Capture/compare register 1 */
__io uint32 CCR2; /**< Capture/compare register 2 */
__io uint32 CCR3; /**< Capture/compare register 3 */
__io uint32 CCR4; /**< Capture/compare register 4 */
__IO uint32 CCR1; /**< Capture/compare register 1 */
__IO uint32 CCR2; /**< Capture/compare register 2 */
__IO uint32 CCR3; /**< Capture/compare register 3 */
__IO uint32 CCR4; /**< Capture/compare register 4 */
const uint32 RESERVED2; /**< Reserved */
__io uint32 DCR; /**< DMA control register */
__io uint32 DMAR; /**< DMA address for full transfer */
__io uint32 OR; /**< Option register. */
__IO uint32 DCR; /**< DMA control register */
__IO uint32 DMAR; /**< DMA address for full transfer */
__IO uint32 OR; /**< Option register. */
} timer_gen_reg_map;
struct timer_adv_reg_map;

54
STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
View File

@ -42,13 +42,13 @@
/** USB register map type */
typedef struct usb_reg_map {
__io uint32 EP[USB_NR_EP_REGS]; /**< Endpoint registers */
__IO uint32 EP[USB_NR_EP_REGS]; /**< Endpoint registers */
const uint32 RESERVED[8]; /**< Reserved */
__io uint32 CNTR; /**< Control register */
__io uint32 ISTR; /**< Interrupt status register */
__io uint32 FNR; /**< Frame number register */
__io uint32 DADDR; /**< Device address */
__io uint32 BTABLE; /**< @brief Buffer table address
__IO uint32 CNTR; /**< Control register */
__IO uint32 ISTR; /**< Interrupt status register */
__IO uint32 FNR; /**< Frame number register */
__IO uint32 DADDR; /**< Device address */
__IO uint32 BTABLE; /**< @brief Buffer table address
*
* Address offset within the USB
* packet memory area which points
@ -340,7 +340,7 @@ static inline void usb_clear_status_out(uint8 ep) {
*
* The USB PMA is SRAM shared between USB and CAN. The USB peripheral
* accesses this memory directly via the packet buffer interface. */
#define USB_PMA_BASE ((__io void*)0x40006000)
#define USB_PMA_BASE ((__IO void*)0x40006000)
/*
* PMA conveniences
@ -367,42 +367,42 @@ union usb_btable_ent;
/* Bidirectional endpoint BTABLE entry */
typedef struct usb_btable_bidi {
__io uint16 addr_tx; const uint16 PAD1;
__io uint16 count_tx; const uint16 PAD2;
__io uint16 addr_rx; const uint16 PAD3;
__io uint16 count_rx; const uint16 PAD4;
__IO uint16 addr_tx; const uint16 PAD1;
__IO uint16 count_tx; const uint16 PAD2;
__IO uint16 addr_rx; const uint16 PAD3;
__IO uint16 count_rx; const uint16 PAD4;
} usb_btable_bidi;
/* Unidirectional receive-only endpoint BTABLE entry */
typedef struct usb_btable_uni_rx {
__io uint16 empty1; const uint16 PAD1;
__io uint16 empty2; const uint16 PAD2;
__io uint16 addr_rx; const uint16 PAD3;
__io uint16 count_rx; const uint16 PAD4;
__IO uint16 empty1; const uint16 PAD1;
__IO uint16 empty2; const uint16 PAD2;
__IO uint16 addr_rx; const uint16 PAD3;
__IO uint16 count_rx; const uint16 PAD4;
} usb_btable_uni_rx;
/* Unidirectional transmit-only endpoint BTABLE entry */
typedef struct usb_btable_uni_tx {
__io uint16 addr_tx; const uint16 PAD1;
__io uint16 count_tx; const uint16 PAD2;
__io uint16 empty1; const uint16 PAD3;
__io uint16 empty2; const uint16 PAD4;
__IO uint16 addr_tx; const uint16 PAD1;
__IO uint16 count_tx; const uint16 PAD2;
__IO uint16 empty1; const uint16 PAD3;
__IO uint16 empty2; const uint16 PAD4;
} usb_btable_uni_tx;
/* Double-buffered transmission endpoint BTABLE entry */
typedef struct usb_btable_dbl_tx {
__io uint16 addr_tx0; const uint16 PAD1;
__io uint16 count_tx0; const uint16 PAD2;
__io uint16 addr_tx1; const uint16 PAD3;
__io uint16 count_tx1; const uint16 PAD4;
__IO uint16 addr_tx0; const uint16 PAD1;
__IO uint16 count_tx0; const uint16 PAD2;
__IO uint16 addr_tx1; const uint16 PAD3;
__IO uint16 count_tx1; const uint16 PAD4;
} usb_btable_dbl_tx;
/* Double-buffered reception endpoint BTABLE entry */
typedef struct usb_btable_dbl_rx {
__io uint16 addr_rx0; const uint16 PAD1;
__io uint16 count_rx0; const uint16 PAD2;
__io uint16 addr_rx1; const uint16 PAD3;
__io uint16 count_rx1; const uint16 PAD4;
__IO uint16 addr_rx0; const uint16 PAD1;
__IO uint16 count_rx0; const uint16 PAD2;
__IO uint16 addr_rx1; const uint16 PAD3;
__IO uint16 count_rx1; const uint16 PAD4;
} usb_btable_dbl_rx;
/* TODO isochronous endpoint entries */

4
STM32F3/cores/maple/libmaple/bkp.c
View File

@ -50,7 +50,7 @@ void bkp_disable_writes(void) {
}
uint16 bkp_read(uint8 reg) {
__io uint32* dr = bkp_data_register(reg);
__IO uint32* dr = bkp_data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return 0;
@ -59,7 +59,7 @@ uint16 bkp_read(uint8 reg) {
}
void bkp_write(uint8 reg, uint16 val) {
__io uint32* dr = bkp_data_register(reg);
__IO uint32* dr = bkp_data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return;

2
STM32F3/cores/maple/libmaple/dma.c
View File

@ -52,7 +52,7 @@ void dma_init(dma_dev *dev) {
* Private API
*/
enum dma_atype _dma_addr_type(__io void *addr) {
enum dma_atype _dma_addr_type(__IO void *addr) {
switch (stm32_block_purpose((void*)addr)) {
/* Notice we're treating the code block as memory here. That's
* correct for addresses in Flash and in [0x0, 0x7FFFFFF]

2
STM32F3/cores/maple/libmaple/dma_private.h
View File

@ -56,6 +56,6 @@ enum dma_atype {
DMA_ATYPE_OTHER,
};
enum dma_atype _dma_addr_type(__io void *addr);
enum dma_atype _dma_addr_type(__IO void *addr);
#endif

2
STM32F3/cores/maple/libmaple/exti.c
View File

@ -200,7 +200,7 @@ void exti_detach_interrupt(exti_num num) {
* Private routines
*/
void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port) {
void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port) {
uint32 shift = 4 * (num % 4);
uint32 cr = *exti_cr;
cr &= ~(0xF << shift);

2
STM32F3/cores/maple/libmaple/exti_private.h
View File

@ -29,6 +29,6 @@
#include <libmaple/exti.h>
void exti_do_select(__io uint32 *exti_cr, exti_num num, exti_cfg port);
void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port);
#endif

2
STM32F3/cores/maple/libmaple/include/libmaple/bkp.h
View File

@ -52,7 +52,7 @@ extern const struct bkp_dev *BKP;
/*
* this function needs to be implemented for each series separately
*/
extern inline __io uint32* bkp_data_register(uint8 reg);
extern inline __IO uint32* bkp_data_register(uint8 reg);
/**
* @brief Initialize backup interface.

8
STM32F3/cores/maple/libmaple/include/libmaple/dma.h
View File

@ -136,12 +136,12 @@ void dma_init(dma_dev *dev);
*/
typedef struct dma_tube_config {
/** Source of data */
__io void *tube_src;
__IO void *tube_src;
/** Source transfer size */
dma_xfer_size tube_src_size;
/** Destination of data */
__io void *tube_dst;
__IO void *tube_dst;
/** Destination transfer size */
dma_xfer_size tube_dst_size;
@ -280,7 +280,7 @@ extern void dma_set_num_transfers(dma_dev *dev, dma_tube tube,
* @param tube Tube whose base memory address to set.
* @param address Memory base address to use.
*/
extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *address);
extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __IO void *address);
/**
* @brief Set the base peripheral address where data will be read from
@ -296,7 +296,7 @@ extern void dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *address);
* @param tube Tube whose peripheral data register base address to set.
* @param address Peripheral memory base address to use.
*/
extern void dma_set_per_addr(dma_dev *dev, dma_tube tube, __io void *address);
extern void dma_set_per_addr(dma_dev *dev, dma_tube tube, __IO void *address);
/* Interrupt handling */

12
STM32F3/cores/maple/libmaple/include/libmaple/exti.h
View File

@ -47,12 +47,12 @@ extern "C"{
/** EXTI register map type */
typedef struct exti_reg_map {
__io uint32 IMR; /**< Interrupt mask register */
__io uint32 EMR; /**< Event mask register */
__io uint32 RTSR; /**< Rising trigger selection register */
__io uint32 FTSR; /**< Falling trigger selection register */
__io uint32 SWIER; /**< Software interrupt event register */
__io uint32 PR; /**< Pending register */
__IO uint32 IMR; /**< Interrupt mask register */
__IO uint32 EMR; /**< Event mask register */
__IO uint32 RTSR; /**< Rising trigger selection register */
__IO uint32 FTSR; /**< Falling trigger selection register */
__IO uint32 SWIER; /**< Software interrupt event register */
__IO uint32 PR; /**< Pending register */
} exti_reg_map;
/*

60
STM32F3/cores/maple/libmaple/include/libmaple/fsmc.h
View File

@ -53,42 +53,42 @@ extern "C"{
/** FSMC register map type */
typedef struct fsmc_reg_map {
__io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
__io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
__io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
__io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
__io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
__io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
__io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
__io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
__IO uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
__IO uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
__IO uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
__IO uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
__IO uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
__IO uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
__IO uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
__IO uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
const uint8 RESERVED1[64]; /**< Reserved */
__io uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
__io uint32 SR2; /**< FIFO status and interrupt register 2 */
__io uint32 PMEM2; /**< Common memory space timing register 2 */
__io uint32 PATT2; /**< Attribute memory space timing register 2 */
__IO uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
__IO uint32 SR2; /**< FIFO status and interrupt register 2 */
__IO uint32 PMEM2; /**< Common memory space timing register 2 */
__IO uint32 PATT2; /**< Attribute memory space timing register 2 */
const uint8 RESERVED2[4]; /**< Reserved */
__io uint32 ECCR2; /**< ECC result register 2 */
__IO uint32 ECCR2; /**< ECC result register 2 */
const uint8 RESERVED3[2];
__io uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
__io uint32 SR3; /**< FIFO status and interrupt register 3 */
__io uint32 PMEM3; /**< Common memory space timing register 3 */
__io uint32 PATT3; /**< Attribute memory space timing register 3 */
__IO uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
__IO uint32 SR3; /**< FIFO status and interrupt register 3 */
__IO uint32 PMEM3; /**< Common memory space timing register 3 */
__IO uint32 PATT3; /**< Attribute memory space timing register 3 */
const uint32 RESERVED4; /**< Reserved */
__io uint32 ECCR3; /**< ECC result register 3 */
__IO uint32 ECCR3; /**< ECC result register 3 */
const uint8 RESERVED5[8]; /**< Reserved */
__io uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
__io uint32 SR4; /**< FIFO status and interrupt register 4 */
__io uint32 PMEM4; /**< Common memory space timing register 4 */
__io uint32 PATT4; /**< Attribute memory space timing register 4 */
__io uint32 PIO4; /**< I/O space timing register 4 */
__IO uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
__IO uint32 SR4; /**< FIFO status and interrupt register 4 */
__IO uint32 PMEM4; /**< Common memory space timing register 4 */
__IO uint32 PATT4; /**< Attribute memory space timing register 4 */
__IO uint32 PIO4; /**< I/O space timing register 4 */
const uint8 RESERVED6[80]; /**< Reserved */
__io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
__IO uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
const uint32 RESERVED7; /**< Reserved */
__io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
__IO uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
const uint32 RESERVED8; /**< Reserved */
__io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
__IO uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
const uint32 RESERVED9; /**< Reserved */
__io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
__IO uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
} __attribute__((packed)) fsmc_reg_map;
#define __FSMCB 0xA0000000
@ -98,10 +98,10 @@ typedef struct fsmc_reg_map {
/** FSMC NOR/PSRAM register map type */
typedef struct fsmc_nor_psram_reg_map {
__io uint32 BCR; /**< Chip-select control register */
__io uint32 BTR; /**< Chip-select timing register */
__IO uint32 BCR; /**< Chip-select control register */
__IO uint32 BTR; /**< Chip-select timing register */
const uint8 RESERVED[252]; /**< Reserved */
__io uint32 BWTR; /**< Write timing register */
__IO uint32 BWTR; /**< Write timing register */
} fsmc_nor_psram_reg_map;
/** FSMC NOR/PSRAM base pointer 1 */

8
STM32F3/cores/maple/libmaple/include/libmaple/iwdg.h
View File

@ -53,10 +53,10 @@ extern "C"{
/** Independent watchdog register map type. */
typedef struct iwdg_reg_map {
__io uint32 KR; /**< Key register. */
__io uint32 PR; /**< Prescaler register. */
__io uint32 RLR; /**< Reload register. */
__io uint32 SR; /**< Status register */
__IO uint32 KR; /**< Key register. */
__IO uint32 PR; /**< Prescaler register. */
__IO uint32 RLR; /**< Reload register. */
__IO uint32 SR; /**< Status register */
} iwdg_reg_map;
/** Independent watchdog base pointer */

2
STM32F3/cores/maple/libmaple/include/libmaple/libmaple_types.h
View File

@ -50,7 +50,7 @@ typedef long long int64;
typedef void (*voidFuncPtr)(void);
typedef void (*voidArgumentFuncPtr)(void *);
#define __io volatile
#define __IO volatile
#define __attr_flash __attribute__((section (".USER_FLASH")))
#define __packed __attribute__((__packed__))
#define __deprecated __attribute__((__deprecated__))

14
STM32F3/cores/maple/libmaple/include/libmaple/nvic.h
View File

@ -55,31 +55,31 @@ extern "C"{
/** NVIC register map type. */
typedef struct nvic_reg_map {
__io uint32 ISER[8]; /**< Interrupt Set Enable Registers */
__IO uint32 ISER[8]; /**< Interrupt Set Enable Registers */
/** Reserved */
uint32 RESERVED0[24];
__io uint32 ICER[8]; /**< Interrupt Clear Enable Registers */
__IO uint32 ICER[8]; /**< Interrupt Clear Enable Registers */
/** Reserved */
uint32 RESERVED1[24];
__io uint32 ISPR[8]; /**< Interrupt Set Pending Registers */
__IO uint32 ISPR[8]; /**< Interrupt Set Pending Registers */
/** Reserved */
uint32 RESERVED2[24];
__io uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */
__IO uint32 ICPR[8]; /**< Interrupt Clear Pending Registers */
/** Reserved */
uint32 RESERVED3[24];
__io uint32 IABR[8]; /**< Interrupt Active bit Registers */
__IO uint32 IABR[8]; /**< Interrupt Active bit Registers */
/** Reserved */
uint32 RESERVED4[56];
__io uint8 IP[240]; /**< Interrupt Priority Registers */
__IO uint8 IP[240]; /**< Interrupt Priority Registers */
/** Reserved */
uint32 RESERVED5[644];
__io uint32 STIR; /**< Software Trigger Interrupt Registers */
__IO uint32 STIR; /**< Software Trigger Interrupt Registers */
} nvic_reg_map;
/** NVIC register map base pointer. */

4
STM32F3/cores/maple/libmaple/include/libmaple/pwr.h
View File

@ -41,8 +41,8 @@ extern "C" {
/** Power interface register map. */
typedef struct pwr_reg_map {
__io uint32 CR; /**< Control register */
__io uint32 CSR; /**< Control and status register */
__IO uint32 CR; /**< Control register */
__IO uint32 CSR; /**< Control and status register */
} pwr_reg_map;
/** Power peripheral register map base pointer. */

2
STM32F3/cores/maple/libmaple/include/libmaple/ring_buffer.h
View File

@ -81,7 +81,7 @@ static inline void rb_init(ring_buffer *rb, uint16 size, uint8 *buf) {
* @param rb Buffer whose elements to count.
*/
static inline uint16 rb_full_count(ring_buffer *rb) {
__io ring_buffer *arb = rb;
__IO ring_buffer *arb = rb;
int32 size = arb->tail - arb->head;
if (arb->tail < arb->head) {
size += arb->size + 1;

38
STM32F3/cores/maple/libmaple/include/libmaple/scb.h
View File

@ -49,37 +49,37 @@ extern "C" {
/** System control block register map type */
typedef struct scb_reg_map {
__io uint32 CPUID; /**< CPU ID Base Register */
__io uint32 ICSR; /**< Interrupt Control State Register */
__io uint32 VTOR; /**< Vector Table Offset Register */
__io uint32 AIRCR; /**< Application Interrupt / Reset Control Register */
__io uint32 SCR; /**< System Control Register */
__io uint32 CCR; /**< Configuration and Control Register */
__io uint8 SHP[12]; /**< System Handler Priority Registers
__IO uint32 CPUID; /**< CPU ID Base Register */
__IO uint32 ICSR; /**< Interrupt Control State Register */
__IO uint32 VTOR; /**< Vector Table Offset Register */
__IO uint32 AIRCR; /**< Application Interrupt / Reset Control Register */
__IO uint32 SCR; /**< System Control Register */
__IO uint32 CCR; /**< Configuration and Control Register */
__IO uint8 SHP[12]; /**< System Handler Priority Registers
(4-7, 8-11, 12-15) */
__io uint32 SHCSR; /**< System Handler Control and State Register */
__io uint32 CFSR; /**< Configurable Fault Status Register */
__io uint32 HFSR; /**< Hard Fault Status Register */
__IO uint32 SHCSR; /**< System Handler Control and State Register */
__IO uint32 CFSR; /**< Configurable Fault Status Register */
__IO uint32 HFSR; /**< Hard Fault Status Register */
/* DFSR is not documented by ST in PM0056 (as of Revision 4), but
* there's a 4 byte hole in the SCB register map docs right where
* it belongs. Since it's specified as "always implemented" in
* the ARM v7-M ARM, I'm assuming its absence is a bug in the ST
* doc, but I haven't proven it. [mbolivar] */
__io uint32 DFSR; /**< Debug Fault Status Register */
__io uint32 MMFAR; /**< Mem Manage Address Register */
__io uint32 BFAR; /**< Bus Fault Address Register */
__IO uint32 DFSR; /**< Debug Fault Status Register */
__IO uint32 MMFAR; /**< Mem Manage Address Register */
__IO uint32 BFAR; /**< Bus Fault Address Register */
#if 0
/* The following registers are implementation-defined according to
* ARM v7-M, and I can't find evidence of their existence in ST's
* docs. I'm removing them. Feel free to yell at me if they do
* exist. [mbolivar]
*/
__io uint32 AFSR; /**< Auxiliary Fault Status Register */
__io uint32 PFR[2]; /**< Processor Feature Register */
__io uint32 DFR; /**< Debug Feature Register */
__io uint32 AFR; /**< Auxiliary Feature Register */
__io uint32 MMFR[4]; /**< Memory Model Feature Register */
__io uint32 ISAR[5]; /**< ISA Feature Register */
__IO uint32 AFSR; /**< Auxiliary Fault Status Register */
__IO uint32 PFR[2]; /**< Processor Feature Register */
__IO uint32 DFR; /**< Debug Feature Register */
__IO uint32 AFR; /**< Auxiliary Feature Register */
__IO uint32 MMFR[4]; /**< Memory Model Feature Register */
__IO uint32 ISAR[5]; /**< ISA Feature Register */
#endif
} scb_reg_map;

18
STM32F3/cores/maple/libmaple/include/libmaple/spi.h
View File

@ -54,15 +54,15 @@ extern "C" {
/** SPI register map type. */
typedef struct spi_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SR; /**< Status register */
__io uint32 DR; /**< Data register */
__io uint32 CRCPR; /**< CRC polynomial register */
__io uint32 RXCRCR; /**< RX CRC register */
__io uint32 TXCRCR; /**< TX CRC register */
__io uint32 I2SCFGR; /**< I2S configuration register */
__io uint32 I2SPR; /**< I2S prescaler register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SR; /**< Status register */
__IO uint32 DR; /**< Data register */
__IO uint32 CRCPR; /**< CRC polynomial register */
__IO uint32 RXCRCR; /**< RX CRC register */
__IO uint32 TXCRCR; /**< TX CRC register */
__IO uint32 I2SCFGR; /**< I2S configuration register */
__IO uint32 I2SPR; /**< I2S prescaler register */
} spi_reg_map;
/*

8
STM32F3/cores/maple/libmaple/include/libmaple/systick.h
View File

@ -41,10 +41,10 @@ extern "C"{
/** SysTick register map type */
typedef struct systick_reg_map {
__io uint32 CSR; /**< Control and status register */
__io uint32 RVR; /**< Reload value register */
__io uint32 CNT; /**< Current value register ("count") */
__io uint32 CVR; /**< Calibration value register */
__IO uint32 CSR; /**< Control and status register */
__IO uint32 RVR; /**< Reload value register */
__IO uint32 CNT; /**< Current value register ("count") */
__IO uint32 CVR; /**< Calibration value register */
} systick_reg_map;
/** SysTick register map base pointer */

62
STM32F3/cores/maple/libmaple/include/libmaple/timer.h
View File

@ -49,26 +49,26 @@ extern "C"{
/** Advanced control timer register map type */
typedef struct timer_adv_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SMCR; /**< Slave mode control register */
__io uint32 DIER; /**< DMA/interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__io uint32 CCMR1; /**< Capture/compare mode register 1 */
__io uint32 CCMR2; /**< Capture/compare mode register 2 */
__io uint32 CCER; /**< Capture/compare enable register */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__io uint32 RCR; /**< Repetition counter register */
__io uint32 CCR1; /**< Capture/compare register 1 */
__io uint32 CCR2; /**< Capture/compare register 2 */
__io uint32 CCR3; /**< Capture/compare register 3 */
__io uint32 CCR4; /**< Capture/compare register 4 */
__io uint32 BDTR; /**< Break and dead-time register */
__io uint32 DCR; /**< DMA control register */
__io uint32 DMAR; /**< DMA address for full transfer */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SMCR; /**< Slave mode control register */
__IO uint32 DIER; /**< DMA/interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
__IO uint32 CCMR1; /**< Capture/compare mode register 1 */
__IO uint32 CCMR2; /**< Capture/compare mode register 2 */
__IO uint32 CCER; /**< Capture/compare enable register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
__IO uint32 RCR; /**< Repetition counter register */
__IO uint32 CCR1; /**< Capture/compare register 1 */
__IO uint32 CCR2; /**< Capture/compare register 2 */
__IO uint32 CCR3; /**< Capture/compare register 3 */
__IO uint32 CCR4; /**< Capture/compare register 4 */
__IO uint32 BDTR; /**< Break and dead-time register */
__IO uint32 DCR; /**< DMA control register */
__IO uint32 DMAR; /**< DMA address for full transfer */
} timer_adv_reg_map;
/* General purpose timer register map type: intentionally omitted.
@ -78,18 +78,18 @@ typedef struct timer_adv_reg_map {
/** Basic timer register map type */
typedef struct timer_bas_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
const uint32 RESERVED1; /**< Reserved */
__io uint32 DIER; /**< DMA/interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__IO uint32 DIER; /**< DMA/interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
const uint32 RESERVED2; /**< Reserved */
const uint32 RESERVED3; /**< Reserved */
const uint32 RESERVED4; /**< Reserved */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
} timer_bas_reg_map;
/*
@ -725,7 +725,7 @@ static inline void timer_set_reload(timer_dev *dev, uint16 arr) {
* @param channel Channel whose compare value to get.
*/
static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) {
__io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
__IO uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
return *ccr;
}
@ -738,7 +738,7 @@ static inline uint16 timer_get_compare(timer_dev *dev, uint8 channel) {
static inline void timer_set_compare(timer_dev *dev,
uint8 channel,
uint16 value) {
__io uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
__IO uint32 *ccr = &(dev->regs).gen->CCR1 + (channel - 1);
*ccr = value;
}
@ -1035,7 +1035,7 @@ static inline void timer_oc_set_mode(timer_dev *dev,
timer_oc_mode mode,
uint8 flags) {
/* channel == 1,2 -> CCMR1; channel == 3,4 -> CCMR2 */
__io uint32 *ccmr = &(dev->regs).gen->CCMR1 + (((channel - 1) >> 1) & 1);
__IO uint32 *ccmr = &(dev->regs).gen->CCMR1 + (((channel - 1) >> 1) & 1);
/* channel == 1,3 -> shift = 0, channel == 2,4 -> shift = 8 */
uint8 shift = 8 * (1 - (channel & 1));

4
STM32F3/cores/maple/libmaple/rcc.c
View File

@ -94,8 +94,8 @@ void rcc_switch_sysclk(rcc_sysclk_src sysclk_src) {
* won't work for you. */
/* Returns the RCC register which controls the clock source. */
static inline __io uint32* rcc_clk_reg(rcc_clk clock) {
return (__io uint32*)((__io uint8*)RCC_BASE + (clock >> 8));
static inline __IO uint32* rcc_clk_reg(rcc_clk clock) {
return (__IO uint32*)((__IO uint8*)RCC_BASE + (clock >> 8));
}
/* Returns a mask in rcc_clk_reg(clock) to be used for turning the

8
STM32F3/cores/maple/libmaple/rcc_private.h
View File

@ -40,16 +40,16 @@ struct rcc_dev_info {
extern const struct rcc_dev_info rcc_dev_table[];
static inline void rcc_do_clk_enable(__io uint32** enable_regs,
static inline void rcc_do_clk_enable(__IO uint32** enable_regs,
rcc_clk_id id) {
__io uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
__IO uint32 *enable_reg = enable_regs[rcc_dev_clk(id)];
uint8 line_num = rcc_dev_table[id].line_num;
bb_peri_set_bit(enable_reg, line_num, 1);
}
static inline void rcc_do_reset_dev(__io uint32** reset_regs,
static inline void rcc_do_reset_dev(__IO uint32** reset_regs,
rcc_clk_id id) {
__io uint32 *reset_reg = reset_regs[rcc_dev_clk(id)];
__IO uint32 *reset_reg = reset_regs[rcc_dev_clk(id)];
uint8 line_num = rcc_dev_table[id].line_num;
bb_peri_set_bit(reset_reg, line_num, 1);
bb_peri_set_bit(reset_reg, line_num, 0);

2
STM32F3/cores/maple/libmaple/stm32f3/f3_adc.c
View File

@ -164,7 +164,7 @@ void adc_set_conv_seq(const adc_dev *dev, const uint8 *channels, uint8 len) {
uint8 i;
uint32 val = 0;
uint8 lshift;
__io uint32 *sqr = &dev->regs->SQR1;
__IO uint32 *sqr = &dev->regs->SQR1;
for (i=0; i<len; i++)
{

2
STM32F3/cores/maple/libmaple/stm32f3/f3_bkp.c
View File

@ -41,7 +41,7 @@ void bkp_init(void) {
rcc_clk_enable(RCC_PWR);
}
inline __io uint32* bkp_data_register(uint8 reg) {
inline __IO uint32* bkp_data_register(uint8 reg) {
if (reg < 1 || reg > BKP_NR_DATA_REGS)
return NULL;
else

6
STM32F3/cores/maple/libmaple/stm32f3/f3_dma.c
View File

@ -86,7 +86,7 @@ static int cfg_dev_ok(dma_dev *dev, dma_tube_config *cfg) {
}
/* Is addr acceptable for use as DMA src/dst? */
static int cfg_mem_ok(__io void *addr) {
static int cfg_mem_ok(__IO void *addr) {
enum dma_atype atype = _dma_addr_type(addr);
return atype == DMA_ATYPE_MEM || atype == DMA_ATYPE_PER;
}
@ -293,7 +293,7 @@ dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
return DMA_TRANSFER_ERROR;
}
void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __IO void *addr) {
dma_channel_reg_map *chan_regs;
ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
@ -302,7 +302,7 @@ void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
chan_regs->CMAR = (uint32)addr;
}
void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
void dma_set_per_addr(dma_dev *dev, dma_channel channel, __IO void *addr) {
dma_channel_reg_map *chan_regs;
ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));

2
STM32F3/cores/maple/libmaple/stm32f3/f3_gpio.c
View File

@ -152,7 +152,7 @@ void gpio_set_modef(gpio_dev *dev,
* @see gpio_set_modef()
*/
void gpio_set_af(gpio_dev *dev, uint8 bit, gpio_af af) {
__io uint32 *afr;
__IO uint32 *afr;
unsigned shift;
uint32 tmp;
if (bit >= 8) {

4
STM32F3/cores/maple/libmaple/stm32f3/f3_rcc.c
View File

@ -121,7 +121,7 @@ void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
}
void rcc_clk_enable(rcc_clk_id id) {
static __io uint32* enable_regs[] = {
static __IO uint32* enable_regs[] = {
[APB1] = &RCC_BASE->APB1ENR,
[APB2] = &RCC_BASE->APB2ENR,
[AHB] = &RCC_BASE->AHBENR,
@ -130,7 +130,7 @@ void rcc_clk_enable(rcc_clk_id id) {
}
void rcc_reset_dev(rcc_clk_id id) {
static __io uint32* reset_regs[] = {
static __IO uint32* reset_regs[] = {
[APB1] = &RCC_BASE->APB1RSTR,
[APB2] = &RCC_BASE->APB2RSTR,
[AHB] = &RCC_BASE->AHBRSTR,

8
STM32F3/cores/maple/libmaple/stm32f3/f3_spi.c
View File

@ -119,10 +119,10 @@ void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
uint16 spi_rx_reg(spi_dev *dev) {
uint8 byte_frame = (dev->regs->CR2 & SPI_CR2_DS) <= SPI_DATA_SIZE_8_BIT;
if (byte_frame) {
__io uint8 *dr8 = (__io uint8 *)&dev->regs->DR; /* we need to access as byte */
__IO uint8 *dr8 = (__IO uint8 *)&dev->regs->DR; /* we need to access as byte */
return (uint16)*dr8;
} else {
__io uint16 *dr16 = (__io uint16 *)&dev->regs->DR; /* we need to access as half-word */
__IO uint16 *dr16 = (__IO uint16 *)&dev->regs->DR; /* we need to access as half-word */
return (uint16)*dr16;
}
}
@ -132,10 +132,10 @@ uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
uint8 byte_frame = (dev->regs->CR2 & SPI_CR2_DS) <= SPI_DATA_SIZE_8_BIT;
while (spi_is_tx_empty(dev) && (txed < len)) {
if (byte_frame) {
__io uint8 *dr8 = (__io uint8 *)&dev->regs->DR; /* we need to access as byte */
__IO uint8 *dr8 = (__IO uint8 *)&dev->regs->DR; /* we need to access as byte */
*dr8 = ((const uint8 *)buf)[txed++];
} else {
__io uint16 *dr16 = (__io uint16 *)&dev->regs->DR; /* we need to access as half-word */
__IO uint16 *dr16 = (__IO uint16 *)&dev->regs->DR; /* we need to access as half-word */
*dr16 = ((const uint16 *)buf)[txed++];
}
}

60
STM32F3/cores/maple/libmaple/stm32f3/include/series/adc.h
View File

@ -45,51 +45,51 @@
* ADC individual register map type.
*/
typedef struct adc_reg_map {
__io uint32 ISR; /**< */
__io uint32 IER; /**< */
__io uint32 CR; /**< */
__io uint32 CFGR; /**< */
__IO uint32 ISR; /**< */
__IO uint32 IER; /**< */
__IO uint32 CR; /**< */
__IO uint32 CFGR; /**< */
uint32 reserved1;
__io uint32 SMPR1; /**< */
__io uint32 SMPR2; /**< */
__IO uint32 SMPR1; /**< */
__IO uint32 SMPR2; /**< */
uint32 reserved2;
__io uint32 TR1; /**< */
__io uint32 TR2; /**< */
__io uint32 TR3; /**< */
__IO uint32 TR1; /**< */
__IO uint32 TR2; /**< */
__IO uint32 TR3; /**< */
uint32 reserved3;
__io uint32 SQR1; /**< */
__io uint32 SQR2; /**< */
__io uint32 SQR3; /**< */
__io uint32 SQR4; /**< */
__io uint32 DR; /**< */
__IO uint32 SQR1; /**< */
__IO uint32 SQR2; /**< */
__IO uint32 SQR3; /**< */
__IO uint32 SQR4; /**< */
__IO uint32 DR; /**< */
uint32 reserved4 [2];
__io uint32 JSQR; /**< */
__IO uint32 JSQR; /**< */
uint32 reserved5 [4];
__io uint32 OFR1; /**< */
__io uint32 OFR2; /**< */
__io uint32 OFR3; /**< */
__io uint32 OFR4; /**< */
__IO uint32 OFR1; /**< */
__IO uint32 OFR2; /**< */
__IO uint32 OFR3; /**< */
__IO uint32 OFR4; /**< */
uint32 reserved6 [4];
__io uint32 JDR1; /**< */
__io uint32 JDR2; /**< */
__io uint32 JDR3; /**< */
__io uint32 JDR4; /**< */
__IO uint32 JDR1; /**< */
__IO uint32 JDR2; /**< */
__IO uint32 JDR3; /**< */
__IO uint32 JDR4; /**< */
uint32 reserved7 [4];
__io uint32 AWD2CR; /**< */
__io uint32 AWD3CR; /**< */
__IO uint32 AWD2CR; /**< */
__IO uint32 AWD3CR; /**< */
uint32 reserved8 [2];
__io uint32 DIFSEL; /**< */
__io uint32 CALFACT; /**< */
__IO uint32 DIFSEL; /**< */
__IO uint32 CALFACT; /**< */
} adc_reg_map;
/*
* ADC master and slave common register map type.
*/
typedef struct adc_common_reg_map {
__io uint32 CSR; /**< */
__IO uint32 CSR; /**< */
uint32 reserved;
__io uint32 CCR; /**< */
__io uint32 CDR; /**< */
__IO uint32 CCR; /**< */
__IO uint32 CDR; /**< */
} adc_common_reg_map;
/** ADC device type. */

32
STM32F3/cores/maple/libmaple/stm32f3/include/series/bkp.h
View File

@ -38,22 +38,22 @@
/** Backup peripheral register map type. */
typedef struct bkp_reg_map {
__io uint32 DR0; ///< Data register 0
__io uint32 DR1; ///< Data register 1
__io uint32 DR2; ///< Data register 2
__io uint32 DR3; ///< Data register 3
__io uint32 DR4; ///< Data register 4
__io uint32 DR5; ///< Data register 5
__io uint32 DR6; ///< Data register 6
__io uint32 DR7; ///< Data register 7
__io uint32 DR8; ///< Data register 8
__io uint32 DR9; ///< Data register 9
__io uint32 DR10; ///< Data register 10
__io uint32 DR11; ///< Data register 11
__io uint32 DR12; ///< Data register 12
__io uint32 DR13; ///< Data register 13
__io uint32 DR14; ///< Data register 14
__io uint32 DR15; ///< Data register 15
__IO uint32 DR0; ///< Data register 0
__IO uint32 DR1; ///< Data register 1
__IO uint32 DR2; ///< Data register 2
__IO uint32 DR3; ///< Data register 3
__IO uint32 DR4; ///< Data register 4
__IO uint32 DR5; ///< Data register 5
__IO uint32 DR6; ///< Data register 6
__IO uint32 DR7; ///< Data register 7
__IO uint32 DR8; ///< Data register 8
__IO uint32 DR9; ///< Data register 9
__IO uint32 DR10; ///< Data register 10
__IO uint32 DR11; ///< Data register 11
__IO uint32 DR12; ///< Data register 12
__IO uint32 DR13; ///< Data register 13
__IO uint32 DR14; ///< Data register 14
__IO uint32 DR15; ///< Data register 15
} bkp_reg_map;
/** Backup peripheral register map base pointer. */

2
STM32F3/cores/maple/libmaple/stm32f3/include/series/comp.h
View File

@ -47,7 +47,7 @@ extern "C"{
* COMP individual register map type.
*/
typedef struct comp_reg_map {
__io uint32 CSR; /**< */
__IO uint32 CSR; /**< */
} comp_reg_map;
/** COMP device type. */

10
STM32F3/cores/maple/libmaple/stm32f3/include/series/crc.h
View File

@ -43,12 +43,12 @@ extern "C"{
/** CRC register map type */
typedef struct crc_reg_map {
__io uint32 DR; /**< Data register */
__io uint32 IDR; /**< Independent data register */
__io uint32 CR; /**< Control register */
__IO uint32 DR; /**< Data register */
__IO uint32 IDR; /**< Independent data register */
__IO uint32 CR; /**< Control register */
uint32 reserved;
__io uint32 INIT; /**< Initial data register */
__io uint32 POL; /**< Polynomial register */
__IO uint32 INIT; /**< Initial data register */
__IO uint32 POL; /**< Polynomial register */
} crc_reg_map;
/*

26
STM32F3/cores/maple/libmaple/stm32f3/include/series/dac.h
View File

@ -40,28 +40,28 @@ extern "C"{
/** STM32F3 DAC register map type. */
typedef struct dac_reg_map {
__io uint32 CR; /**< Control register */
__io uint32 SWTRIGR; /**< Software trigger register */
__io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
__IO uint32 CR; /**< Control register */
__IO uint32 SWTRIGR; /**< Software trigger register */
__IO uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
holding register */
__io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
__IO uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
holding register */
__io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
__IO uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
holding register */
__io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
__IO uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
holding register */
__io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
__IO uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
holding register */
__io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
__IO uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
holding register */
__io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
__IO uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
holding register */
__io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
__IO uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
holding register */
__io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
__IO uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
register */
__io uint32 DOR1; /**< Channel 1 data output register */
__io uint32 DOR2; /**< Channel 2 data output register */
__IO uint32 DOR1; /**< Channel 1 data output register */
__IO uint32 DOR2; /**< Channel 2 data output register */
} dac_reg_map;
//#define DAC1_BASE ((struct dac_reg_map*)0x40007400)

70
STM32F3/cores/maple/libmaple/stm32f3/include/series/dma.h
View File

@ -55,42 +55,42 @@ extern "C"{
* only supports channels 1--5.
*/
typedef struct dma_reg_map {
__io uint32 ISR; /**< Interrupt status register */
__io uint32 IFCR; /**< Interrupt flag clear register */
__io uint32 CCR1; /**< Channel 1 configuration register */
__io uint32 CNDTR1; /**< Channel 1 number of data register */
__io uint32 CPAR1; /**< Channel 1 peripheral address register */
__io uint32 CMAR1; /**< Channel 1 memory address register */
__IO uint32 ISR; /**< Interrupt status register */
__IO uint32 IFCR; /**< Interrupt flag clear register */
__IO uint32 CCR1; /**< Channel 1 configuration register */
__IO uint32 CNDTR1; /**< Channel 1 number of data register */
__IO uint32 CPAR1; /**< Channel 1 peripheral address register */
__IO uint32 CMAR1; /**< Channel 1 memory address register */
const uint32 RESERVED1; /**< Reserved. */
__io uint32 CCR2; /**< Channel 2 configuration register */
__io uint32 CNDTR2; /**< Channel 2 number of data register */
__io uint32 CPAR2; /**< Channel 2 peripheral address register */
__io uint32 CMAR2; /**< Channel 2 memory address register */
__IO uint32 CCR2; /**< Channel 2 configuration register */
__IO uint32 CNDTR2; /**< Channel 2 number of data register */
__IO uint32 CPAR2; /**< Channel 2 peripheral address register */
__IO uint32 CMAR2; /**< Channel 2 memory address register */
const uint32 RESERVED2; /**< Reserved. */
__io uint32 CCR3; /**< Channel 3 configuration register */
__io uint32 CNDTR3; /**< Channel 3 number of data register */
__io uint32 CPAR3; /**< Channel 3 peripheral address register */
__io uint32 CMAR3; /**< Channel 3 memory address register */
__IO uint32 CCR3; /**< Channel 3 configuration register */
__IO uint32 CNDTR3; /**< Channel 3 number of data register */
__IO uint32 CPAR3; /**< Channel 3 peripheral address register */
__IO uint32 CMAR3; /**< Channel 3 memory address register */
const uint32 RESERVED3; /**< Reserved. */
__io uint32 CCR4; /**< Channel 4 configuration register */
__io uint32 CNDTR4; /**< Channel 4 number of data register */
__io uint32 CPAR4; /**< Channel 4 peripheral address register */
__io uint32 CMAR4; /**< Channel 4 memory address register */
__IO uint32 CCR4; /**< Channel 4 configuration register */
__IO uint32 CNDTR4; /**< Channel 4 number of data register */
__IO uint32 CPAR4; /**< Channel 4 peripheral address register */
__IO uint32 CMAR4; /**< Channel 4 memory address register */
const uint32 RESERVED4; /**< Reserved. */
__io uint32 CCR5; /**< Channel 5 configuration register */
__io uint32 CNDTR5; /**< Channel 5 number of data register */
__io uint32 CPAR5; /**< Channel 5 peripheral address register */
__io uint32 CMAR5; /**< Channel 5 memory address register */
__IO uint32 CCR5; /**< Channel 5 configuration register */
__IO uint32 CNDTR5; /**< Channel 5 number of data register */
__IO uint32 CPAR5; /**< Channel 5 peripheral address register */
__IO uint32 CMAR5; /**< Channel 5 memory address register */
const uint32 RESERVED5; /**< Reserved. */
__io uint32 CCR6; /**< Channel 6 configuration register */
__io uint32 CNDTR6; /**< Channel 6 number of data register */
__io uint32 CPAR6; /**< Channel 6 peripheral address register */
__io uint32 CMAR6; /**< Channel 6 memory address register */
__IO uint32 CCR6; /**< Channel 6 configuration register */
__IO uint32 CNDTR6; /**< Channel 6 number of data register */
__IO uint32 CPAR6; /**< Channel 6 peripheral address register */
__IO uint32 CMAR6; /**< Channel 6 memory address register */
const uint32 RESERVED6; /**< Reserved. */
__io uint32 CCR7; /**< Channel 7 configuration register */
__io uint32 CNDTR7; /**< Channel 7 number of data register */
__io uint32 CPAR7; /**< Channel 7 peripheral address register */
__io uint32 CMAR7; /**< Channel 7 memory address register */
__IO uint32 CCR7; /**< Channel 7 configuration register */
__IO uint32 CNDTR7; /**< Channel 7 number of data register */
__IO uint32 CPAR7; /**< Channel 7 peripheral address register */
__IO uint32 CMAR7; /**< Channel 7 memory address register */
const uint32 RESERVED7; /**< Reserved. */
} dma_reg_map;
@ -105,10 +105,10 @@ typedef struct dma_reg_map {
* @see dma_tube_regs()
*/
typedef struct dma_tube_reg_map {
__io uint32 CCR; /**< Channel configuration register */
__io uint32 CNDTR; /**< Channel number of data register */
__io uint32 CPAR; /**< Channel peripheral address register */
__io uint32 CMAR; /**< Channel memory address register */
__IO uint32 CCR; /**< Channel configuration register */
__IO uint32 CNDTR; /**< Channel number of data register */
__IO uint32 CPAR; /**< Channel peripheral address register */
__IO uint32 CMAR; /**< Channel memory address register */
} dma_tube_reg_map;
/** DMA1 channel 1 register map base pointer */
@ -528,7 +528,7 @@ typedef enum dma_request_src {
#define DMA_CHANNEL_NREGS 5 /* accounts for reserved word */
static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube) {
__io uint32 *ccr1 = &dev->regs->CCR1;
__IO uint32 *ccr1 = &dev->regs->CCR1;
return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (tube - 1));
}

16
STM32F3/cores/maple/libmaple/stm32f3/include/series/flash.h
View File

@ -50,14 +50,14 @@ extern "C"{
/** @brief STM32F3 Flash register map type */
typedef struct flash_reg_map {
__io uint32 ACR; /**< Access control register */
__io uint32 KEYR; /**< Key register */
__io uint32 OPTKEYR; /**< OPTKEY register */
__io uint32 SR; /**< Status register */
__io uint32 CR; /**< Control register */
__io uint32 AR; /**< Address register */
__io uint32 OBR; /**< Option byte register */
__io uint32 WRPR; /**< Write protection register */
__IO uint32 ACR; /**< Access control register */
__IO uint32 KEYR; /**< Key register */
__IO uint32 OPTKEYR; /**< OPTKEY register */
__IO uint32 SR; /**< Status register */
__IO uint32 CR; /**< Control register */
__IO uint32 AR; /**< Address register */
__IO uint32 OBR; /**< Option byte register */
__IO uint32 WRPR; /**< Write protection register */
} flash_reg_map;
#define FLASH_BASE ((struct flash_reg_map*)0x40022000)

8
STM32F3/cores/maple/libmaple/stm32f3/include/series/fpu.h
View File

@ -46,10 +46,10 @@ extern "C"{
/** FPU register map type */
typedef struct fpu_reg_map {
__io uint32 CPACR; /**< coprocessor access control register */
__io uint32 FPCCR; /**< floating-point context control register */
__io uint32 FPCAR; /**< floating-point context address register */
__io uint32 FPDSCR; /**< floating-point default status control register */
__IO uint32 CPACR; /**< coprocessor access control register */
__IO uint32 FPCCR; /**< floating-point context control register */
__IO uint32 FPCAR; /**< floating-point context address register */
__IO uint32 FPDSCR; /**< floating-point default status control register */
} fpu_reg_map;
#define FPU_BASE ((struct fpu_reg_map*)(SCB_BASE + 0x88))

22
STM32F3/cores/maple/libmaple/stm32f3/include/series/gpio.h
View File

@ -46,17 +46,17 @@ extern "C"{
/** GPIO register map type */
typedef struct gpio_reg_map {
__io uint32 MODER; /**< Mode register */
__io uint32 OTYPER; /**< Output type register */
__io uint32 OSPEEDR; /**< Output speed register */
__io uint32 PUPDR; /**< Pull-up/pull-down register */
__io uint32 IDR; /**< Input data register */
__io uint32 ODR; /**< Output data register */
__io uint32 BSRR; /**< Bit set/reset register */
__io uint32 LCKR; /**< Configuration lock register */
__io uint32 AFRL; /**< Alternate function low register */
__io uint32 AFRH; /**< Alternate function high register */
__io uint32 BRR; /**< Port bit reset register */
__IO uint32 MODER; /**< Mode register */
__IO uint32 OTYPER; /**< Output type register */
__IO uint32 OSPEEDR; /**< Output speed register */
__IO uint32 PUPDR; /**< Pull-up/pull-down register */
__IO uint32 IDR; /**< Input data register */
__IO uint32 ODR; /**< Output data register */
__IO uint32 BSRR; /**< Bit set/reset register */
__IO uint32 LCKR; /**< Configuration lock register */
__IO uint32 AFRL; /**< Alternate function low register */
__IO uint32 AFRH; /**< Alternate function high register */
__IO uint32 BRR; /**< Port bit reset register */
} gpio_reg_map;
/** GPIO port A register map base pointer */

22
STM32F3/cores/maple/libmaple/stm32f3/include/series/i2c.h
View File

@ -47,17 +47,17 @@ extern "C"{
/** I2C register map type */
typedef struct i2c_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 OAR1; /**< Own address register 1 */
__io uint32 OAR2; /**< Own address register 2 */
__io uint32 TIMINGR; /**< Timing register */
__io uint32 TIMEOUTR; /**< Timeout register */
__io uint32 ISR; /**< Interrupt and status register */
__io uint32 ICR; /**< Interrupt clear register */
__io uint32 PECR; /**< PEC register */
__io uint32 RXDR; /**< Receive data register */
__io uint32 TXDR; /**< Transmit data register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 OAR1; /**< Own address register 1 */
__IO uint32 OAR2; /**< Own address register 2 */
__IO uint32 TIMINGR; /**< Timing register */
__IO uint32 TIMEOUTR; /**< Timeout register */
__IO uint32 ISR; /**< Interrupt and status register */
__IO uint32 ICR; /**< Interrupt clear register */
__IO uint32 PECR; /**< PEC register */
__IO uint32 RXDR; /**< Receive data register */
__IO uint32 TXDR; /**< Transmit data register */
} i2c_reg_map;
extern i2c_dev* const I2C1;

2
STM32F3/cores/maple/libmaple/stm32f3/include/series/opamp.h
View File

@ -47,7 +47,7 @@ extern "C"{
* OpAmp individual register map type.
*/
typedef struct opamp_reg_map {
__io uint32 CSR; /**< */
__IO uint32 CSR; /**< */
} opamp_reg_map;
/** OpAmp device type. */

26
STM32F3/cores/maple/libmaple/stm32f3/include/series/rcc.h
View File

@ -47,19 +47,19 @@ extern "C"{
/** STM32F3 RCC register map type */
typedef struct rcc_reg_map {
__io uint32 CR; /**< Clock control register */
__io uint32 CFGR; /**< Clock configuration register */
__io uint32 CIR; /**< Clock interrupt register */
__io uint32 APB2RSTR; /**< APB2 peripheral reset register */
__io uint32 APB1RSTR; /**< APB1 peripheral reset register */
__io uint32 AHBENR; /**< AHB peripheral clock enable register */
__io uint32 APB2ENR; /**< APB2 peripheral clock enable register */
__io uint32 APB1ENR; /**< APB1 peripheral clock enable register */
__io uint32 BDCR; /**< Backup domain control register */
__io uint32 CSR; /**< Control/status register */
__io uint32 AHBRSTR; /**< AHB peripheral reset register */
__io uint32 CFGR2; /**< Control/status register 2 */
__io uint32 CFGR3; /**< Control/status register 3 */
__IO uint32 CR; /**< Clock control register */
__IO uint32 CFGR; /**< Clock configuration register */
__IO uint32 CIR; /**< Clock interrupt register */
__IO uint32 APB2RSTR; /**< APB2 peripheral reset register */
__IO uint32 APB1RSTR; /**< APB1 peripheral reset register */
__IO uint32 AHBENR; /**< AHB peripheral clock enable register */
__IO uint32 APB2ENR; /**< APB2 peripheral clock enable register */
__IO uint32 APB1ENR; /**< APB1 peripheral clock enable register */
__IO uint32 BDCR; /**< Backup domain control register */
__IO uint32 CSR; /**< Control/status register */
__IO uint32 AHBRSTR; /**< AHB peripheral reset register */
__IO uint32 CFGR2; /**< Control/status register 2 */
__IO uint32 CFGR3; /**< Control/status register 3 */
} rcc_reg_map;
#define RCC_BASE ((struct rcc_reg_map*)0x40021000)

8
STM32F3/cores/maple/libmaple/stm32f3/include/series/syscfg.h
View File

@ -47,10 +47,10 @@ extern "C" {
* @brief SYSCFG register map type.
*/
typedef struct syscfg_reg_map {
__io uint32 CFGR1; /**< Configuration register 1*/
__io uint32 RCR; /**< CCM SRAM protection register */
__io uint32 EXTICR[4]; /**< External Interrupt configuration register */
__io uint32 CFGR2; /**< Configuration register 2 */
__IO uint32 CFGR1; /**< Configuration register 1*/
__IO uint32 RCR; /**< CCM SRAM protection register */
__IO uint32 EXTICR[4]; /**< External Interrupt configuration register */
__IO uint32 CFGR2; /**< Configuration register 2 */
} syscfg_reg_map;
/** SYSCFG register map base pointer */

36
STM32F3/cores/maple/libmaple/stm32f3/include/series/timer.h
View File

@ -44,26 +44,26 @@
/** STM32F1 general purpose timer register map type */
typedef struct timer_gen_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 SMCR; /**< Slave mode control register */
__io uint32 DIER; /**< DMA/Interrupt enable register */
__io uint32 SR; /**< Status register */
__io uint32 EGR; /**< Event generation register */
__io uint32 CCMR1; /**< Capture/compare mode register 1 */
__io uint32 CCMR2; /**< Capture/compare mode register 2 */
__io uint32 CCER; /**< Capture/compare enable register */
__io uint32 CNT; /**< Counter */
__io uint32 PSC; /**< Prescaler */
__io uint32 ARR; /**< Auto-reload register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 SMCR; /**< Slave mode control register */
__IO uint32 DIER; /**< DMA/Interrupt enable register */
__IO uint32 SR; /**< Status register */
__IO uint32 EGR; /**< Event generation register */
__IO uint32 CCMR1; /**< Capture/compare mode register 1 */
__IO uint32 CCMR2; /**< Capture/compare mode register 2 */
__IO uint32 CCER; /**< Capture/compare enable register */
__IO uint32 CNT; /**< Counter */
__IO uint32 PSC; /**< Prescaler */
__IO uint32 ARR; /**< Auto-reload register */
const uint32 RESERVED1; /**< Reserved */
__io uint32 CCR1; /**< Capture/compare register 1 */
__io uint32 CCR2; /**< Capture/compare register 2 */
__io uint32 CCR3; /**< Capture/compare register 3 */
__io uint32 CCR4; /**< Capture/compare register 4 */
__IO uint32 CCR1; /**< Capture/compare register 1 */
__IO uint32 CCR2; /**< Capture/compare register 2 */
__IO uint32 CCR3; /**< Capture/compare register 3 */
__IO uint32 CCR4; /**< Capture/compare register 4 */
const uint32 RESERVED2; /**< Reserved */
__io uint32 DCR; /**< DMA control register */
__io uint32 DMAR; /**< DMA address for full transfer */
__IO uint32 DCR; /**< DMA control register */
__IO uint32 DMAR; /**< DMA address for full transfer */
} timer_gen_reg_map;
struct timer_adv_reg_map;

22
STM32F3/cores/maple/libmaple/stm32f3/include/series/usart.h
View File

@ -45,18 +45,18 @@ extern "C"{
/** USART register map type */
typedef struct usart_reg_map {
__io uint32 CR1; /**< Control register 1 */
__io uint32 CR2; /**< Control register 2 */
__io uint32 CR3; /**< Control register 3 */
__io uint32 BRR; /**< Baud rate register */
__io uint32 GTPR; /**< Guard time and prescaler register */
__io uint32 RTOR; /**< Receiver timeout register */
__io uint32 RQR; /**< Request register */
__io uint32 SR; /**< ISR Interrupt and status register */
__io uint32 ICR; /**< Interrupt clear register */
__io uint16 RDR; /**< Receive data register */
__IO uint32 CR1; /**< Control register 1 */
__IO uint32 CR2; /**< Control register 2 */
__IO uint32 CR3; /**< Control register 3 */
__IO uint32 BRR; /**< Baud rate register */
__IO uint32 GTPR; /**< Guard time and prescaler register */
__IO uint32 RTOR; /**< Receiver timeout register */
__IO uint32 RQR; /**< Request register */
__IO uint32 SR; /**< ISR Interrupt and status register */
__IO uint32 ICR; /**< Interrupt clear register */
__IO uint16 RDR; /**< Receive data register */
uint16 RESERVED1;
__io uint16 TDR; /**< Transmit data register */
__IO uint16 TDR; /**< Transmit data register */
uint16 RESERVED2;
} usart_reg_map;

54
STM32F3/cores/maple/libmaple/usb/usb_reg_map.h
View File

@ -42,13 +42,13 @@
/** USB register map type */
typedef struct usb_reg_map {
__io uint32 EP[USB_NR_EP_REGS]; /**< Endpoint registers */
__IO uint32 EP[USB_NR_EP_REGS]; /**< Endpoint registers */
const uint32 RESERVED[8]; /**< Reserved */
__io uint32 CNTR; /**< Control register */
__io uint32 ISTR; /**< Interrupt status register */
__io uint32 FNR; /**< Frame number register */
__io uint32 DADDR; /**< Device address */
__io uint32 BTABLE; /**< @brief Buffer table address
__IO uint32 CNTR; /**< Control register */
__IO uint32 ISTR; /**< Interrupt status register */
__IO uint32 FNR; /**< Frame number register */
__IO uint32 DADDR; /**< Device address */
__IO uint32 BTABLE; /**< @brief Buffer table address
*
* Address offset within the USB
* packet memory area which points
@ -340,7 +340,7 @@ static inline void usb_clear_status_out(uint8 ep) {
*
* The USB PMA is SRAM shared between USB and CAN. The USB peripheral
* accesses this memory directly via the packet buffer interface. */
#define USB_PMA_BASE ((__io void*)0x40006000)
#define USB_PMA_BASE ((__IO void*)0x40006000)
/*
* PMA conveniences
@ -367,42 +367,42 @@ union usb_btable_ent;
/* Bidirectional endpoint BTABLE entry */
typedef struct usb_btable_bidi {
__io uint16 addr_tx; const uint16 PAD1;
__io uint16 count_tx; const uint16 PAD2;
__io uint16 addr_rx; const uint16 PAD3;
__io uint16 count_rx; const uint16 PAD4;
__IO uint16 addr_tx; const uint16 PAD1;
__IO uint16 count_tx; const uint16 PAD2;
__IO uint16 addr_rx; const uint16 PAD3;
__IO uint16 count_rx; const uint16 PAD4;
} usb_btable_bidi;
/* Unidirectional receive-only endpoint BTABLE entry */
typedef struct usb_btable_uni_rx {
__io uint16 empty1; const uint16 PAD1;
__io uint16 empty2; const uint16 PAD2;
__io uint16 addr_rx; const uint16 PAD3;
__io uint16 count_rx; const uint16 PAD4;
__IO uint16 empty1; const uint16 PAD1;
__IO uint16 empty2; const uint16 PAD2;
__IO uint16 addr_rx; const uint16 PAD3;
__IO uint16 count_rx; const uint16 PAD4;
} usb_btable_uni_rx;
/* Unidirectional transmit-only endpoint BTABLE entry */
typedef struct usb_btable_uni_tx {
__io uint16 addr_tx; const uint16 PAD1;
__io uint16 count_tx; const uint16 PAD2;
__io uint16 empty1; const uint16 PAD3;
__io uint16 empty2; const uint16 PAD4;
__IO uint16 addr_tx; const uint16 PAD1;
__IO uint16 count_tx; const uint16 PAD2;
__IO uint16 empty1; const uint16 PAD3;
__IO uint16 empty2; const uint16 PAD4;
} usb_btable_uni_tx;
/* Double-buffered transmission endpoint BTABLE entry */
typedef struct usb_btable_dbl_tx {
__io uint16 addr_tx0; const uint16 PAD1;
__io uint16 count_tx0; const uint16 PAD2;
__io uint16 addr_tx1; const uint16 PAD3;
__io uint16 count_tx1; const uint16 PAD4;
__IO uint16 addr_tx0; const uint16 PAD1;
__IO uint16 count_tx0; const uint16 PAD2;
__IO uint16 addr_tx1; const uint16 PAD3;
__IO uint16 count_tx1; const uint16 PAD4;
} usb_btable_dbl_tx;
/* Double-buffered reception endpoint BTABLE entry */
typedef struct usb_btable_dbl_rx {
__io uint16 addr_rx0; const uint16 PAD1;
__io uint16 count_rx0; const uint16 PAD2;
__io uint16 addr_rx1; const uint16 PAD3;
__io uint16 count_rx1; const uint16 PAD4;
__IO uint16 addr_rx0; const uint16 PAD1;
__IO uint16 count_rx0; const uint16 PAD2;
__IO uint16 addr_rx1; const uint16 PAD3;
__IO uint16 count_rx1; const uint16 PAD4;
} usb_btable_dbl_rx;
/* TODO isochronous endpoint entries */

4
STM32F4/cores/maple/libmaple/adc.c
View File

@ -137,8 +137,8 @@ void adc_calibrate(const adc_dev *dev)
{
/*
#ifndef STM32F2
__io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
__io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
__IO uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
__IO uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
*rstcal_bit = 1;
while (*rstcal_bit)

46
STM32F4/cores/maple/libmaple/adc.h
View File

@ -44,9 +44,9 @@ extern "C"{
typedef struct
{
__io uint32 CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
__io uint32 CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
__io uint32 CDR; /*!< ADC common regular data register for dual
__IO uint32 CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
__IO uint32 CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
__IO uint32 CDR; /*!< ADC common regular data register for dual
AND triple modes, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
#define ADC_COMMON ((ADC_Common_TypeDef *) 0x40012300)
@ -54,26 +54,26 @@ typedef struct
/** ADC register map type. */
typedef struct adc_reg_map {
__io uint32 SR; ///< Status register
__io uint32 CR1; ///< Control register 1
__io uint32 CR2; ///< Control register 2
__io uint32 SMPR1; ///< Sample time register 1
__io uint32 SMPR2; ///< Sample time register 2
__io uint32 JOFR1; ///< Injected channel data offset register 1
__io uint32 JOFR2; ///< Injected channel data offset register 2
__io uint32 JOFR3; ///< Injected channel data offset register 3
__io uint32 JOFR4; ///< Injected channel data offset register 4
__io uint32 HTR; ///< Watchdog high threshold register
__io uint32 LTR; ///< Watchdog low threshold register
__io uint32 SQR1; ///< Regular sequence register 1
__io uint32 SQR2; ///< Regular sequence register 2
__io uint32 SQR3; ///< Regular sequence register 3
__io uint32 JSQR; ///< Injected sequence register
__io uint32 JDR1; ///< Injected data register 1
__io uint32 JDR2; ///< Injected data register 2
__io uint32 JDR3; ///< Injected data register 3
__io uint32 JDR4; ///< Injected data register 4
__io uint32 DR; ///< Regular data register
__IO uint32 SR; ///< Status register
__IO uint32 CR1; ///< Control register 1
__IO uint32 CR2; ///< Control register 2
__IO uint32 SMPR1; ///< Sample time register 1
__IO uint32 SMPR2; ///< Sample time register 2
__IO uint32 JOFR1; ///< Injected channel data offset register 1
__IO uint32 JOFR2; ///< Injected channel data offset register 2
__IO uint32 JOFR3; ///< Injected channel data offset register 3
__IO uint32 JOFR4; ///< Injected channel data offset register 4
__IO uint32 HTR; ///< Watchdog high threshold register
__IO uint32 LTR; ///< Watchdog low threshold register
__IO uint32 SQR1; ///< Regular sequence register 1
__IO uint32 SQR2; ///< Regular sequence register 2
__IO uint32 SQR3; ///< Regular sequence register 3
__IO uint32 JSQR; ///< Injected sequence register
__IO uint32 JDR1; ///< Injected data register 1
__IO uint32 JDR2; ///< Injected data register 2
__IO uint32 JDR3; ///< Injected data register 3
__IO uint32 JDR4; ///< Injected data register 4
__IO uint32 DR; ///< Regular data register
} adc_reg_map;
/** ADC device type. */

8
STM32F4/cores/maple/libmaple/bkp.c
View File

@ -34,7 +34,7 @@
#include "rcc.h"
#include "bitband.h"
static inline __io uint32* data_register(uint8 reg);
static inline __IO uint32* data_register(uint8 reg);
bkp_dev bkp = {
.regs = BKP_BASE,
@ -78,7 +78,7 @@ void bkp_disable_writes(void) {
* medium-density devices, 42 on high-density devices).
*/
uint16 bkp_read(uint8 reg) {
__io uint32* dr = data_register(reg);
__IO uint32* dr = data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return 0;
@ -97,7 +97,7 @@ uint16 bkp_read(uint8 reg) {
* @see bkp_enable_writes()
*/
void bkp_write(uint8 reg, uint16 val) {
__io uint32* dr = data_register(reg);
__IO uint32* dr = data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return;
@ -112,7 +112,7 @@ void bkp_write(uint8 reg, uint16 val) {
*/
#define NR_LOW_DRS 10
static inline __io uint32* data_register(uint8 reg) {
static inline __IO uint32* data_register(uint8 reg) {
if (reg < 1 || reg > BKP_NR_DATA_REGS) {
return 0;
}

90
STM32F4/cores/maple/libmaple/bkp.h
View File

@ -47,54 +47,54 @@ extern "C" {
/** Backup peripheral register map type. */
typedef struct bkp_reg_map {
const uint32 RESERVED1; ///< Reserved
__io uint32 DR1; ///< Data register 1
__io uint32 DR2; ///< Data register 2
__io uint32 DR3; ///< Data register 3
__io uint32 DR4; ///< Data register 4
__io uint32 DR5; ///< Data register 5
__io uint32 DR6; ///< Data register 6
__io uint32 DR7; ///< Data register 7
__io uint32 DR8; ///< Data register 8
__io uint32 DR9; ///< Data register 9
__io uint32 DR10; ///< Data register 10
__io uint32 RTCCR; ///< RTC control register
__io uint32 CR; ///< Control register
__io uint32 CSR; ///< Control and status register
__IO uint32 DR1; ///< Data register 1
__IO uint32 DR2; ///< Data register 2
__IO uint32 DR3; ///< Data register 3
__IO uint32 DR4; ///< Data register 4
__IO uint32 DR5; ///< Data register 5
__IO uint32 DR6; ///< Data register 6
__IO uint32 DR7; ///< Data register 7
__IO uint32 DR8; ///< Data register 8
__IO uint32 DR9; ///< Data register 9
__IO uint32 DR10; ///< Data register 10
__IO uint32 RTCCR; ///< RTC control register
__IO uint32 CR; ///< Control register
__IO uint32 CSR; ///< Control and status register
#ifdef STM32_HIGH_DENSITY
const uint32 RESERVED2; ///< Reserved
const uint32 RESERVED3; ///< Reserved
__io uint32 DR11; ///< Data register 11
__io uint32 DR12; ///< Data register 12
__io uint32 DR13; ///< Data register 13
__io uint32 DR14; ///< Data register 14
__io uint32 DR15; ///< Data register 15
__io uint32 DR16; ///< Data register 16
__io uint32 DR17; ///< Data register 17
__io uint32 DR18; ///< Data register 18
__io uint32 DR19; ///< Data register 19
__io uint32 DR20; ///< Data register 20
__io uint32 DR21; ///< Data register 21
__io uint32 DR22; ///< Data register 22
__io uint32 DR23; ///< Data register 23
__io uint32 DR24; ///< Data register 24
__io uint32 DR25; ///< Data register 25
__io uint32 DR26; ///< Data register 26
__io uint32 DR27; ///< Data register 27
__io uint32 DR28; ///< Data register 28
__io uint32 DR29; ///< Data register 29
__io uint32 DR30; ///< Data register 30
__io uint32 DR31; ///< Data register 31
__io uint32 DR32; ///< Data register 32
__io uint32 DR33; ///< Data register 33
__io uint32 DR34; ///< Data register 34
__io uint32 DR35; ///< Data register 35
__io uint32 DR36; ///< Data register 36
__io uint32 DR37; ///< Data register 37
__io uint32 DR38; ///< Data register 38
__io uint32 DR39; ///< Data register 39
__io uint32 DR40; ///< Data register 40
__io uint32 DR41; ///< Data register 41
__io uint32 DR42; ///< Data register 42
__IO uint32 DR11; ///< Data register 11
__IO uint32 DR12; ///< Data register 12
__IO uint32 DR13; ///< Data register 13
__IO uint32 DR14; ///< Data register 14
__IO uint32 DR15; ///< Data register 15
__IO uint32 DR16; ///< Data register 16
__IO uint32 DR17; ///< Data register 17
__IO uint32 DR18; ///< Data register 18
__IO uint32 DR19; ///< Data register 19
__IO uint32 DR20; ///< Data register 20
__IO uint32 DR21; ///< Data register 21
__IO uint32 DR22; ///< Data register 22
__IO uint32 DR23; ///< Data register 23
__IO uint32 DR24; ///< Data register 24
__IO uint32 DR25; ///< Data register 25
__IO uint32 DR26; ///< Data register 26
__IO uint32 DR27; ///< Data register 27
__IO uint32 DR28; ///< Data register 28
__IO uint32 DR29; ///< Data register 29
__IO uint32 DR30; ///< Data register 30
__IO uint32 DR31; ///< Data register 31
__IO uint32 DR32; ///< Data register 32
__IO uint32 DR33; ///< Data register 33
__IO uint32 DR34; ///< Data register 34
__IO uint32 DR35; ///< Data register 35
__IO uint32 DR36; ///< Data register 36
__IO uint32 DR37; ///< Data register 37
__IO uint32 DR38; ///< Data register 38
__IO uint32 DR39; ///< Data register 39
__IO uint32 DR40; ///< Data register 40
__IO uint32 DR41; ///< Data register 41
__IO uint32 DR42; ///< Data register 42
#endif
} bkp_reg_map;

26
STM32F4/cores/maple/libmaple/dac.h
View File

@ -46,28 +46,28 @@ extern "C"{
/** DAC register map. */
typedef struct dac_reg_map {
__io uint32 CR; /**< Control register */
__io uint32 SWTRIGR; /**< Software trigger register */
__io uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
__IO uint32 CR; /**< Control register */
__IO uint32 SWTRIGR; /**< Software trigger register */
__IO uint32 DHR12R1; /**< Channel 1 12-bit right-aligned data
holding register */
__io uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
__IO uint32 DHR12L1; /**< Channel 1 12-bit left-aligned data
holding register */
__io uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
__IO uint32 DHR8R1; /**< Channel 1 8-bit left-aligned data
holding register */
__io uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
__IO uint32 DHR12R2; /**< Channel 2 12-bit right-aligned data
holding register */
__io uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
__IO uint32 DHR12L2; /**< Channel 2 12-bit left-aligned data
holding register */
__io uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
__IO uint32 DHR8R2; /**< Channel 2 8-bit left-aligned data
holding register */
__io uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
__IO uint32 DHR12RD; /**< Dual DAC 12-bit right-aligned data
holding register */
__io uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
__IO uint32 DHR12LD; /**< Dual DAC 12-bit left-aligned data
holding register */
__io uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
__IO uint32 DHR8RD; /**< Dual DAC 8-bit right-aligned data holding
register */
__io uint32 DOR1; /**< Channel 1 data output register */
__io uint32 DOR2; /**< Channel 2 data output register */
__IO uint32 DOR1; /**< Channel 1 data output register */
__IO uint32 DOR2; /**< Channel 2 data output register */
} dac_reg_map;
/** DAC register map base address */

26
STM32F4/cores/maple/libmaple/dmaF4.h
View File

@ -57,22 +57,22 @@ extern "C"{
*
*/
typedef struct dma_stream_t {
__io uint32 CR; /**< Stream configuration register */
__io uint32 NDTR; /**< Stream number of data register */
__io uint32 PAR; /**< Stream peripheral address register */
__io uint32 M0AR; /**< Stream memory address register 0 */
__io uint32 M1AR; /**< Stream memory address register 1 */
__io uint32 FCR; /**< Stream FIFO configuration register */
__IO uint32 CR; /**< Stream configuration register */
__IO uint32 NDTR; /**< Stream number of data register */
__IO uint32 PAR; /**< Stream peripheral address register */
__IO uint32 M0AR; /**< Stream memory address register 0 */
__IO uint32 M1AR; /**< Stream memory address register 1 */
__IO uint32 FCR; /**< Stream FIFO configuration register */
} dma_stream_t;
/**
* @brief DMA register map type.
*
*/
typedef struct dma_reg_map {
__io uint32 LISR; /**< Low interrupt status register */
__io uint32 HISR; /**< High interrupt status register */
__io uint32 LIFCR; /**< Low interrupt flag clear register */
__io uint32 HIFCR; /**< High interrupt flag clear register */
__IO uint32 LISR; /**< Low interrupt status register */
__IO uint32 HISR; /**< High interrupt status register */
__IO uint32 LIFCR; /**< Low interrupt flag clear register */
__IO uint32 HIFCR; /**< High interrupt flag clear register */
dma_stream_t STREAM[8];
} dma_reg_map;
@ -255,9 +255,9 @@ static inline void dma_setup_transfer(dma_dev *dev,
dma_stream stream,
dma_channel channel,
dma_xfer_size trx_size,
__io void *peripheral_address,
__io void *memory_address0,
__io void *memory_address1,
__IO void *peripheral_address,
__IO void *memory_address0,
__IO void *memory_address1,
uint32 flags)
{
dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable

12
STM32F4/cores/maple/libmaple/exti.h
View File

@ -43,12 +43,12 @@ extern "C"{
/** EXTI register map type */
typedef struct exti_reg_map {
__io uint32 IMR; /**< Interrupt mask register */
__io uint32 EMR; /**< Event mask register */
__io uint32 RTSR; /**< Rising trigger selection register */
__io uint32 FTSR; /**< Falling trigger selection register */
__io uint32 SWIER; /**< Software interrupt event register */
__io uint32 PR; /**< Pending register */
__IO uint32 IMR; /**< Interrupt mask register */
__IO uint32 EMR; /**< Event mask register */
__IO uint32 RTSR; /**< Rising trigger selection register */
__IO uint32 FTSR; /**< Falling trigger selection register */
__IO uint32 SWIER; /**< Software interrupt event register */
__IO uint32 PR; /**< Pending register */
} exti_reg_map;
/** EXTI register map base pointer */

16
STM32F4/cores/maple/libmaple/flash.h
View File

@ -41,14 +41,14 @@ extern "C"{
/** Flash register map type */
typedef struct flash_reg_map {
__io uint32 ACR; /**< Access control register */
__io uint32 KEYR; /**< Key register */
__io uint32 OPTKEYR; /**< OPTKEY register */
__io uint32 SR; /**< Status register */
__io uint32 CR; /**< Control register */
__io uint32 AR; /**< Address register */
__io uint32 OBR; /**< Option byte register */
__io uint32 WRPR; /**< Write protection register */
__IO uint32 ACR; /**< Access control register */
__IO uint32 KEYR; /**< Key register */
__IO uint32 OPTKEYR; /**< OPTKEY register */
__IO uint32 SR; /**< Status register */
__IO uint32 CR; /**< Control register */
__IO uint32 AR; /**< Address register */
__IO uint32 OBR; /**< Option byte register */
__IO uint32 WRPR; /**< Write protection register */
} flash_reg_map;
/** Flash register map base pointer */

60
STM32F4/cores/maple/libmaple/fsmc.h
View File

@ -55,42 +55,42 @@ extern "C"{
/** FSMC register map type */
typedef struct fsmc_reg_map {
__io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
__io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
__io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
__io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
__io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
__io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
__io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
__io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
__IO uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
__IO uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
__IO uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
__IO uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
__IO uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
__IO uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
__IO uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
__IO uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
const uint32 RESERVED1[16]; /**< Reserved */
__io uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
__io uint32 SR2; /**< FIFO status and interrupt register 2 */
__io uint32 PMEM2; /**< Common memory space timing register 2 */
__io uint32 PATT2; /**< Attribute memory space timing register 2 */
__IO uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
__IO uint32 SR2; /**< FIFO status and interrupt register 2 */
__IO uint32 PMEM2; /**< Common memory space timing register 2 */
__IO uint32 PATT2; /**< Attribute memory space timing register 2 */
const uint32 RESERVED2; /**< Reserved */
__io uint32 ECCR2; /**< ECC result register 2 */
__IO uint32 ECCR2; /**< ECC result register 2 */
const uint32 RESERVED3[2]; /**< Reserved */
__io uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
__io uint32 SR3; /**< FIFO status and interrupt register 3 */
__io uint32 PMEM3; /**< Common memory space timing register 3 */
__io uint32 PATT3; /**< Attribute memory space timing register 3 */
__IO uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
__IO uint32 SR3; /**< FIFO status and interrupt register 3 */
__IO uint32 PMEM3; /**< Common memory space timing register 3 */
__IO uint32 PATT3; /**< Attribute memory space timing register 3 */
const uint32 RESERVED4; /**< Reserved */
__io uint32 ECCR3; /**< ECC result register 3 */
__IO uint32 ECCR3; /**< ECC result register 3 */
const uint32 RESERVED5[2]; /**< Reserved */
__io uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
__io uint32 SR4; /**< FIFO status and interrupt register 4 */
__io uint32 PMEM4; /**< Common memory space timing register 4 */
__io uint32 PATT4; /**< Attribute memory space timing register 4 */
__io uint32 PIO4; /**< I/O space timing register 4 */
__IO uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
__IO uint32 SR4; /**< FIFO status and interrupt register 4 */
__IO uint32 PMEM4; /**< Common memory space timing register 4 */
__IO uint32 PATT4; /**< Attribute memory space timing register 4 */
__IO uint32 PIO4; /**< I/O space timing register 4 */
const uint32 RESERVED6[20]; /**< Reserved */
__io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
__IO uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
const uint32 RESERVED7; /**< Reserved */
__io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
__IO uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
const uint32 RESERVED8; /**< Reserved */
__io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
__IO uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
const uint32 RESERVED9; /**< Reserved */
__io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
__IO uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
} __attribute__((packed)) fsmc_reg_map;
#define __FSMCB 0xA0000000
@ -100,10 +100,10 @@ typedef struct fsmc_reg_map {
/** FSMC NOR/PSRAM register map type */
typedef struct fsmc_nor_psram_reg_map {
__io uint32 BCR; /**< Chip-select control register */
__io uint32 BTR; /**< Chip-select timing register */
__IO uint32 BCR; /**< Chip-select control register */
__IO uint32 BTR; /**< Chip-select timing register */
const uint32 RESERVED[63]; /**< Reserved */
__io uint32 BWTR; /**< Write timing register */
__IO uint32 BWTR; /**< Write timing register */
} fsmc_nor_psram_reg_map;
/** FSMC NOR/PSRAM base pointer 1 */

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