Changes tabs for spaces.
This commit is contained in:
victorpv
GitHub
parent
b892004cc2
commit
910072c7db
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@ -94,14 +94,14 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
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SPIClass::SPIClass(uint32 spi_num) {
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_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
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_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
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switch (spi_num) {
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#if BOARD_NR_SPI >= 1
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case 1:
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_currentSetting->spi_d = SPI1;
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_spi1_this = (void*) this;
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_spi1_this = (void*) this;
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break;
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#endif
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#if BOARD_NR_SPI >= 2
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@ -119,25 +119,25 @@ SPIClass::SPIClass(uint32 spi_num) {
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default:
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ASSERT(0);
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}
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// Init things specific to each SPI device
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// clock divider setup is a bit of hack, and needs to be improved at a later date.
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_settings[0].spi_d = SPI1;
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_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
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_settings[0].spiDmaDev = DMA1;
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_settings[0].spiTxDmaChannel = DMA_CH3;
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_settings[0].spiRxDmaChannel = DMA_CH2;
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_settings[1].spi_d = SPI2;
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_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
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_settings[1].spiDmaDev = DMA1;
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_settings[1].spiTxDmaChannel = DMA_CH5;
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_settings[1].spiRxDmaChannel = DMA_CH4;
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// Init things specific to each SPI device
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// clock divider setup is a bit of hack, and needs to be improved at a later date.
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_settings[0].spi_d = SPI1;
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_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
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_settings[0].spiDmaDev = DMA1;
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_settings[0].spiTxDmaChannel = DMA_CH3;
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_settings[0].spiRxDmaChannel = DMA_CH2;
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_settings[1].spi_d = SPI2;
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_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
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_settings[1].spiDmaDev = DMA1;
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_settings[1].spiTxDmaChannel = DMA_CH5;
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_settings[1].spiRxDmaChannel = DMA_CH4;
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#if BOARD_NR_SPI >= 3
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_settings[2].spi_d = SPI3;
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_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
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_settings[2].spiDmaDev = DMA2;
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_settings[2].spiTxDmaChannel = DMA_CH2;
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_settings[2].spiRxDmaChannel = DMA_CH1;
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_settings[2].spi_d = SPI3;
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_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
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_settings[2].spiDmaDev = DMA2;
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_settings[2].spiTxDmaChannel = DMA_CH2;
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_settings[2].spiRxDmaChannel = DMA_CH1;
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#endif
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// added for DMA callbacks.
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@ -148,11 +148,11 @@ SPIClass::SPIClass(uint32 spi_num) {
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* Set up/tear down
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*/
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void SPIClass::updateSettings(void) {
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uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
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#ifdef SPI_DEBUG
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Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
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#endif
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spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
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uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
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#ifdef SPI_DEBUG
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Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
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#endif
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spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
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}
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void SPIClass::begin(void) {
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@ -167,9 +167,9 @@ void SPIClass::beginSlave(void) {
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spi_init(_currentSetting->spi_d);
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configure_gpios(_currentSetting->spi_d, 0);
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uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
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#ifdef SPI_DEBUG
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Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
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#endif
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#ifdef SPI_DEBUG
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Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
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#endif
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spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
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// added for DMA callbacks.
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_currentSetting->state = SPI_STATE_READY;
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@ -199,23 +199,23 @@ void SPIClass::end(void) {
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/* Roger Clark added 3 functions */
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void SPIClass::setClockDivider(uint32_t clockDivider)
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{
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#ifdef SPI_DEBUG
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Serial.print("Clock divider set to "); Serial.println(clockDivider);
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#endif
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_currentSetting->clockDivider = clockDivider;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
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_currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
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#ifdef SPI_DEBUG
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Serial.print("Clock divider set to "); Serial.println(clockDivider);
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#endif
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_currentSetting->clockDivider = clockDivider;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
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_currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
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}
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void SPIClass::setBitOrder(BitOrder bitOrder)
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{
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#ifdef SPI_DEBUG
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Serial.print("Bit order set to "); Serial.println(bitOrder);
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#endif
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_currentSetting->bitOrder = bitOrder;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
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if ( bitOrder==LSBFIRST ) cr1 |= SPI_CR1_LSBFIRST;
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_currentSetting->spi_d->regs->CR1 = cr1;
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#ifdef SPI_DEBUG
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Serial.print("Bit order set to "); Serial.println(bitOrder);
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#endif
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_currentSetting->bitOrder = bitOrder;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
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if ( bitOrder==LSBFIRST ) cr1 |= SPI_CR1_LSBFIRST;
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_currentSetting->spi_d->regs->CR1 = cr1;
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}
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/* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
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@ -224,11 +224,11 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
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*/
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void SPIClass::setDataSize(uint32 datasize)
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{
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_currentSetting->dataSize = datasize;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
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uint8 en = spi_is_enabled(_currentSetting->spi_d);
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spi_peripheral_disable(_currentSetting->spi_d);
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_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
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_currentSetting->dataSize = datasize;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
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uint8 en = spi_is_enabled(_currentSetting->spi_d);
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spi_peripheral_disable(_currentSetting->spi_d);
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_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
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}
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void SPIClass::setDataMode(uint8_t dataMode)
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@ -258,56 +258,56 @@ bit 0 - CPHA : Clock phase
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If someone finds this is not the case or sees a logic error with this let me know ;-)
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*/
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#ifdef SPI_DEBUG
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Serial.print("Data mode set to "); Serial.println(dataMode);
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#endif
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_currentSetting->dataMode = dataMode;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
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_currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
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#ifdef SPI_DEBUG
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Serial.print("Data mode set to "); Serial.println(dataMode);
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#endif
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_currentSetting->dataMode = dataMode;
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uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
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_currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
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}
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void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
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{
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#ifdef SPI_DEBUG
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Serial.println("SPIClass::beginTransaction");
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#endif
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setBitOrder(settings.bitOrder);
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setDataMode(settings.dataMode);
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setDataSize(settings.dataSize);
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setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
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begin();
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#ifdef SPI_DEBUG
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Serial.println("SPIClass::beginTransaction");
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#endif
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setBitOrder(settings.bitOrder);
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setDataMode(settings.dataMode);
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setDataSize(settings.dataSize);
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setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
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begin();
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}
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void SPIClass::beginTransactionSlave(SPISettings settings)
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{
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#ifdef SPI_DEBUG
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Serial.println(F("SPIClass::beginTransactionSlave"));
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#endif
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setBitOrder(settings.bitOrder);
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setDataMode(settings.dataMode);
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setDataSize(settings.dataSize);
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beginSlave();
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#ifdef SPI_DEBUG
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Serial.println(F("SPIClass::beginTransactionSlave"));
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#endif
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setBitOrder(settings.bitOrder);
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setDataMode(settings.dataMode);
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setDataSize(settings.dataSize);
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beginSlave();
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}
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void SPIClass::endTransaction(void)
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{
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#ifdef SPI_DEBUG
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Serial.println("SPIClass::endTransaction");
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#endif
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//digitalWrite(_SSPin,HIGH);
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#ifdef SPI_DEBUG
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Serial.println("SPIClass::endTransaction");
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#endif
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//digitalWrite(_SSPin,HIGH);
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#if false
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// code from SAM core
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uint8_t mode = interruptMode;
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if (mode > 0) {
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if (mode < 16) {
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if (mode & 1) PIOA->PIO_IER = interruptMask[0];
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if (mode & 2) PIOB->PIO_IER = interruptMask[1];
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if (mode & 4) PIOC->PIO_IER = interruptMask[2];
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if (mode & 8) PIOD->PIO_IER = interruptMask[3];
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} else {
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if (interruptSave) interrupts();
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}
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}
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uint8_t mode = interruptMode;
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if (mode > 0) {
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if (mode < 16) {
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if (mode & 1) PIOA->PIO_IER = interruptMask[0];
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if (mode & 2) PIOB->PIO_IER = interruptMask[1];
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if (mode & 4) PIOC->PIO_IER = interruptMask[2];
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if (mode & 8) PIOD->PIO_IER = interruptMask[3];
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} else {
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if (interruptSave) interrupts();
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}
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}
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#endif
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}
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@ -318,80 +318,80 @@ void SPIClass::endTransaction(void)
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uint16 SPIClass::read(void)
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{
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while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
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return (uint16)spi_rx_reg(_currentSetting->spi_d);
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while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
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return (uint16)spi_rx_reg(_currentSetting->spi_d);
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}
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void SPIClass::read(uint8 *buf, uint32 len)
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{
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if ( len == 0 ) return;
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spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
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spi_reg_map * regs = _currentSetting->spi_d->regs;
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// start sequence: write byte 0
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regs->DR = 0x00FF; // write the first byte
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// main loop
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while ( (--len) ) {
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while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag
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noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data
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regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
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while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register
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*buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
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interrupts(); // let systick do its job
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}
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// read remaining last byte
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while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the Rx register
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*buf++ = (uint8)(regs->DR); // read and store the received byte
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if ( len == 0 ) return;
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spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
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spi_reg_map * regs = _currentSetting->spi_d->regs;
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// start sequence: write byte 0
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regs->DR = 0x00FF; // write the first byte
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// main loop
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while ( (--len) ) {
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while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag
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noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data
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regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
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while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register
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*buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
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interrupts(); // let systick do its job
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}
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// read remaining last byte
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while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the Rx register
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*buf++ = (uint8)(regs->DR); // read and store the received byte
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}
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void SPIClass::write(uint16 data)
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{
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/* Added for 16bit data Victor Perez. Roger Clark
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* Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
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* by taking the Tx code from transfer(byte)
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* This almost doubles the speed of this function.
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*/
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spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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/* Added for 16bit data Victor Perez. Roger Clark
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* Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
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* by taking the Tx code from transfer(byte)
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* This almost doubles the speed of this function.
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*/
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spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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}
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void SPIClass::write(uint16 data, uint32 n)
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{
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// Added by stevstrong: Repeatedly send same data by the specified number of times
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spi_reg_map * regs = _currentSetting->spi_d->regs;
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while ( (n--)>0 ) {
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regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
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}
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while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning
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// Added by stevstrong: Repeatedly send same data by the specified number of times
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spi_reg_map * regs = _currentSetting->spi_d->regs;
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while ( (n--)>0 ) {
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regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
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while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
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}
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while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning
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}
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void SPIClass::write(void *data, uint32 length)
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{
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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}
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uint8 SPIClass::transfer(uint8 byte) const
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{
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_rx_reg(spi_d); // read any previous data
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spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_rx_reg(spi_d); // read any previous data
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spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
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while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
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return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
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}
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uint16_t SPIClass::transfer16(uint16_t wr_data) const
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{
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spi_dev * spi_d = _currentSetting->spi_d;
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spi_rx_reg(spi_d); // read any previous data
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spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
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while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
|
||||
spi_dev * spi_d = _currentSetting->spi_d;
|
||||
spi_rx_reg(spi_d); // read any previous data
|
||||
spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
|
||||
while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
|
||||
}
|
||||
|
||||
/* Roger Clark and Victor Perez, 2015
|
||||
|
|
@ -402,54 +402,54 @@ uint16_t SPIClass::transfer16(uint16_t wr_data) const
|
|||
*/
|
||||
void SPIClass::dmaTransferSet(void *transmitBuf, void *receiveBuf) {
|
||||
dma_init(_currentSetting->spiDmaDev);
|
||||
//spi_rx_dma_enable(_currentSetting->spi_d);
|
||||
//spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
//spi_rx_dma_enable(_currentSetting->spi_d);
|
||||
//spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT ));// receive buffer DMA
|
||||
if (!transmitBuf) {
|
||||
transmitBuf = &ff;
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
if (!transmitBuf) {
|
||||
transmitBuf = &ff;
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
|
||||
}
|
||||
else {
|
||||
}
|
||||
else {
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
transmitBuf, dma_bit_size, (DMA_MINC_MODE | DMA_FROM_MEM ));// Transmit buffer DMA
|
||||
}
|
||||
dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
|
||||
dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
|
||||
}
|
||||
dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
|
||||
dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
|
||||
}
|
||||
|
||||
uint8 SPIClass::dmaTransferRepeat(uint16 length) {
|
||||
if (length == 0) return 0;
|
||||
if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
|
||||
_currentSetting->state = SPI_STATE_TRANSFER;
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
||||
spi_rx_dma_enable(_currentSetting->spi_d);
|
||||
spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
if (length == 0) return 0;
|
||||
if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
|
||||
_currentSetting->state = SPI_STATE_TRANSFER;
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
||||
spi_rx_dma_enable(_currentSetting->spi_d);
|
||||
spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
if (_currentSetting->receiveCallback){
|
||||
return 0;
|
||||
}
|
||||
//uint32_t m = millis();
|
||||
uint8 b = 0;
|
||||
uint32_t m = millis();
|
||||
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
||||
//Avoid interrupts and just loop waiting for the flag to be set.
|
||||
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
||||
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
||||
//Avoid interrupts and just loop waiting for the flag to be set.
|
||||
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
||||
}
|
||||
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
spi_rx_dma_disable(_currentSetting->spi_d);
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
spi_rx_dma_disable(_currentSetting->spi_d);
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
return b;
|
||||
}
|
||||
|
||||
|
|
@ -461,8 +461,8 @@ uint8 SPIClass::dmaTransferRepeat(uint16 length) {
|
|||
*/
|
||||
|
||||
uint8 SPIClass::dmaTransfer(void *transmitBuf, void *receiveBuf, uint16 length) {
|
||||
dmaTransferSet(transmitBuf, receiveBuf);
|
||||
return dmaTransferRepeat(length);
|
||||
dmaTransferSet(transmitBuf, receiveBuf);
|
||||
return dmaTransferRepeat(length);
|
||||
}
|
||||
|
||||
/* Roger Clark and Victor Perez, 2015
|
||||
|
|
@ -482,29 +482,29 @@ void SPIClass::dmaSendSet(void * transmitBuf, bool minc) {
|
|||
}
|
||||
|
||||
uint8 SPIClass::dmaSendRepeat(uint16 length) {
|
||||
if (length == 0) return 0;
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
||||
_currentSetting->state = SPI_STATE_TRANSMIT;
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
||||
spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
if (_currentSetting->transmitCallback)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
uint32_t m = millis();
|
||||
uint8 b = 0;
|
||||
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
||||
//Avoid interrupts and just loop waiting for the flag to be set.
|
||||
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
||||
}
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
return b;
|
||||
if (length == 0) return 0;
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
||||
_currentSetting->state = SPI_STATE_TRANSMIT;
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
||||
spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
if (_currentSetting->transmitCallback)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
uint32_t m = millis();
|
||||
uint8 b = 0;
|
||||
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
||||
//Avoid interrupts and just loop waiting for the flag to be set.
|
||||
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
||||
}
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
return b;
|
||||
}
|
||||
|
||||
uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc) {
|
||||
|
|
@ -513,42 +513,42 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc) {
|
|||
}
|
||||
|
||||
uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
|
||||
uint8 b = 0;
|
||||
uint8 b = 0;
|
||||
|
||||
if (_currentSetting->state != SPI_STATE_READY)
|
||||
{
|
||||
if (_currentSetting->state != SPI_STATE_READY)
|
||||
{
|
||||
|
||||
uint32_t m = millis();
|
||||
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
|
||||
//delayMicroseconds(10);
|
||||
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
||||
}
|
||||
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
}
|
||||
uint32_t m = millis();
|
||||
while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
|
||||
//delayMicroseconds(10);
|
||||
if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
||||
}
|
||||
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
}
|
||||
|
||||
|
||||
if (length == 0) return 0;
|
||||
uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
|
||||
|
||||
if (length == 0) return 0;
|
||||
uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
|
||||
|
||||
|
||||
dma_init(_currentSetting->spiDmaDev);
|
||||
// TX
|
||||
dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
||||
spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
|
||||
dma_init(_currentSetting->spiDmaDev);
|
||||
// TX
|
||||
dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
||||
dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
||||
transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
|
||||
dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
||||
dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
||||
spi_tx_dma_enable(_currentSetting->spi_d);
|
||||
|
||||
_currentSetting->state = SPI_STATE_TRANSMIT;
|
||||
_currentSetting->state = SPI_STATE_TRANSMIT;
|
||||
|
||||
return b;
|
||||
return b;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -558,51 +558,51 @@ uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
|
|||
*/
|
||||
|
||||
void SPIClass::onReceive(void(*callback)(void)) {
|
||||
_currentSetting->receiveCallback = callback;
|
||||
if (callback){
|
||||
switch (_currentSetting->spi_d->clk_id) {
|
||||
case RCC_SPI1:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
|
||||
break;
|
||||
case RCC_SPI2:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
|
||||
break;
|
||||
#if BOARD_NR_SPI >= 3
|
||||
case RCC_SPI3:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ASSERT(0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
}
|
||||
_currentSetting->receiveCallback = callback;
|
||||
if (callback){
|
||||
switch (_currentSetting->spi_d->clk_id) {
|
||||
case RCC_SPI1:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
|
||||
break;
|
||||
case RCC_SPI2:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
|
||||
break;
|
||||
#if BOARD_NR_SPI >= 3
|
||||
case RCC_SPI3:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ASSERT(0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
}
|
||||
}
|
||||
|
||||
void SPIClass::onTransmit(void(*callback)(void)) {
|
||||
_currentSetting->transmitCallback = callback;
|
||||
if (callback){
|
||||
switch (_currentSetting->spi_d->clk_id) {
|
||||
case RCC_SPI1:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
|
||||
break;
|
||||
case RCC_SPI2:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
|
||||
break;
|
||||
#if BOARD_NR_SPI >= 3
|
||||
case RCC_SPI3:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ASSERT(0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
}
|
||||
_currentSetting->transmitCallback = callback;
|
||||
if (callback){
|
||||
switch (_currentSetting->spi_d->clk_id) {
|
||||
case RCC_SPI1:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
|
||||
break;
|
||||
case RCC_SPI2:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
|
||||
break;
|
||||
#if BOARD_NR_SPI >= 3
|
||||
case RCC_SPI3:
|
||||
dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ASSERT(0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -611,44 +611,44 @@ void SPIClass::onTransmit(void(*callback)(void)) {
|
|||
*/
|
||||
|
||||
void SPIClass::EventCallback() {
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
|
||||
switch (_currentSetting->state) {
|
||||
case SPI_STATE_TRANSFER:
|
||||
while (spi_is_rx_nonempty(_currentSetting->spi_d));
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
spi_rx_dma_disable(_currentSetting->spi_d);
|
||||
//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
||||
while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
|
||||
switch (_currentSetting->state) {
|
||||
case SPI_STATE_TRANSFER:
|
||||
while (spi_is_rx_nonempty(_currentSetting->spi_d));
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
spi_rx_dma_disable(_currentSetting->spi_d);
|
||||
//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
||||
|
||||
if (_currentSetting->receiveCallback)
|
||||
{
|
||||
_currentSetting->receiveCallback();
|
||||
}
|
||||
break;
|
||||
case SPI_STATE_TRANSMIT:
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
if (_currentSetting->transmitCallback)
|
||||
{
|
||||
_currentSetting->transmitCallback();
|
||||
}
|
||||
if (_currentSetting->receiveCallback)
|
||||
{
|
||||
_currentSetting->receiveCallback();
|
||||
}
|
||||
break;
|
||||
case SPI_STATE_TRANSMIT:
|
||||
_currentSetting->state = SPI_STATE_READY;
|
||||
spi_tx_dma_disable(_currentSetting->spi_d);
|
||||
//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
||||
if (_currentSetting->transmitCallback)
|
||||
{
|
||||
_currentSetting->transmitCallback();
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
// we shouldn't get here, so better to add an assert and fail.
|
||||
return;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
// we shouldn't get here, so better to add an assert and fail.
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void SPIClass::attachInterrupt(void) {
|
||||
// Should be enableInterrupt()
|
||||
// Should be enableInterrupt()
|
||||
}
|
||||
|
||||
void SPIClass::detachInterrupt(void) {
|
||||
// Should be disableInterrupt()
|
||||
// Should be disableInterrupt()
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -699,11 +699,11 @@ void SPIClass::_spi1EventCallback()
|
|||
}
|
||||
|
||||
void SPIClass::_spi2EventCallback() {
|
||||
reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
|
||||
reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
|
||||
}
|
||||
#if BOARD_NR_SPI >= 3
|
||||
void SPIClass::_spi3EventCallback() {
|
||||
reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
|
||||
reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
|
|
@ -711,57 +711,57 @@ void SPIClass::_spi3EventCallback() {
|
|||
*/
|
||||
|
||||
static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
|
||||
switch (dev->clk_id) {
|
||||
switch (dev->clk_id) {
|
||||
#if BOARD_NR_SPI >= 1
|
||||
case RCC_SPI1: return board_spi_pins;
|
||||
case RCC_SPI1: return board_spi_pins;
|
||||
#endif
|
||||
#if BOARD_NR_SPI >= 2
|
||||
case RCC_SPI2: return board_spi_pins + 1;
|
||||
case RCC_SPI2: return board_spi_pins + 1;
|
||||
#endif
|
||||
#if BOARD_NR_SPI >= 3
|
||||
case RCC_SPI3: return board_spi_pins + 2;
|
||||
case RCC_SPI3: return board_spi_pins + 2;
|
||||
#endif
|
||||
default: return NULL;
|
||||
}
|
||||
default: return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static void disable_pwm(const stm32_pin_info *i) {
|
||||
if (i->timer_device) {
|
||||
timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
|
||||
}
|
||||
if (i->timer_device) {
|
||||
timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
|
||||
}
|
||||
}
|
||||
|
||||
static void configure_gpios(spi_dev *dev, bool as_master) {
|
||||
const spi_pins *pins = dev_to_spi_pins(dev);
|
||||
const spi_pins *pins = dev_to_spi_pins(dev);
|
||||
|
||||
if (!pins) {
|
||||
return;
|
||||
}
|
||||
if (!pins) {
|
||||
return;
|
||||
}
|
||||
|
||||
const stm32_pin_info *nssi = &PIN_MAP[pins->nss];
|
||||
const stm32_pin_info *scki = &PIN_MAP[pins->sck];
|
||||
const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
|
||||
const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
|
||||
const stm32_pin_info *nssi = &PIN_MAP[pins->nss];
|
||||
const stm32_pin_info *scki = &PIN_MAP[pins->sck];
|
||||
const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
|
||||
const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
|
||||
|
||||
disable_pwm(nssi);
|
||||
disable_pwm(scki);
|
||||
disable_pwm(misoi);
|
||||
disable_pwm(mosii);
|
||||
disable_pwm(nssi);
|
||||
disable_pwm(scki);
|
||||
disable_pwm(misoi);
|
||||
disable_pwm(mosii);
|
||||
|
||||
spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
|
||||
scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
|
||||
mosii->gpio_bit);
|
||||
spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
|
||||
scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
|
||||
mosii->gpio_bit);
|
||||
}
|
||||
|
||||
static const spi_baud_rate baud_rates[8] __FLASH__ = {
|
||||
SPI_BAUD_PCLK_DIV_2,
|
||||
SPI_BAUD_PCLK_DIV_4,
|
||||
SPI_BAUD_PCLK_DIV_8,
|
||||
SPI_BAUD_PCLK_DIV_16,
|
||||
SPI_BAUD_PCLK_DIV_32,
|
||||
SPI_BAUD_PCLK_DIV_64,
|
||||
SPI_BAUD_PCLK_DIV_128,
|
||||
SPI_BAUD_PCLK_DIV_256,
|
||||
SPI_BAUD_PCLK_DIV_2,
|
||||
SPI_BAUD_PCLK_DIV_4,
|
||||
SPI_BAUD_PCLK_DIV_8,
|
||||
SPI_BAUD_PCLK_DIV_16,
|
||||
SPI_BAUD_PCLK_DIV_32,
|
||||
SPI_BAUD_PCLK_DIV_64,
|
||||
SPI_BAUD_PCLK_DIV_128,
|
||||
SPI_BAUD_PCLK_DIV_256,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -769,22 +769,22 @@ static const spi_baud_rate baud_rates[8] __FLASH__ = {
|
|||
* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
|
||||
*/
|
||||
static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
|
||||
uint32_t clock = 0, i;
|
||||
#ifdef SPI_DEBUG
|
||||
Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")");
|
||||
#endif
|
||||
switch (rcc_dev_clk(dev->clk_id))
|
||||
{
|
||||
case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
|
||||
case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
|
||||
}
|
||||
clock /= 2;
|
||||
i = 0;
|
||||
while (i < 7 && freq < clock) {
|
||||
clock /= 2;
|
||||
i++;
|
||||
}
|
||||
return baud_rates[i];
|
||||
uint32_t clock = 0, i;
|
||||
#ifdef SPI_DEBUG
|
||||
Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")");
|
||||
#endif
|
||||
switch (rcc_dev_clk(dev->clk_id))
|
||||
{
|
||||
case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
|
||||
case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
|
||||
}
|
||||
clock /= 2;
|
||||
i = 0;
|
||||
while (i < 7 && freq < clock) {
|
||||
clock /= 2;
|
||||
i++;
|
||||
}
|
||||
return baud_rates[i];
|
||||
}
|
||||
|
||||
SPIClass SPI(1);
|
||||
|
|
|
|||
Loading…
Reference in New Issue