diff --git a/STM32F1/cores/maple/libmaple/adc_f1.c b/STM32F1/cores/maple/libmaple/adc_f1.c index 8cb4b4a..a8ea30b 100644 --- a/STM32F1/cores/maple/libmaple/adc_f1.c +++ b/STM32F1/cores/maple/libmaple/adc_f1.c @@ -72,7 +72,7 @@ adc_dev *ADC3 = &adc3; adc irq routine. Added by bubulindo. */ -void __irq_adc() { +__weak void __irq_adc() { //get status uint32 adc_sr = ADC1->regs->SR; //End Of Conversion @@ -107,7 +107,7 @@ void __irq_adc() { added by bubulindo */ #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -void __irq_adc3() { +__weak void __irq_adc3() { //get status uint32 adc_sr = ADC3->regs->SR; //End Of Conversion diff --git a/STM32F1/cores/maple/libmaple/dma_f1.c b/STM32F1/cores/maple/libmaple/dma_f1.c index 33dc0ef..fb5b03c 100644 --- a/STM32F1/cores/maple/libmaple/dma_f1.c +++ b/STM32F1/cores/maple/libmaple/dma_f1.c @@ -360,48 +360,48 @@ void dma_setup_transfer(dma_dev *dev, * IRQ handlers */ -void __irq_dma1_channel1(void) { +__weak void __irq_dma1_channel1(void) { dma_irq_handler(DMA1, DMA_CH1); } -void __irq_dma1_channel2(void) { +__weak void __irq_dma1_channel2(void) { dma_irq_handler(DMA1, DMA_CH2); } -void __irq_dma1_channel3(void) { +__weak void __irq_dma1_channel3(void) { dma_irq_handler(DMA1, DMA_CH3); } -void __irq_dma1_channel4(void) { +__weak void __irq_dma1_channel4(void) { dma_irq_handler(DMA1, DMA_CH4); } -void __irq_dma1_channel5(void) { +__weak void __irq_dma1_channel5(void) { dma_irq_handler(DMA1, DMA_CH5); } -void __irq_dma1_channel6(void) { +__weak void __irq_dma1_channel6(void) { dma_irq_handler(DMA1, DMA_CH6); } -void __irq_dma1_channel7(void) { +__weak void __irq_dma1_channel7(void) { dma_irq_handler(DMA1, DMA_CH7); } #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -void __irq_dma2_channel1(void) { +__weak void __irq_dma2_channel1(void) { dma_irq_handler(DMA2, DMA_CH1); } -void __irq_dma2_channel2(void) { +__weak void __irq_dma2_channel2(void) { dma_irq_handler(DMA2, DMA_CH2); } -void __irq_dma2_channel3(void) { +__weak void __irq_dma2_channel3(void) { dma_irq_handler(DMA2, DMA_CH3); } -void __irq_dma2_channel4_5(void) { +__weak void __irq_dma2_channel4_5(void) { if ((DMA2_BASE->CCR4 & DMA_CCR_EN) && (DMA2_BASE->ISR & DMA_ISR_GIF4)) { dma_irq_handler(DMA2, DMA_CH4); } diff --git a/STM32F1/cores/maple/libmaple/exc.S b/STM32F1/cores/maple/libmaple/exc.S index 7631e48..24153fc 100644 --- a/STM32F1/cores/maple/libmaple/exc.S +++ b/STM32F1/cores/maple/libmaple/exc.S @@ -41,7 +41,6 @@ # SP--> r0 .text -.globl __exc_hardfault .globl __exc_nmi .globl __exc_hardfault .globl __exc_memmanage diff --git a/STM32F1/cores/maple/libmaple/exti.c b/STM32F1/cores/maple/libmaple/exti.c index c8836a7..982ba06 100644 --- a/STM32F1/cores/maple/libmaple/exti.c +++ b/STM32F1/cores/maple/libmaple/exti.c @@ -212,31 +212,31 @@ void exti_do_select(__IO uint32 *exti_cr, exti_num num, exti_cfg port) { * Interrupt handlers */ -void __irq_exti0(void) { +__weak void __irq_exti0(void) { dispatch_single_exti(EXTI0); } -void __irq_exti1(void) { +__weak void __irq_exti1(void) { dispatch_single_exti(EXTI1); } -void __irq_exti2(void) { +__weak void __irq_exti2(void) { dispatch_single_exti(EXTI2); } -void __irq_exti3(void) { +__weak void __irq_exti3(void) { dispatch_single_exti(EXTI3); } -void __irq_exti4(void) { +__weak void __irq_exti4(void) { dispatch_single_exti(EXTI4); } -void __irq_exti9_5(void) { +__weak void __irq_exti9_5(void) { dispatch_extis(5, 9); } -void __irq_exti15_10(void) { +__weak void __irq_exti15_10(void) { dispatch_extis(10, 15); } diff --git a/STM32F1/cores/maple/libmaple/i2c_f1.c b/STM32F1/cores/maple/libmaple/i2c_f1.c index 8439793..3b1cc36 100644 --- a/STM32F1/cores/maple/libmaple/i2c_f1.c +++ b/STM32F1/cores/maple/libmaple/i2c_f1.c @@ -76,19 +76,19 @@ void i2c_master_release_bus(const i2c_dev *dev) { * IRQ handlers */ -void __irq_i2c1_ev(void) { +__weak void __irq_i2c1_ev(void) { _i2c_irq_handler(I2C1); } -void __irq_i2c2_ev(void) { +__weak void __irq_i2c2_ev(void) { _i2c_irq_handler(I2C2); } -void __irq_i2c1_er(void) { +__weak void __irq_i2c1_er(void) { _i2c_irq_error_handler(I2C1); } -void __irq_i2c2_er(void) { +__weak void __irq_i2c2_er(void) { _i2c_irq_error_handler(I2C2); } diff --git a/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S b/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S index 8c1a44f..7a9b4aa 100644 --- a/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S +++ b/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S @@ -76,9 +76,9 @@ __default_handler: .weak __exc_pendsv .globl __exc_pendsv .set __exc_pendsv, __default_handler - .weak __exc_systick - .globl __exc_systick - .set __exc_systick, __default_handler +// .weak __exc_systick // __exc_systick() defined in STM32F1/cores/maple/libmaple/systick.c +// .globl __exc_systick +// .set __exc_systick, __default_handler .weak __irq_wwdg .globl __irq_wwdg .set __irq_wwdg, __default_handler @@ -97,110 +97,110 @@ __default_handler: .weak __irq_rcc .globl __irq_rcc .set __irq_rcc, __default_handler - .weak __irq_exti0 - .globl __irq_exti0 - .set __irq_exti0, __default_handler - .weak __irq_exti1 - .globl __irq_exti1 - .set __irq_exti1, __default_handler - .weak __irq_exti2 - .globl __irq_exti2 - .set __irq_exti2, __default_handler - .weak __irq_exti3 - .globl __irq_exti3 - .set __irq_exti3, __default_handler - .weak __irq_exti4 - .globl __irq_exti4 - .set __irq_exti4, __default_handler - .weak __irq_dma1_channel1 - .globl __irq_dma1_channel1 - .set __irq_dma1_channel1, __default_handler - .weak __irq_dma1_channel2 - .globl __irq_dma1_channel2 - .set __irq_dma1_channel2, __default_handler - .weak __irq_dma1_channel3 - .globl __irq_dma1_channel3 - .set __irq_dma1_channel3, __default_handler - .weak __irq_dma1_channel4 - .globl __irq_dma1_channel4 - .set __irq_dma1_channel4, __default_handler - .weak __irq_dma1_channel5 - .globl __irq_dma1_channel5 - .set __irq_dma1_channel5, __default_handler - .weak __irq_dma1_channel6 - .globl __irq_dma1_channel6 - .set __irq_dma1_channel6, __default_handler - .weak __irq_dma1_channel7 - .globl __irq_dma1_channel7 - .set __irq_dma1_channel7, __default_handler - .weak __irq_adc - .globl __irq_adc - .set __irq_adc, __default_handler +// .weak __irq_exti0 // __irq_exti0() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti0 +// .set __irq_exti0, __default_handler +// .weak __irq_exti1 // __irq_exti1() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti1 +// .set __irq_exti1, __default_handler +// .weak __irq_exti2 // __irq_exti2() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti2 +// .set __irq_exti2, __default_handler +// .weak __irq_exti3 // __irq_exti3() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti3 +// .set __irq_exti3, __default_handler +// .weak __irq_exti4 // __irq_exti4() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti4 +// .set __irq_exti4, __default_handler +// .weak __irq_dma1_channel1 // __irq_dma1_channel1() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel1 +// .set __irq_dma1_channel1, __default_handler +// .weak __irq_dma1_channel2 // __irq_dma1_channel2() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel2 +// .set __irq_dma1_channel2, __default_handler +// .weak __irq_dma1_channel3 // __irq_dma1_channel3() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel3 +// .set __irq_dma1_channel3, __default_handler +// .weak __irq_dma1_channel4 // __irq_dma1_channel4() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel4 +// .set __irq_dma1_channel4, __default_handler +// .weak __irq_dma1_channel5 // __irq_dma1_channel5() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel5 +// .set __irq_dma1_channel5, __default_handler +// .weak __irq_dma1_channel6 // __irq_dma1_channel6() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel6 +// .set __irq_dma1_channel6, __default_handler +// .weak __irq_dma1_channel7 // __irq_dma1_channel7() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma1_channel7 +// .set __irq_dma1_channel7, __default_handler +// .weak __irq_adc // __irq_adc() defined in STM32F1/cores/maple/libmaple/adc_f1.c +// .globl __irq_adc +// .set __irq_adc, __default_handler .weak __irq_usb_hp_can_tx .globl __irq_usb_hp_can_tx .set __irq_usb_hp_can_tx, __default_handler - .weak __irq_usb_lp_can_rx0 - .globl __irq_usb_lp_can_rx0 - .set __irq_usb_lp_can_rx0, __default_handler +// .weak __irq_usb_lp_can_rx0 // __irq_usb_lp_can_rx0() defined in STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c +// .globl __irq_usb_lp_can_rx0 +// .set __irq_usb_lp_can_rx0, __default_handler .weak __irq_can_rx1 .globl __irq_can_rx1 .set __irq_can_rx1, __default_handler .weak __irq_can_sce .globl __irq_can_sce .set __irq_can_sce, __default_handler - .weak __irq_exti9_5 - .globl __irq_exti9_5 - .set __irq_exti9_5, __default_handler - .weak __irq_tim1_brk - .globl __irq_tim1_brk - .set __irq_tim1_brk, __default_handler - .weak __irq_tim1_up - .globl __irq_tim1_up - .set __irq_tim1_up, __default_handler - .weak __irq_tim1_trg_com - .globl __irq_tim1_trg_com - .set __irq_tim1_trg_com, __default_handler - .weak __irq_tim1_cc - .globl __irq_tim1_cc - .set __irq_tim1_cc, __default_handler - - .weakref __irq_tim2, __default_handler - .globl __irq_tim2 - .weakref __irq_tim3, __default_handler - .globl __irq_tim3 - .weakref __irq_tim4, __default_handler - .globl __irq_tim4 - - .weak __irq_i2c1_ev - .globl __irq_i2c1_ev - .set __irq_i2c1_ev, __default_handler - .weak __irq_i2c1_er - .globl __irq_i2c1_er - .set __irq_i2c1_er, __default_handler - .weak __irq_i2c2_ev - .globl __irq_i2c2_ev - .set __irq_i2c2_ev, __default_handler - .weak __irq_i2c2_er - .globl __irq_i2c2_er - .set __irq_i2c2_er, __default_handler +// .weak __irq_exti9_5 // __irq_exti9_5() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti9_5 +// .set __irq_exti9_5, __default_handler +// .weak __irq_tim1_brk // __irq_tim1_brk() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim1_brk +// .set __irq_tim1_brk, __default_handler +// .weak __irq_tim1_up // __irq_tim1_up() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim1_up +// .set __irq_tim1_up, __default_handler +// .weak __irq_tim1_trg_com // __irq_tim1_trg_com() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim1_trg_com +// .set __irq_tim1_trg_com, __default_handler +// .weak __irq_tim1_cc // __irq_tim1_cc() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim1_cc +// .set __irq_tim1_cc, __default_handler +// +// .weakref __irq_tim2, __default_handler // __irq_tim2() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim2 +// .weakref __irq_tim3, __default_handler // __irq_tim3() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim3 +// .weakref __irq_tim4, __default_handler // __irq_tim4() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim4 +// +// .weak __irq_i2c1_ev // __irq_i2c1_ev() defined in STM32F1/cores/maple/libmaple/i2c_f1.c +// .globl __irq_i2c1_ev +// .set __irq_i2c1_ev, __default_handler +// .weak __irq_i2c1_er // __irq_i2c1_er() defined in STM32F1/cores/maple/libmaple/i2c_f1.c +// .globl __irq_i2c1_er +// .set __irq_i2c1_er, __default_handler +// .weak __irq_i2c2_ev // __irq_i2c2_ev() defined in STM32F1/cores/maple/libmaple/i2c_f1.c +// .globl __irq_i2c2_ev +// .set __irq_i2c2_ev, __default_handler +// .weak __irq_i2c2_er // __irq_i2c2_er() defined in STM32F1/cores/maple/libmaple/i2c_f1.c +// .globl __irq_i2c2_er +// .set __irq_i2c2_er, __default_handler .weak __irq_spi1 .globl __irq_spi1 .set __irq_spi1, __default_handler .weak __irq_spi2 .globl __irq_spi2 .set __irq_spi2, __default_handler - .weak __irq_usart1 - .globl __irq_usart1 - .set __irq_usart1, __default_handler - .weak __irq_usart2 - .globl __irq_usart2 - .set __irq_usart2, __default_handler - .weak __irq_usart3 - .globl __irq_usart3 - .set __irq_usart3, __default_handler - .weak __irq_exti15_10 - .globl __irq_exti15_10 - .set __irq_exti15_10, __default_handler +// .weak __irq_usart1 // __irq_usart1() defined in STM32F1/cores/maple/libmaple/usart_f1.c +// .globl __irq_usart1 +// .set __irq_usart1, __default_handler +// .weak __irq_usart2 // __irq_usart2() defined in STM32F1/cores/maple/libmaple/usart_f1.c +// .globl __irq_usart2 +// .set __irq_usart2, __default_handler +// .weak __irq_usart3 // __irq_usart3() defined in STM32F1/cores/maple/libmaple/usart_f1.c +// .globl __irq_usart3 +// .set __irq_usart3, __default_handler +// .weak __irq_exti15_10 // __irq_exti15_10() defined in STM32F1/cores/maple/libmaple/exti.c +// .globl __irq_exti15_10 +// .set __irq_exti15_10, __default_handler .weak __irq_rtcalarm .globl __irq_rtcalarm .set __irq_rtcalarm, __default_handler @@ -208,55 +208,55 @@ __default_handler: .globl __irq_usbwakeup .set __irq_usbwakeup, __default_handler #if defined (STM32_HIGH_DENSITY) - .weak __irq_tim8_brk - .globl __irq_tim8_brk - .set __irq_tim8_brk, __default_handler - .weak __irq_tim8_up - .globl __irq_tim8_up - .set __irq_tim8_up, __default_handler - .weak __irq_tim8_trg_com - .globl __irq_tim8_trg_com - .set __irq_tim8_trg_com, __default_handler - .weak __irq_tim8_cc - .globl __irq_tim8_cc - .set __irq_tim8_cc, __default_handler - .weak __irq_adc3 - .globl __irq_adc3 - .set __irq_adc3, __default_handler +// .weak __irq_tim8_brk // __irq_tim8_brk() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim8_brk +// .set __irq_tim8_brk, __default_handler +// .weak __irq_tim8_up // __irq_tim8_up() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim8_up +// .set __irq_tim8_up, __default_handler +// .weak __irq_tim8_trg_com // __irq_tim8_trg_com() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim8_trg_com +// .set __irq_tim8_trg_com, __default_handler +// .weak __irq_tim8_cc // __irq_tim8_cc() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim8_cc +// .set __irq_tim8_cc, __default_handler +// .weak __irq_adc3 // __irq_adc3() defined in STM32F1/cores/maple/libmaple/adc_f1.c +// .globl __irq_adc3 +// .set __irq_adc3, __default_handler .weak __irq_fsmc .globl __irq_fsmc .set __irq_fsmc, __default_handler .weak __irq_sdio .globl __irq_sdio .set __irq_sdio, __default_handler - .weak __irq_tim5 - .globl __irq_tim5 - .set __irq_tim5, __default_handler +// .weak __irq_tim5 // __irq_tim5() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim5 +// .set __irq_tim5, __default_handler .weak __irq_spi3 .globl __irq_spi3 .set __irq_spi3, __default_handler - .weak __irq_uart4 - .globl __irq_uart4 - .set __irq_uart4, __default_handler - .weak __irq_uart5 - .globl __irq_uart5 - .set __irq_uart5, __default_handler - .weak __irq_tim6 - .globl __irq_tim6 - .set __irq_tim6, __default_handler - .weak __irq_tim7 - .globl __irq_tim7 - .set __irq_tim7, __default_handler - .weak __irq_dma2_channel1 - .globl __irq_dma2_channel1 - .set __irq_dma2_channel1, __default_handler - .weak __irq_dma2_channel2 - .globl __irq_dma2_channel2 - .set __irq_dma2_channel2, __default_handler - .weak __irq_dma2_channel3 - .globl __irq_dma2_channel3 - .set __irq_dma2_channel3, __default_handler - .weak __irq_dma2_channel4_5 - .globl __irq_dma2_channel4_5 - .set __irq_dma2_channel4_5, __default_handler +// .weak __irq_uart4 // __irq_uart4() defined in STM32F1/cores/maple/libmaple/usart_f1.c +// .globl __irq_uart4 +// .set __irq_uart4, __default_handler +// .weak __irq_uart5 // __irq_uart5() defined in STM32F1/cores/maple/libmaple/usart_f1.c +// .globl __irq_uart5 +// .set __irq_uart5, __default_handler +// .weak __irq_tim6 // __irq_tim6() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim6 +// .set __irq_tim6, __default_handler +// .weak __irq_tim7 // __irq_tim7() defined in STM32F1/cores/maple/libmaple/timer.c +// .globl __irq_tim7 +// .set __irq_tim7, __default_handler +// .weak __irq_dma2_channel1 // __irq_dma2_channel1() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma2_channel1 +// .set __irq_dma2_channel1, __default_handler +// .weak __irq_dma2_channel2 // __irq_dma2_channel2() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma2_channel2 +// .set __irq_dma2_channel2, __default_handler +// .weak __irq_dma2_channel3 // __irq_dma2_channel3() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma2_channel3 +// .set __irq_dma2_channel3, __default_handler +// .weak __irq_dma2_channel4_5 // __irq_dma2_channel4_5() defined in STM32F1/cores/maple/libmaple/dma_f1.c +// .globl __irq_dma2_channel4_5 +// .set __irq_dma2_channel4_5, __default_handler #endif /* STM32_HIGH_DENSITY */ \ No newline at end of file diff --git a/STM32F1/cores/maple/libmaple/systick.c b/STM32F1/cores/maple/libmaple/systick.c index 7568abe..1ac92f1 100644 --- a/STM32F1/cores/maple/libmaple/systick.c +++ b/STM32F1/cores/maple/libmaple/systick.c @@ -80,7 +80,7 @@ void systick_attach_callback(void (*callback)(void)) { * SysTick ISR */ -void __exc_systick(void) { +__weak void __exc_systick(void) { systick_uptime_millis++; if (systick_user_callback) { systick_user_callback(); diff --git a/STM32F1/cores/maple/libmaple/timer.c b/STM32F1/cores/maple/libmaple/timer.c index fa50c20..5f12430 100644 --- a/STM32F1/cores/maple/libmaple/timer.c +++ b/STM32F1/cores/maple/libmaple/timer.c @@ -478,78 +478,78 @@ static void enable_bas_gen_irq(timer_dev *dev) { * file. */ -void __irq_tim1_brk(void) { +__weak void __irq_tim1_brk(void) { dispatch_adv_brk(TIMER1); #if STM32_HAVE_TIMER(9) dispatch_tim_9_12(TIMER9); #endif } -void __irq_tim1_up(void) { +__weak void __irq_tim1_up(void) { dispatch_adv_up(TIMER1); #if STM32_HAVE_TIMER(10) dispatch_tim_10_11_13_14(TIMER10); #endif } -void __irq_tim1_trg_com(void) { +__weak void __irq_tim1_trg_com(void) { dispatch_adv_trg_com(TIMER1); #if STM32_HAVE_TIMER(11) dispatch_tim_10_11_13_14(TIMER11); #endif } -void __irq_tim1_cc(void) { +__weak void __irq_tim1_cc(void) { dispatch_adv_cc(TIMER1); } -void __irq_tim2(void) { +__weak void __irq_tim2(void) { dispatch_general(TIMER2); } -void __irq_tim3(void) { +__weak void __irq_tim3(void) { dispatch_general(TIMER3); } -void __irq_tim4(void) { +__weak void __irq_tim4(void) { dispatch_general(TIMER4); } #if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) -void __irq_tim5(void) { +__weak void __irq_tim5(void) { dispatch_general(TIMER5); } -void __irq_tim6(void) { +__weak void __irq_tim6(void) { dispatch_basic(TIMER6); } -void __irq_tim7(void) { +__weak void __irq_tim7(void) { dispatch_basic(TIMER7); } -void __irq_tim8_brk(void) { +__weak void __irq_tim8_brk(void) { dispatch_adv_brk(TIMER8); #if STM32_HAVE_TIMER(12) dispatch_tim_9_12(TIMER12); #endif } -void __irq_tim8_up(void) { +__weak void __irq_tim8_up(void) { dispatch_adv_up(TIMER8); #if STM32_HAVE_TIMER(13) dispatch_tim_10_11_13_14(TIMER13); #endif } -void __irq_tim8_trg_com(void) { +__weak void __irq_tim8_trg_com(void) { dispatch_adv_trg_com(TIMER8); #if STM32_HAVE_TIMER(14) dispatch_tim_10_11_13_14(TIMER14); #endif } -void __irq_tim8_cc(void) { +__weak void __irq_tim8_cc(void) { dispatch_adv_cc(TIMER8); } #endif /* defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY) */ \ No newline at end of file diff --git a/STM32F1/cores/maple/libmaple/usart_f1.c b/STM32F1/cores/maple/libmaple/usart_f1.c index 2b590fc..30ce000 100644 --- a/STM32F1/cores/maple/libmaple/usart_f1.c +++ b/STM32F1/cores/maple/libmaple/usart_f1.c @@ -200,24 +200,24 @@ void usart_foreach(void (*fn)(usart_dev*)) { * Interrupt handlers. */ -void __irq_usart1(void) { +__weak void __irq_usart1(void) { usart_irq(&usart1_rb, &usart1_wb, USART1_BASE); } -void __irq_usart2(void) { +__weak void __irq_usart2(void) { usart_irq(&usart2_rb, &usart2_wb, USART2_BASE); } -void __irq_usart3(void) { +__weak void __irq_usart3(void) { usart_irq(&usart3_rb, &usart3_wb, USART3_BASE); } #ifdef STM32_HIGH_DENSITY -void __irq_uart4(void) { +__weak void __irq_uart4(void) { usart_irq(&uart4_rb, &uart4_wb, UART4_BASE); } -void __irq_uart5(void) { +__weak void __irq_uart5(void) { usart_irq(&uart5_rb, &uart5_wb, UART5_BASE); } #endif diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c index 0feb745..4f6c823 100644 --- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c +++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c @@ -190,7 +190,7 @@ static void usb_resume(RESUME_STATE eResumeSetVal) { } #define SUSPEND_ENABLED 1 -void __irq_usb_lp_can_rx0(void) { +__weak void __irq_usb_lp_can_rx0(void) { uint16 istr = USB_BASE->ISTR; /* Use USB_ISR_MSK to only include code for bits we care about. */