Merge branch 'me21-enable-hsi'
This commit is contained in:
commit
cd3cab3a79
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -46,6 +46,7 @@
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// Additionally the GD32 has a 4 USB PLL divider settings, rather than the 2 settings in the STM32, which allow it to operate on frequencies of 48,72,96 and 120Mhz and still have USB functioning
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==120000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_10
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#elif F_CPU==96000000
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@ -53,14 +54,20 @@
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#elif F_CPU==72000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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@ -120,12 +120,12 @@ static void setup_clocks(void) {
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// Clear clock readiness interrupt flags and turn off clock
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// readiness interrupts.
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RCC_BASE->CIR = 0x00000000;
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#if !USE_HSI_CLOCK
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// Enable HSE, and wait until it's ready.
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rcc_turn_on_clk(RCC_CLK_HSE);
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while (!rcc_is_clk_ready(RCC_CLK_HSE))
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;
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#endif
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// Configure AHBx, APBx, etc. prescalers and the main PLL.
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wirish::priv::board_setup_clock_prescalers();
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rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
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@ -48,6 +48,7 @@
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// works for F103 performance line MCUs, which is all that LeafLabs
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// currently officially supports).
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#ifndef BOARD_RCC_PLLMUL
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#if !USE_HSI_CLOCK
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#if F_CPU==128000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#elif F_CPU==72000000
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@ -57,13 +58,20 @@
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#elif F_CPU==16000000
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_2
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#endif
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#else
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#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
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#endif
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#endif
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namespace wirish {
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namespace priv {
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static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
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#if !USE_HSI_CLOCK
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
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#else
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__weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
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#endif
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__weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
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__weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
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||||
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||||
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