diff --git a/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S b/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S index 2d6052c..8c1a44f 100644 --- a/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S +++ b/STM32F1/cores/maple/libmaple/stm32f1/performance/isrs.S @@ -37,153 +37,226 @@ __default_handler: b . - .weakref __exc_nmi, __default_handler + .weak __exc_nmi .globl __exc_nmi - .weakref __exc_hardfault, __default_handler + .set __exc_nmi, __default_handler + .weak __exc_hardfault .globl __exc_hardfault - .weakref __exc_memmanage, __default_handler + .set __exc_hardfault, __default_handler + .weak __exc_memmanage .globl __exc_memmanage - .weakref __exc_busfault, __default_handler + .set __exc_memmanage, __default_handler + .weak __exc_busfault .globl __exc_busfault - .weakref __exc_usagefault, __default_handler + .set __exc_busfault, __default_handler + .weak __exc_usagefault .globl __exc_usagefault - .weakref __stm32reservedexception7, __default_handler + .set __exc_usagefault, __default_handler + .weak __stm32reservedexception7 .globl __stm32reservedexception7 - .weakref __stm32reservedexception8, __default_handler + .set __stm32reservedexception7, __default_handler + .weak __stm32reservedexception8 .globl __stm32reservedexception8 - .weakref __stm32reservedexception9, __default_handler + .set __stm32reservedexception8, __default_handler + .weak __stm32reservedexception9 .globl __stm32reservedexception9 - .weakref __stm32reservedexception10, __default_handler + .set __stm32reservedexception9, __default_handler + .weak __stm32reservedexception10 .globl __stm32reservedexception10 - .weakref __exc_svc, __default_handler + .set __stm32reservedexception10, __default_handler + .weak __exc_svc .globl __exc_svc - .weakref __exc_debug_monitor, __default_handler + .set __exc_svc, __default_handler + .weak __exc_debug_monitor .globl __exc_debug_monitor - .weakref __stm32reservedexception13, __default_handler + .set __exc_debug_monitor, __default_handler + .weak __stm32reservedexception13 .globl __stm32reservedexception13 - .weakref __exc_pendsv, __default_handler + .set __stm32reservedexception13, __default_handler + .weak __exc_pendsv .globl __exc_pendsv - .weakref __exc_systick, __default_handler + .set __exc_pendsv, __default_handler + .weak __exc_systick .globl __exc_systick - .weakref __irq_wwdg, __default_handler + .set __exc_systick, __default_handler + .weak __irq_wwdg .globl __irq_wwdg - .weakref __irq_pvd, __default_handler + .set __irq_wwdg, __default_handler + .weak __irq_pvd .globl __irq_pvd - .weakref __irq_tamper, __default_handler + .set __irq_pvd, __default_handler + .weak __irq_tamper .globl __irq_tamper - .weakref __irq_rtc, __default_handler + .set __irq_tamper, __default_handler + .weak __irq_rtc .globl __irq_rtc - .weakref __irq_flash, __default_handler + .set __irq_rtc, __default_handler + .weak __irq_flash .globl __irq_flash - .weakref __irq_rcc, __default_handler + .set __irq_flash, __default_handler + .weak __irq_rcc .globl __irq_rcc - .weakref __irq_exti0, __default_handler + .set __irq_rcc, __default_handler + .weak __irq_exti0 .globl __irq_exti0 - .weakref __irq_exti1, __default_handler + .set __irq_exti0, __default_handler + .weak __irq_exti1 .globl __irq_exti1 - .weakref __irq_exti2, __default_handler + .set __irq_exti1, __default_handler + .weak __irq_exti2 .globl __irq_exti2 - .weakref __irq_exti3, __default_handler + .set __irq_exti2, __default_handler + .weak __irq_exti3 .globl __irq_exti3 - .weakref __irq_exti4, __default_handler + .set __irq_exti3, __default_handler + .weak __irq_exti4 .globl __irq_exti4 - .weakref __irq_dma1_channel1, __default_handler + .set __irq_exti4, __default_handler + .weak __irq_dma1_channel1 .globl __irq_dma1_channel1 - .weakref __irq_dma1_channel2, __default_handler + .set __irq_dma1_channel1, __default_handler + .weak __irq_dma1_channel2 .globl __irq_dma1_channel2 - .weakref __irq_dma1_channel3, __default_handler + .set __irq_dma1_channel2, __default_handler + .weak __irq_dma1_channel3 .globl __irq_dma1_channel3 - .weakref __irq_dma1_channel4, __default_handler + .set __irq_dma1_channel3, __default_handler + .weak __irq_dma1_channel4 .globl __irq_dma1_channel4 - .weakref __irq_dma1_channel5, __default_handler + .set __irq_dma1_channel4, __default_handler + .weak __irq_dma1_channel5 .globl __irq_dma1_channel5 - .weakref __irq_dma1_channel6, __default_handler + .set __irq_dma1_channel5, __default_handler + .weak __irq_dma1_channel6 .globl __irq_dma1_channel6 - .weakref __irq_dma1_channel7, __default_handler + .set __irq_dma1_channel6, __default_handler + .weak __irq_dma1_channel7 .globl __irq_dma1_channel7 - .weakref __irq_adc, __default_handler + .set __irq_dma1_channel7, __default_handler + .weak __irq_adc .globl __irq_adc - .weakref __irq_usb_hp_can_tx, __default_handler + .set __irq_adc, __default_handler + .weak __irq_usb_hp_can_tx .globl __irq_usb_hp_can_tx - .weakref __irq_usb_lp_can_rx0, __default_handler + .set __irq_usb_hp_can_tx, __default_handler + .weak __irq_usb_lp_can_rx0 .globl __irq_usb_lp_can_rx0 - .weakref __irq_can_rx1, __default_handler + .set __irq_usb_lp_can_rx0, __default_handler + .weak __irq_can_rx1 .globl __irq_can_rx1 - .weakref __irq_can_sce, __default_handler + .set __irq_can_rx1, __default_handler + .weak __irq_can_sce .globl __irq_can_sce - .weakref __irq_exti9_5, __default_handler + .set __irq_can_sce, __default_handler + .weak __irq_exti9_5 .globl __irq_exti9_5 - .weakref __irq_tim1_brk, __default_handler + .set __irq_exti9_5, __default_handler + .weak __irq_tim1_brk .globl __irq_tim1_brk - .weakref __irq_tim1_up, __default_handler + .set __irq_tim1_brk, __default_handler + .weak __irq_tim1_up .globl __irq_tim1_up - .weakref __irq_tim1_trg_com, __default_handler + .set __irq_tim1_up, __default_handler + .weak __irq_tim1_trg_com .globl __irq_tim1_trg_com - .weakref __irq_tim1_cc, __default_handler + .set __irq_tim1_trg_com, __default_handler + .weak __irq_tim1_cc .globl __irq_tim1_cc + .set __irq_tim1_cc, __default_handler + .weakref __irq_tim2, __default_handler - .globl __irq_tim2 + .globl __irq_tim2 .weakref __irq_tim3, __default_handler - .globl __irq_tim3 + .globl __irq_tim3 .weakref __irq_tim4, __default_handler - .globl __irq_tim4 - .weakref __irq_i2c1_ev, __default_handler + .globl __irq_tim4 + + .weak __irq_i2c1_ev .globl __irq_i2c1_ev - .weakref __irq_i2c1_er, __default_handler + .set __irq_i2c1_ev, __default_handler + .weak __irq_i2c1_er .globl __irq_i2c1_er - .weakref __irq_i2c2_ev, __default_handler + .set __irq_i2c1_er, __default_handler + .weak __irq_i2c2_ev .globl __irq_i2c2_ev - .weakref __irq_i2c2_er, __default_handler + .set __irq_i2c2_ev, __default_handler + .weak __irq_i2c2_er .globl __irq_i2c2_er - .weakref __irq_spi1, __default_handler + .set __irq_i2c2_er, __default_handler + .weak __irq_spi1 .globl __irq_spi1 - .weakref __irq_spi2, __default_handler + .set __irq_spi1, __default_handler + .weak __irq_spi2 .globl __irq_spi2 - .weakref __irq_usart1, __default_handler + .set __irq_spi2, __default_handler + .weak __irq_usart1 .globl __irq_usart1 - .weakref __irq_usart2, __default_handler + .set __irq_usart1, __default_handler + .weak __irq_usart2 .globl __irq_usart2 - .weakref __irq_usart3, __default_handler + .set __irq_usart2, __default_handler + .weak __irq_usart3 .globl __irq_usart3 - .weakref __irq_exti15_10, __default_handler + .set __irq_usart3, __default_handler + .weak __irq_exti15_10 .globl __irq_exti15_10 - .weakref __irq_rtcalarm, __default_handler + .set __irq_exti15_10, __default_handler + .weak __irq_rtcalarm .globl __irq_rtcalarm - .weakref __irq_usbwakeup, __default_handler + .set __irq_rtcalarm, __default_handler + .weak __irq_usbwakeup .globl __irq_usbwakeup + .set __irq_usbwakeup, __default_handler #if defined (STM32_HIGH_DENSITY) - .weakref __irq_tim8_brk, __default_handler + .weak __irq_tim8_brk .globl __irq_tim8_brk - .weakref __irq_tim8_up, __default_handler + .set __irq_tim8_brk, __default_handler + .weak __irq_tim8_up .globl __irq_tim8_up - .weakref __irq_tim8_trg_com, __default_handler + .set __irq_tim8_up, __default_handler + .weak __irq_tim8_trg_com .globl __irq_tim8_trg_com - .weakref __irq_tim8_cc, __default_handler + .set __irq_tim8_trg_com, __default_handler + .weak __irq_tim8_cc .globl __irq_tim8_cc - .weakref __irq_adc3, __default_handler + .set __irq_tim8_cc, __default_handler + .weak __irq_adc3 .globl __irq_adc3 - .weakref __irq_fsmc, __default_handler + .set __irq_adc3, __default_handler + .weak __irq_fsmc .globl __irq_fsmc - .weakref __irq_sdio, __default_handler + .set __irq_fsmc, __default_handler + .weak __irq_sdio .globl __irq_sdio - .weakref __irq_tim5, __default_handler + .set __irq_sdio, __default_handler + .weak __irq_tim5 .globl __irq_tim5 - .weakref __irq_spi3, __default_handler + .set __irq_tim5, __default_handler + .weak __irq_spi3 .globl __irq_spi3 - .weakref __irq_uart4, __default_handler + .set __irq_spi3, __default_handler + .weak __irq_uart4 .globl __irq_uart4 - .weakref __irq_uart5, __default_handler + .set __irq_uart4, __default_handler + .weak __irq_uart5 .globl __irq_uart5 - .weakref __irq_tim6, __default_handler + .set __irq_uart5, __default_handler + .weak __irq_tim6 .globl __irq_tim6 - .weakref __irq_tim7, __default_handler + .set __irq_tim6, __default_handler + .weak __irq_tim7 .globl __irq_tim7 - .weakref __irq_dma2_channel1, __default_handler + .set __irq_tim7, __default_handler + .weak __irq_dma2_channel1 .globl __irq_dma2_channel1 - .weakref __irq_dma2_channel2, __default_handler + .set __irq_dma2_channel1, __default_handler + .weak __irq_dma2_channel2 .globl __irq_dma2_channel2 - .weakref __irq_dma2_channel3, __default_handler + .set __irq_dma2_channel2, __default_handler + .weak __irq_dma2_channel3 .globl __irq_dma2_channel3 - .weakref __irq_dma2_channel4_5, __default_handler + .set __irq_dma2_channel3, __default_handler + .weak __irq_dma2_channel4_5 .globl __irq_dma2_channel4_5 + .set __irq_dma2_channel4_5, __default_handler #endif /* STM32_HIGH_DENSITY */ \ No newline at end of file