fix compiler warnings related to __always_inline
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be6e7f0734
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@ -106,7 +106,7 @@ void detachInterrupt(uint8 pin);
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*
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* @see noInterrupts()
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*/
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static __always_inline void interrupts() {
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static inline __always_inline void interrupts() {
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nvic_globalirq_enable();
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}
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@ -120,7 +120,7 @@ static __always_inline void interrupts() {
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*
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* @see interrupts()
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*/
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static __always_inline void noInterrupts() {
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static inline __always_inline void noInterrupts() {
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nvic_globalirq_disable();
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}
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@ -250,7 +250,7 @@ void __irq_exti15_10(void) {
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* won't actually be cleared in time and the ISR will fire again. To
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* compensate, this function NOPs for 2 cycles after clearing the
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* pending bits to ensure it takes effect. */
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static __always_inline void clear_pending_msk(uint32 exti_msk) {
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static inline __always_inline void clear_pending_msk(uint32 exti_msk) {
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EXTI_BASE->PR = exti_msk;
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asm volatile("nop");
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asm volatile("nop");
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@ -258,7 +258,7 @@ static __always_inline void clear_pending_msk(uint32 exti_msk) {
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/* This dispatch routine is for non-multiplexed EXTI lines only; i.e.,
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* it doesn't check EXTI_PR. */
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static __always_inline void dispatch_single_exti(uint32 exti) {
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static inline __always_inline void dispatch_single_exti(uint32 exti) {
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voidArgumentFuncPtr handler = exti_channels[exti].handler;
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if (!handler) {
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@ -270,7 +270,7 @@ static __always_inline void dispatch_single_exti(uint32 exti) {
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}
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/* Dispatch routine for EXTIs which share an IRQ. */
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static __always_inline void dispatch_extis(uint32 start, uint32 stop) {
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static inline __always_inline void dispatch_extis(uint32 start, uint32 stop) {
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uint32 pr = EXTI_BASE->PR;
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uint32 handled_msk = 0;
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uint32 exti;
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@ -37,7 +37,7 @@
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/* Wrap this in an ifdef to shut up GCC. (We provide DMA_GET_HANDLER
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* in the series support files, which need dma_irq_handler().) */
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#ifdef DMA_GET_HANDLER
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static __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) {
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static inline __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) {
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void (*handler)(void) = DMA_GET_HANDLER(dev, tube);
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if (handler) {
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@ -57,8 +57,12 @@ typedef void (*voidArgumentFuncPtr)(void *);
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#define __packed __attribute__((__packed__))
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#define __deprecated __attribute__((__deprecated__))
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#define __weak __attribute__((weak))
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#define __always_inline inline __attribute__((always_inline))
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#ifndef __always_inline
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#define __always_inline __attribute__((always_inline))
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#endif
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#ifndef __unused
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#define __unused __attribute__((unused))
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#endif
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#ifndef NULL
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#define NULL 0
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@ -109,14 +109,14 @@ void nvic_sys_reset();
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/**
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* Enables interrupts and configurable fault handlers (clear PRIMASK).
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*/
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static __always_inline void nvic_globalirq_enable() {
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static inline __always_inline void nvic_globalirq_enable() {
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asm volatile("cpsie i");
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}
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/**
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* Disable interrupts and configurable fault handlers (set PRIMASK).
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*/
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static __always_inline void nvic_globalirq_disable() {
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static inline __always_inline void nvic_globalirq_disable() {
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asm volatile("cpsid i");
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}
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@ -169,7 +169,7 @@ int usb_cdcacm_get_n_data_bits(void); /* bDataBits */
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void usb_cdcacm_set_hooks(unsigned hook_flags, void (*hook)(unsigned, void*));
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static __always_inline void usb_cdcacm_remove_hooks(unsigned hook_flags) {
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static inline __always_inline void usb_cdcacm_remove_hooks(unsigned hook_flags) {
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usb_cdcacm_set_hooks(hook_flags, 0);
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}
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@ -484,7 +484,7 @@ typedef exti_num afio_exti_num;
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/**
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* @brief Deprecated. Use exti_select(exti, port) instead.
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*/
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static __always_inline void afio_exti_select(exti_num exti, exti_cfg port) {
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static inline __always_inline void afio_exti_select(exti_num exti, exti_cfg port) {
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exti_select(exti, port);
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}
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@ -75,7 +75,7 @@ extern void spi_config_gpios(struct spi_dev*, uint8,
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* @brief Deprecated. Use spi_config_gpios() instead.
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* @see spi_config_gpios()
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*/
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static __always_inline void spi_gpio_cfg(uint8 as_master,
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static inline __always_inline void spi_gpio_cfg(uint8 as_master,
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struct gpio_dev *nss_dev,
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uint8 nss_bit,
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struct gpio_dev *comm_dev,
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@ -707,7 +707,7 @@ void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n,
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* @param tube Tube whose memory 0 address to set
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* @param addr Address to use as memory 0
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*/
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static __always_inline void
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static inline __always_inline void
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dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
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dma_set_mem_n_addr(dev, tube, 0, addr);
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}
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@ -720,13 +720,13 @@ dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
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* @param tube Tube whose memory 1 address to set
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* @param addr Address to use as memory 1
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*/
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static __always_inline void
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static inline __always_inline void
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dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
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dma_set_mem_n_addr(dev, tube, 1, addr);
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}
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/* Assume the user means SM0AR in a non-double-buffered configuration. */
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static __always_inline void
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static inline __always_inline void
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dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
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dma_set_mem0_addr(dev, tube, addr);
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}
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@ -743,7 +743,7 @@ static inline dma_xfer_size dma_get_per_size(dma_dev *dev, dma_tube tube) {
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void dma_enable_fifo(dma_dev *dev, dma_tube tube);
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void dma_disable_fifo(dma_dev *dev, dma_tube tube);
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static __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) {
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static inline __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) {
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return dma_tube_regs(dev, tube)->SFCR & DMA_SFCR_DMDIS;
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}
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@ -769,7 +769,7 @@ static __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) {
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* I can't imagine why ST didn't just use a byte for each group. The
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* bits fit, and it would have made functions like these simpler and
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* faster. Oh well. */
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static __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) {
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static inline __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) {
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switch (tube) {
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case DMA_S0: /* fall through */
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case DMA_S4:
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@ -121,7 +121,7 @@
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* line may be shared with another timer. For example, the timer 1
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* update interrupt shares an IRQ line with the timer 10 interrupt on
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* STM32F1 (XL-density), STM32F2, and STM32F4. */
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static __always_inline void dispatch_single_irq(timer_dev *dev,
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static inline __always_inline void dispatch_single_irq(timer_dev *dev,
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timer_interrupt_id iid,
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uint32 irq_mask) {
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timer_bas_reg_map *regs = (dev->regs).bas;
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@ -145,15 +145,15 @@ static __always_inline void dispatch_single_irq(timer_dev *dev,
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} \
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} while (0)
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static __always_inline void dispatch_adv_brk(timer_dev *dev) {
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static inline __always_inline void dispatch_adv_brk(timer_dev *dev) {
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dispatch_single_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF);
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}
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static __always_inline void dispatch_adv_up(timer_dev *dev) {
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static inline __always_inline void dispatch_adv_up(timer_dev *dev) {
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dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF);
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}
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static __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
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static inline __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
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timer_adv_reg_map *regs = (dev->regs).adv;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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@ -168,7 +168,7 @@ static __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
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regs->SR &= ~handled;
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}
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static __always_inline void dispatch_adv_cc(timer_dev *dev) {
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static inline __always_inline void dispatch_adv_cc(timer_dev *dev) {
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timer_adv_reg_map *regs = (dev->regs).adv;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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@ -182,7 +182,7 @@ static __always_inline void dispatch_adv_cc(timer_dev *dev) {
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regs->SR &= ~handled;
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}
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static __always_inline void dispatch_general(timer_dev *dev) {
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static inline __always_inline void dispatch_general(timer_dev *dev) {
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timer_gen_reg_map *regs = (dev->regs).gen;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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@ -200,7 +200,7 @@ static __always_inline void dispatch_general(timer_dev *dev) {
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/* On F1 (XL-density), F2, and F4, TIM9 and TIM12 are restricted
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* general-purpose timers with update, CC1, CC2, and TRG interrupts. */
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static __always_inline void dispatch_tim_9_12(timer_dev *dev) {
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static inline __always_inline void dispatch_tim_9_12(timer_dev *dev) {
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timer_gen_reg_map *regs = (dev->regs).gen;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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@ -216,7 +216,7 @@ static __always_inline void dispatch_tim_9_12(timer_dev *dev) {
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/* On F1 (XL-density), F2, and F4, timers 10, 11, 13, and 14 are
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* restricted general-purpose timers with update and CC1 interrupts. */
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static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
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static inline __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
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timer_gen_reg_map *regs = (dev->regs).gen;
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uint32 dsr = regs->DIER & regs->SR;
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void (**hs)(void) = dev->handlers;
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@ -228,7 +228,7 @@ static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
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regs->SR &= ~handled;
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}
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static __always_inline void dispatch_basic(timer_dev *dev) {
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static inline __always_inline void dispatch_basic(timer_dev *dev) {
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dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF);
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}
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@ -37,7 +37,7 @@
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#include <libmaple/ring_buffer.h>
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#include <libmaple/usart.h>
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static __always_inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) {
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static inline __always_inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) {
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/* We can get RXNE and ORE interrupts here. Only RXNE signifies
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* availability of a byte in DR.
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*
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