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fix compiler warnings related to __always_inline

This commit is contained in:
Rick Kimball 2016-05-03 13:04:54 -04:00
parent be6e7f0734
commit f9aa37ed01
11 changed files with 31 additions and 27 deletions
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4
STM32F1/cores/maple/ext_interrupts.h
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@ -106,7 +106,7 @@ void detachInterrupt(uint8 pin);
* *
* @see noInterrupts() * @see noInterrupts()
*/ */
static __always_inline void interrupts() { static inline __always_inline void interrupts() {
nvic_globalirq_enable(); nvic_globalirq_enable();
} }
@ -120,7 +120,7 @@ static __always_inline void interrupts() {
* *
* @see interrupts() * @see interrupts()
*/ */
static __always_inline void noInterrupts() { static inline __always_inline void noInterrupts() {
nvic_globalirq_disable(); nvic_globalirq_disable();
} }

6
STM32F1/cores/maple/libmaple/exti.c
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@ -250,7 +250,7 @@ void __irq_exti15_10(void) {
* won't actually be cleared in time and the ISR will fire again. To * won't actually be cleared in time and the ISR will fire again. To
* compensate, this function NOPs for 2 cycles after clearing the * compensate, this function NOPs for 2 cycles after clearing the
* pending bits to ensure it takes effect. */ * pending bits to ensure it takes effect. */
static __always_inline void clear_pending_msk(uint32 exti_msk) { static inline __always_inline void clear_pending_msk(uint32 exti_msk) {
EXTI_BASE->PR = exti_msk; EXTI_BASE->PR = exti_msk;
asm volatile("nop"); asm volatile("nop");
asm volatile("nop"); asm volatile("nop");
@ -258,7 +258,7 @@ static __always_inline void clear_pending_msk(uint32 exti_msk) {
/* This dispatch routine is for non-multiplexed EXTI lines only; i.e., /* This dispatch routine is for non-multiplexed EXTI lines only; i.e.,
* it doesn't check EXTI_PR. */ * it doesn't check EXTI_PR. */
static __always_inline void dispatch_single_exti(uint32 exti) { static inline __always_inline void dispatch_single_exti(uint32 exti) {
voidArgumentFuncPtr handler = exti_channels[exti].handler; voidArgumentFuncPtr handler = exti_channels[exti].handler;
if (!handler) { if (!handler) {
@ -270,7 +270,7 @@ static __always_inline void dispatch_single_exti(uint32 exti) {
} }
/* Dispatch routine for EXTIs which share an IRQ. */ /* Dispatch routine for EXTIs which share an IRQ. */
static __always_inline void dispatch_extis(uint32 start, uint32 stop) { static inline __always_inline void dispatch_extis(uint32 start, uint32 stop) {
uint32 pr = EXTI_BASE->PR; uint32 pr = EXTI_BASE->PR;
uint32 handled_msk = 0; uint32 handled_msk = 0;
uint32 exti; uint32 exti;

2
STM32F1/system/libmaple/dma_private.h
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@ -37,7 +37,7 @@
/* Wrap this in an ifdef to shut up GCC. (We provide DMA_GET_HANDLER /* Wrap this in an ifdef to shut up GCC. (We provide DMA_GET_HANDLER
* in the series support files, which need dma_irq_handler().) */ * in the series support files, which need dma_irq_handler().) */
#ifdef DMA_GET_HANDLER #ifdef DMA_GET_HANDLER
static __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) { static inline __always_inline void dma_irq_handler(dma_dev *dev, dma_tube tube) {
void (*handler)(void) = DMA_GET_HANDLER(dev, tube); void (*handler)(void) = DMA_GET_HANDLER(dev, tube);
if (handler) { if (handler) {

6
STM32F1/system/libmaple/include/libmaple/libmaple_types.h
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@ -57,8 +57,12 @@ typedef void (*voidArgumentFuncPtr)(void *);
#define __packed __attribute__((__packed__)) #define __packed __attribute__((__packed__))
#define __deprecated __attribute__((__deprecated__)) #define __deprecated __attribute__((__deprecated__))
#define __weak __attribute__((weak)) #define __weak __attribute__((weak))
#define __always_inline inline __attribute__((always_inline)) #ifndef __always_inline
#define __always_inline __attribute__((always_inline))
#endif
#ifndef __unused
#define __unused __attribute__((unused)) #define __unused __attribute__((unused))
#endif
#ifndef NULL #ifndef NULL
#define NULL 0 #define NULL 0

4
STM32F1/system/libmaple/include/libmaple/nvic.h
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@ -109,14 +109,14 @@ void nvic_sys_reset();
/** /**
* Enables interrupts and configurable fault handlers (clear PRIMASK). * Enables interrupts and configurable fault handlers (clear PRIMASK).
*/ */
static __always_inline void nvic_globalirq_enable() { static inline __always_inline void nvic_globalirq_enable() {
asm volatile("cpsie i"); asm volatile("cpsie i");
} }
/** /**
* Disable interrupts and configurable fault handlers (set PRIMASK). * Disable interrupts and configurable fault handlers (set PRIMASK).
*/ */
static __always_inline void nvic_globalirq_disable() { static inline __always_inline void nvic_globalirq_disable() {
asm volatile("cpsid i"); asm volatile("cpsid i");
} }

2
STM32F1/system/libmaple/include/libmaple/usb_cdcacm.h
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@ -169,7 +169,7 @@ int usb_cdcacm_get_n_data_bits(void); /* bDataBits */
void usb_cdcacm_set_hooks(unsigned hook_flags, void (*hook)(unsigned, void*)); void usb_cdcacm_set_hooks(unsigned hook_flags, void (*hook)(unsigned, void*));
static __always_inline void usb_cdcacm_remove_hooks(unsigned hook_flags) { static inline __always_inline void usb_cdcacm_remove_hooks(unsigned hook_flags) {
usb_cdcacm_set_hooks(hook_flags, 0); usb_cdcacm_set_hooks(hook_flags, 0);
} }

2
STM32F1/system/libmaple/stm32f1/include/series/gpio.h
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@ -484,7 +484,7 @@ typedef exti_num afio_exti_num;
/** /**
* @brief Deprecated. Use exti_select(exti, port) instead. * @brief Deprecated. Use exti_select(exti, port) instead.
*/ */
static __always_inline void afio_exti_select(exti_num exti, exti_cfg port) { static inline __always_inline void afio_exti_select(exti_num exti, exti_cfg port) {
exti_select(exti, port); exti_select(exti, port);
} }

2
STM32F1/system/libmaple/stm32f1/include/series/spi.h
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@ -75,7 +75,7 @@ extern void spi_config_gpios(struct spi_dev*, uint8,
* @brief Deprecated. Use spi_config_gpios() instead. * @brief Deprecated. Use spi_config_gpios() instead.
* @see spi_config_gpios() * @see spi_config_gpios()
*/ */
static __always_inline void spi_gpio_cfg(uint8 as_master, static inline __always_inline void spi_gpio_cfg(uint8 as_master,
struct gpio_dev *nss_dev, struct gpio_dev *nss_dev,
uint8 nss_bit, uint8 nss_bit,
struct gpio_dev *comm_dev, struct gpio_dev *comm_dev,

10
STM32F1/system/libmaple/stm32f2/include/series/dma.h
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@ -707,7 +707,7 @@ void dma_set_mem_n_addr(dma_dev *dev, dma_tube tube, int n,
* @param tube Tube whose memory 0 address to set * @param tube Tube whose memory 0 address to set
* @param addr Address to use as memory 0 * @param addr Address to use as memory 0
*/ */
static __always_inline void static inline __always_inline void
dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) { dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
dma_set_mem_n_addr(dev, tube, 0, addr); dma_set_mem_n_addr(dev, tube, 0, addr);
} }
@ -720,13 +720,13 @@ dma_set_mem0_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
* @param tube Tube whose memory 1 address to set * @param tube Tube whose memory 1 address to set
* @param addr Address to use as memory 1 * @param addr Address to use as memory 1
*/ */
static __always_inline void static inline __always_inline void
dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) { dma_set_mem1_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
dma_set_mem_n_addr(dev, tube, 1, addr); dma_set_mem_n_addr(dev, tube, 1, addr);
} }
/* Assume the user means SM0AR in a non-double-buffered configuration. */ /* Assume the user means SM0AR in a non-double-buffered configuration. */
static __always_inline void static inline __always_inline void
dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) { dma_set_mem_addr(dma_dev *dev, dma_tube tube, __io void *addr) {
dma_set_mem0_addr(dev, tube, addr); dma_set_mem0_addr(dev, tube, addr);
} }
@ -743,7 +743,7 @@ static inline dma_xfer_size dma_get_per_size(dma_dev *dev, dma_tube tube) {
void dma_enable_fifo(dma_dev *dev, dma_tube tube); void dma_enable_fifo(dma_dev *dev, dma_tube tube);
void dma_disable_fifo(dma_dev *dev, dma_tube tube); void dma_disable_fifo(dma_dev *dev, dma_tube tube);
static __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) { static inline __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) {
return dma_tube_regs(dev, tube)->SFCR & DMA_SFCR_DMDIS; return dma_tube_regs(dev, tube)->SFCR & DMA_SFCR_DMDIS;
} }
@ -769,7 +769,7 @@ static __always_inline int dma_is_fifo_enabled(dma_dev *dev, dma_tube tube) {
* I can't imagine why ST didn't just use a byte for each group. The * I can't imagine why ST didn't just use a byte for each group. The
* bits fit, and it would have made functions like these simpler and * bits fit, and it would have made functions like these simpler and
* faster. Oh well. */ * faster. Oh well. */
static __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) { static inline __always_inline uint32 _dma_sr_fcr_shift(dma_tube tube) {
switch (tube) { switch (tube) {
case DMA_S0: /* fall through */ case DMA_S0: /* fall through */
case DMA_S4: case DMA_S4:

18
STM32F1/system/libmaple/timer_private.h
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@ -121,7 +121,7 @@
* line may be shared with another timer. For example, the timer 1 * line may be shared with another timer. For example, the timer 1
* update interrupt shares an IRQ line with the timer 10 interrupt on * update interrupt shares an IRQ line with the timer 10 interrupt on
* STM32F1 (XL-density), STM32F2, and STM32F4. */ * STM32F1 (XL-density), STM32F2, and STM32F4. */
static __always_inline void dispatch_single_irq(timer_dev *dev, static inline __always_inline void dispatch_single_irq(timer_dev *dev,
timer_interrupt_id iid, timer_interrupt_id iid,
uint32 irq_mask) { uint32 irq_mask) {
timer_bas_reg_map *regs = (dev->regs).bas; timer_bas_reg_map *regs = (dev->regs).bas;
@ -145,15 +145,15 @@ static __always_inline void dispatch_single_irq(timer_dev *dev,
} \ } \
} while (0) } while (0)
static __always_inline void dispatch_adv_brk(timer_dev *dev) { static inline __always_inline void dispatch_adv_brk(timer_dev *dev) {
dispatch_single_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF); dispatch_single_irq(dev, TIMER_BREAK_INTERRUPT, TIMER_SR_BIF);
} }
static __always_inline void dispatch_adv_up(timer_dev *dev) { static inline __always_inline void dispatch_adv_up(timer_dev *dev) {
dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF);
} }
static __always_inline void dispatch_adv_trg_com(timer_dev *dev) { static inline __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
timer_adv_reg_map *regs = (dev->regs).adv; timer_adv_reg_map *regs = (dev->regs).adv;
uint32 dsr = regs->DIER & regs->SR; uint32 dsr = regs->DIER & regs->SR;
void (**hs)(void) = dev->handlers; void (**hs)(void) = dev->handlers;
@ -168,7 +168,7 @@ static __always_inline void dispatch_adv_trg_com(timer_dev *dev) {
regs->SR &= ~handled; regs->SR &= ~handled;
} }
static __always_inline void dispatch_adv_cc(timer_dev *dev) { static inline __always_inline void dispatch_adv_cc(timer_dev *dev) {
timer_adv_reg_map *regs = (dev->regs).adv; timer_adv_reg_map *regs = (dev->regs).adv;
uint32 dsr = regs->DIER & regs->SR; uint32 dsr = regs->DIER & regs->SR;
void (**hs)(void) = dev->handlers; void (**hs)(void) = dev->handlers;
@ -182,7 +182,7 @@ static __always_inline void dispatch_adv_cc(timer_dev *dev) {
regs->SR &= ~handled; regs->SR &= ~handled;
} }
static __always_inline void dispatch_general(timer_dev *dev) { static inline __always_inline void dispatch_general(timer_dev *dev) {
timer_gen_reg_map *regs = (dev->regs).gen; timer_gen_reg_map *regs = (dev->regs).gen;
uint32 dsr = regs->DIER & regs->SR; uint32 dsr = regs->DIER & regs->SR;
void (**hs)(void) = dev->handlers; void (**hs)(void) = dev->handlers;
@ -200,7 +200,7 @@ static __always_inline void dispatch_general(timer_dev *dev) {
/* On F1 (XL-density), F2, and F4, TIM9 and TIM12 are restricted /* On F1 (XL-density), F2, and F4, TIM9 and TIM12 are restricted
* general-purpose timers with update, CC1, CC2, and TRG interrupts. */ * general-purpose timers with update, CC1, CC2, and TRG interrupts. */
static __always_inline void dispatch_tim_9_12(timer_dev *dev) { static inline __always_inline void dispatch_tim_9_12(timer_dev *dev) {
timer_gen_reg_map *regs = (dev->regs).gen; timer_gen_reg_map *regs = (dev->regs).gen;
uint32 dsr = regs->DIER & regs->SR; uint32 dsr = regs->DIER & regs->SR;
void (**hs)(void) = dev->handlers; void (**hs)(void) = dev->handlers;
@ -216,7 +216,7 @@ static __always_inline void dispatch_tim_9_12(timer_dev *dev) {
/* On F1 (XL-density), F2, and F4, timers 10, 11, 13, and 14 are /* On F1 (XL-density), F2, and F4, timers 10, 11, 13, and 14 are
* restricted general-purpose timers with update and CC1 interrupts. */ * restricted general-purpose timers with update and CC1 interrupts. */
static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) { static inline __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
timer_gen_reg_map *regs = (dev->regs).gen; timer_gen_reg_map *regs = (dev->regs).gen;
uint32 dsr = regs->DIER & regs->SR; uint32 dsr = regs->DIER & regs->SR;
void (**hs)(void) = dev->handlers; void (**hs)(void) = dev->handlers;
@ -228,7 +228,7 @@ static __always_inline void dispatch_tim_10_11_13_14(timer_dev *dev) {
regs->SR &= ~handled; regs->SR &= ~handled;
} }
static __always_inline void dispatch_basic(timer_dev *dev) { static inline __always_inline void dispatch_basic(timer_dev *dev) {
dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF); dispatch_single_irq(dev, TIMER_UPDATE_INTERRUPT, TIMER_SR_UIF);
} }

2
STM32F1/system/libmaple/usart_private.h
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@ -37,7 +37,7 @@
#include <libmaple/ring_buffer.h> #include <libmaple/ring_buffer.h>
#include <libmaple/usart.h> #include <libmaple/usart.h>
static __always_inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) { static inline __always_inline void usart_irq(ring_buffer *rb, usart_reg_map *regs) {
/* We can get RXNE and ORE interrupts here. Only RXNE signifies /* We can get RXNE and ORE interrupts here. Only RXNE signifies
* availability of a byte in DR. * availability of a byte in DR.
* *