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Merge pull request #151 from martinayotte/master 

STM32F4 - fix LeafLab code for spi_config_gpios()
This commit is contained in:
Roger Clark 2015-12-10 09:35:17 +11:00
parent d68220b964 e1b85b7774
commit fe7bae21a1
12 changed files with 70 additions and 343 deletions
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22
STM32F4/cores/maple/libmaple/HardwareSPI.cpp
View File

@ -385,21 +385,15 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
#endif
if(nssi) {
spi_gpio_cfg(as_master,
nssi->gpio_device,
nssi->gpio_bit,
scki->gpio_device,
scki->gpio_bit,
misoi->gpio_bit,
mosii->gpio_bit);
spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
scki->gpio_device, scki->gpio_bit,
misoi->gpio_device, misoi->gpio_bit,
mosii->gpio_device, mosii->gpio_bit);
} else {
spi_gpio_cfg(as_master,
NULL,
-1,
scki->gpio_device,
scki->gpio_bit,
misoi->gpio_bit,
mosii->gpio_bit);
spi_config_gpios(dev, as_master, NULL, -1,
scki->gpio_device, scki->gpio_bit,
misoi->gpio_device, misoi->gpio_bit,
mosii->gpio_device, mosii->gpio_bit);
}
}

1
STM32F4/cores/maple/libmaple/bkp.c Symbolic link
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@ -0,0 +1 @@
bkp.c.xxx

129
STM32F4/cores/maple/libmaple/bkp.c.xxx
View File

@ -1,129 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file bkp.c
* @brief Backup register support.
*/
#include "bkp.h"
#include "pwr.h"
#include "rcc.h"
#include "bitband.h"
static inline __io uint32* data_register(uint8 reg);
bkp_dev bkp = {
.regs = BKP_BASE,
};
/** Backup device. */
const bkp_dev *BKP = &bkp;
/**
* @brief Initialize backup interface.
*
* Enables the power and backup interface clocks, and resets the
* backup device.
*/
void bkp_init(void) {
/* Don't call pwr_init(), or you'll reset the device. We just
* need the clock. */
rcc_clk_enable(RCC_PWR);
rcc_clk_enable(RCC_BKP);
rcc_reset_dev(RCC_BKP);
}
/**
* Enable write access to the backup registers. Backup interface must
* be initialized for subsequent register writes to work.
* @see bkp_init()
*/
void bkp_enable_writes(void) {
*bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 1;
}
/**
* Disable write access to the backup registers.
*/
void bkp_disable_writes(void) {
*bb_perip(&PWR_BASE->CR, PWR_CR_DBP) = 0;
}
/**
* Read a value from given backup data register.
* @param reg Data register to read, from 1 to BKP_NR_DATA_REGS (10 on
* medium-density devices, 42 on high-density devices).
*/
uint16 bkp_read(uint8 reg) {
__io uint32* dr = data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return 0;
}
return (uint16)*dr;
}
/**
* @brief Write a value to given data register.
*
* Write access to backup registers must be enabled.
*
* @param reg Data register to write, from 1 to BKP_NR_DATA_REGS (10
* on medium-density devices, 42 on high-density devices).
* @param val Value to write into the register.
* @see bkp_enable_writes()
*/
void bkp_write(uint8 reg, uint16 val) {
__io uint32* dr = data_register(reg);
if (!dr) {
ASSERT(0); /* nonexistent register */
return;
}
*dr = (uint32)val;
}
/*
* Data register memory layout is not contiguous. It's split up from
* 1--NR_LOW_DRS, beginning at BKP_BASE->DR1, through to
* (NR_LOW_DRS+1)--BKP_NR_DATA_REGS, beginning at BKP_BASE->DR11.
*/
#define NR_LOW_DRS 10
static inline __io uint32* data_register(uint8 reg) {
if (reg < 1 || reg > BKP_NR_DATA_REGS) {
return 0;
}
#if BKP_NR_DATA_REGS == NR_LOW_DRS
return (uint32*)BKP_BASE + reg;
#else
if (reg <= NR_LOW_DRS) {
return (uint32*)BKP_BASE + reg;
} else {
return (uint32*)&(BKP_BASE->DR11) + (reg - NR_LOW_DRS - 1);
}
#endif
}

1
STM32F4/cores/maple/libmaple/bkp.h Symbolic link
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@ -0,0 +1 @@
bkp.h.xxx

166
STM32F4/cores/maple/libmaple/bkp.h.xxx
View File

@ -1,166 +0,0 @@
/******************************************************************************
* The MIT License
*
* Copyright (c) 2010 LeafLabs, LLC.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy,
* modify, merge, publish, distribute, sublicense, and/or sell copies
* of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*****************************************************************************/
/**
* @file bkp.h
* @brief Backup register support.
*/
#ifndef _BKP_H_
#define _BKP_H_
#include "libmaple.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32_MEDIUM_DENSITY)
#define BKP_NR_DATA_REGS 10
#elif defined(STM32_HIGH_DENSITY)
#define BKP_NR_DATA_REGS 42
#endif
/** Backup peripheral register map type. */
typedef struct bkp_reg_map {
const uint32 RESERVED1; ///< Reserved
__io uint32 DR1; ///< Data register 1
__io uint32 DR2; ///< Data register 2
__io uint32 DR3; ///< Data register 3
__io uint32 DR4; ///< Data register 4
__io uint32 DR5; ///< Data register 5
__io uint32 DR6; ///< Data register 6
__io uint32 DR7; ///< Data register 7
__io uint32 DR8; ///< Data register 8
__io uint32 DR9; ///< Data register 9
__io uint32 DR10; ///< Data register 10
__io uint32 RTCCR; ///< RTC control register
__io uint32 CR; ///< Control register
__io uint32 CSR; ///< Control and status register
#ifdef STM32_HIGH_DENSITY
const uint32 RESERVED2; ///< Reserved
const uint32 RESERVED3; ///< Reserved
__io uint32 DR11; ///< Data register 11
__io uint32 DR12; ///< Data register 12
__io uint32 DR13; ///< Data register 13
__io uint32 DR14; ///< Data register 14
__io uint32 DR15; ///< Data register 15
__io uint32 DR16; ///< Data register 16
__io uint32 DR17; ///< Data register 17
__io uint32 DR18; ///< Data register 18
__io uint32 DR19; ///< Data register 19
__io uint32 DR20; ///< Data register 20
__io uint32 DR21; ///< Data register 21
__io uint32 DR22; ///< Data register 22
__io uint32 DR23; ///< Data register 23
__io uint32 DR24; ///< Data register 24
__io uint32 DR25; ///< Data register 25
__io uint32 DR26; ///< Data register 26
__io uint32 DR27; ///< Data register 27
__io uint32 DR28; ///< Data register 28
__io uint32 DR29; ///< Data register 29
__io uint32 DR30; ///< Data register 30
__io uint32 DR31; ///< Data register 31
__io uint32 DR32; ///< Data register 32
__io uint32 DR33; ///< Data register 33
__io uint32 DR34; ///< Data register 34
__io uint32 DR35; ///< Data register 35
__io uint32 DR36; ///< Data register 36
__io uint32 DR37; ///< Data register 37
__io uint32 DR38; ///< Data register 38
__io uint32 DR39; ///< Data register 39
__io uint32 DR40; ///< Data register 40
__io uint32 DR41; ///< Data register 41
__io uint32 DR42; ///< Data register 42
#endif
} bkp_reg_map;
/** Backup peripheral register map base pointer. */
#define BKP_BASE ((struct bkp_reg_map*)0x40006C00)
/** Backup peripheral device type. */
typedef struct bkp_dev {
bkp_reg_map *regs; /**< Register map */
} bkp_dev;
extern const bkp_dev *BKP;
/*
* Register bit definitions
*/
/* Data Registers */
#define BKP_DR_D 0xFFFF
/* RTC Clock Calibration Register */
#define BKP_RTCCR_ASOS_BIT 9
#define BKP_RTCCR_ASOE_BIT 8
#define BKP_RTCCR_CCO_BIT 7
#define BKP_RTCCR_ASOS BIT(BKP_RTCCR_ASOS_BIT)
#define BKP_RTCCR_ASOE BIT(BKP_RTCCR_ASOE_BIT)
#define BKP_RTCCR_CCO BIT(BKP_RTCCR_CCO_BIT)
#define BKP_RTCCR_CAL 0x7F
/* Backup control register */
#define BKP_CR_TPAL_BIT 1
#define BKP_CR_TPE_BIT 0
#define BKP_CR_TPAL BIT(BKP_CR_TPAL_BIT)
#define BKP_CR_TPE BIT(BKP_CR_TPE_BIT)
/* Backup control/status register */
#define BKP_CSR_TIF_BIT 9
#define BKP_CSR_TEF_BIT 8
#define BKP_CSR_TPIE_BIT 2
#define BKP_CSR_CTI_BIT 1
#define BKP_CSR_CTE_BIT 0
#define BKP_CSR_TIF BIT(BKP_CSR_TIF_BIT)
#define BKP_CSR_TEF BIT(BKP_CSR_TEF_BIT)
#define BKP_CSR_TPIE BIT(BKP_CSR_TPIE_BIT)
#define BKP_CSR_CTI BIT(BKP_CSR_CTI_BIT)
#define BKP_CSR_CTE BIT(BKP_CSR_CTE_BIT)
/*
* Convenience functions
*/
void bkp_init(void);
void bkp_enable_writes(void);
void bkp_disable_writes(void);
uint16 bkp_read(uint8 reg);
void bkp_write(uint8 reg, uint16 val);
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif

2
STM32F4/cores/maple/libmaple/rccF2.c
View File

@ -74,7 +74,7 @@ static const struct rcc_dev_info rcc_dev_table[] = {
[RCC_SPI2] = { .clk_domain = APB1, .line_num = 14 }, //unchanged
[RCC_DMA1] = { .clk_domain = AHB1, .line_num = 21 }, //*
[RCC_PWR] = { .clk_domain = APB1, .line_num = 28}, //unchanged
// [RCC_BKP] = { .clk_domain = AHB1, .line_num = 18}, //*
[RCC_BKP] = { .clk_domain = AHB1, .line_num = 18}, //*
[RCC_I2C1] = { .clk_domain = APB1, .line_num = 21 }, //unchanged
[RCC_I2C2] = { .clk_domain = APB1, .line_num = 22 }, //unchanged
[RCC_CRC] = { .clk_domain = AHB1, .line_num = 12}, //*

33
STM32F4/cores/maple/libmaple/rccF2.h
View File

@ -30,6 +30,7 @@
*/
#include "libmaple_types.h"
#include "bitband.h"
#ifndef _RCC_H_
#define _RCC_H_
@ -385,6 +386,7 @@ typedef struct
#define RCC_BDCR_RTCSEL (0x3 << 8)
#define RCC_BDCR_RTCSEL_NONE (0x0 << 8)
#define RCC_BDCR_RTCSEL_LSE (0x1 << 8)
#define RCC_BDCR_RTCSEL_LSI (0x2 << 8)
#define RCC_BDCR_RTCSEL_HSE (0x3 << 8)
#define RCC_BDCR_LSEBYP BIT(RCC_BDCR_LSEBYP_BIT)
#define RCC_BDCR_LSERDY BIT(RCC_BDCR_LSERDY_BIT)
@ -483,7 +485,7 @@ typedef enum rcc_clk_id {
RCC_SPI2,
RCC_DMA1,
RCC_PWR,
// RCC_BKP,
RCC_BKP,
RCC_I2C1,
RCC_I2C2,
RCC_CRC,
@ -604,6 +606,35 @@ typedef enum rcc_ahb_divider {
void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
/**
* @brief Start the low speed internal oscillatior
*/
static inline void rcc_start_lsi(void) {
*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
}
/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */
/**
* @brief Start the low speed external oscillatior
*/
static inline void rcc_start_lse(void) {
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
}
/*
* Deprecated bits.
*/
static inline void rcc_start_hse(void) { // Added to support RTClock
// *bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
}
#ifdef __cplusplus
} // extern "C"
#endif

8
STM32F4/cores/maple/libmaple/spi.h
View File

@ -221,18 +221,22 @@ struct gpio_dev;
* @param as_master If true, configure as bus master; otherwise, as slave.
* @param nss_dev NSS pin's GPIO device
* @param nss_bit NSS pin's GPIO bit on nss_dev
* @param comm_dev SCK, MISO, MOSI pins' GPIO device
* @param sck_dev SCK pin's GPIO device
* @param sck_bit SCK pin's GPIO bit on comm_dev
* @param miso_dev MISO pin's GPIO device
* @param miso_bit MISO pin's GPIO bit on comm_dev
* @param mosi_dev MOSI pin's GPIO device
* @param mosi_bit MOSI pin's GPIO bit on comm_dev
*/
extern void spi_config_gpios(spi_dev *dev,
uint8 as_master,
struct gpio_dev *nss_dev,
uint8 nss_bit,
struct gpio_dev *comm_dev,
struct gpio_dev *sck_dev,
uint8 sck_bit,
struct gpio_dev *miso_dev,
uint8 miso_bit,
struct gpio_dev *mosi_dev,
uint8 mosi_bit);
/**

24
STM32F4/cores/maple/libmaple/spiF4.h
View File

@ -70,27 +70,9 @@ extern struct spi_dev *SPI3;
struct gpio_dev;
extern void spi_config_gpios(struct spi_dev*, uint8,
struct gpio_dev*, uint8,
struct gpio_dev*, uint8, uint8, uint8);
/**
* @brief Deprecated. Use spi_config_gpios() instead.
* @see spi_config_gpios()
*/
static __always_inline void spi_gpio_cfg(uint8 as_master,
struct gpio_dev *nss_dev,
uint8 nss_bit,
struct gpio_dev *comm_dev,
uint8 sck_bit,
uint8 miso_bit,
uint8 mosi_bit) {
/* We switched style globally to foo_config_gpios() and always
* taking a foo_dev* argument (that last bit is the important
* part) after this function was written.
*
* However, spi_config_gpios() just ignores the spi_dev* on F1, so
* we can still keep this around for older code. */
spi_config_gpios(NULL, as_master, nss_dev, nss_bit,
comm_dev, sck_bit, miso_bit, mosi_bit);
}
struct gpio_dev*, uint8,
struct gpio_dev*, uint8,
struct gpio_dev*, uint8);
#ifdef __cplusplus
}

16
STM32F4/cores/maple/libmaple/spi_f4.c
View File

@ -58,21 +58,23 @@ void spi_config_gpios(spi_dev *ignored,
uint8 as_master,
gpio_dev *nss_dev,
uint8 nss_bit,
gpio_dev *comm_dev,
gpio_dev *sck_dev,
uint8 sck_bit,
gpio_dev *miso_dev,
uint8 miso_bit,
gpio_dev *mosi_dev,
uint8 mosi_bit) {
if (as_master) {
// gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(comm_dev, sck_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(sck_dev, sck_bit, GPIO_AF_OUTPUT_PP);
// gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(comm_dev, miso_bit, GPIO_AF_INPUT_PD);
gpio_set_mode(comm_dev, mosi_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(miso_dev, miso_bit, GPIO_AF_INPUT_PD);
gpio_set_mode(mosi_dev, mosi_bit, GPIO_AF_OUTPUT_PP);
} else {
gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(comm_dev, sck_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(comm_dev, miso_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(comm_dev, mosi_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(sck_dev, sck_bit, GPIO_INPUT_FLOATING);
gpio_set_mode(miso_dev, miso_bit, GPIO_AF_OUTPUT_PP);
gpio_set_mode(mosi_dev, mosi_bit, GPIO_INPUT_FLOATING);
}
}

5
STM32F4/libraries/SPI/src/SPI.cpp
View File

@ -605,8 +605,9 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
#endif
spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
mosii->gpio_bit);
scki->gpio_device, scki->gpio_bit,
misoi->gpio_device, misoi->gpio_bit,
mosii->gpio_device, mosii->gpio_bit);
}
static const spi_baud_rate baud_rates[8] __FLASH__ = {

6
STM32F4/variants/discovery_f407/pins_arduino.h Normal file
View File

@ -0,0 +1,6 @@
// API compatibility
#include "variant.h"