217 lines
5.6 KiB
C
217 lines
5.6 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2012 LeafLabs, LLC.
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f1/adc.c
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* @author Marti Bolivar <mbolivar@leaflabs.com>,
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* Perry Hung <perry@leaflabs.com>
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* @brief STM32F1 ADC support.
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*/
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#include <libmaple/adc.h>
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#include <libmaple/gpio.h>
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#include <libmaple/nvic.h>//Added by bubulindo.
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/*
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* Devices
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*/
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adc_dev adc1 = {
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.regs = ADC1_BASE,
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.clk_id = RCC_ADC1,
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.handlers = {[3]=0}, //added by bubulindo. EOC, JEOC, AWD
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.irq_num = NVIC_ADC_1_2,
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};
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/** ADC1 device. */
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adc_dev *ADC1 = &adc1;
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adc_dev adc2 = {
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.regs = ADC2_BASE,
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.clk_id = RCC_ADC2,
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};
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/** ADC2 device. */
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adc_dev *ADC2 = &adc2;
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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adc_dev adc3 = {
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.regs = ADC3_BASE,
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.clk_id = RCC_ADC3,
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.handlers = {[3]=0}, //added by bubulindo. EOC, JEOC, AWD
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.irq_num = NVIC_ADC3,//added by bubulindo.
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};
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/** ADC3 device. */
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adc_dev *ADC3 = &adc3;
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#endif
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/*
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adc irq routine.
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Added by bubulindo.
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*/
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__weak void __irq_adc() {
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//get status
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uint32 adc_sr = ADC1->regs->SR;
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//End Of Conversion
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if (adc_sr & (1U << ADC_SR_EOC_BIT)) {
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ADC1->regs->SR &= ~(1<<ADC_SR_EOC_BIT);
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void (*handler)(void) = ADC1->handlers[ADC_EOC];
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if (handler) {
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handler();
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}
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}
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//Injected End Of Conversion
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if (adc_sr & (1U << ADC_SR_JEOC_BIT)) {
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ADC1->regs->SR &= ~(1<<ADC_SR_JEOC_BIT);
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void (*handler)(void) = ADC1->handlers[ADC_JEOC];
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if (handler) {
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handler();
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}
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}
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//Analog Watchdog
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if (adc_sr & (1U << ADC_SR_AWD_BIT)) {
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ADC1->regs->SR &= ~(1<<ADC_SR_AWD_BIT);
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void (*handler)(void) = ADC1->handlers[ADC_AWD];
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if (handler) {
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handler();
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}
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}
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};//end of adc irq
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/*
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ADC3 IRQ handler.
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added by bubulindo
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*/
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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__weak void __irq_adc3() {
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//get status
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uint32 adc_sr = ADC3->regs->SR;
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//End Of Conversion
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if (adc_sr & (1U << ADC_SR_EOC_BIT)) {
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ADC3->regs->SR &= ~(1<<ADC_SR_EOC_BIT);
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void (*handler)(void) = ADC3->handlers[ADC_EOC];
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if (handler) {
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handler();
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}
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}
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//Injected End Of Conversion
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if (adc_sr & (1U << ADC_SR_JEOC_BIT)) {
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ADC3->regs->SR &= ~(1<<ADC_SR_JEOC_BIT);
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void (*handler)(void) = ADC3->handlers[ADC_JEOC];
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if (handler) {
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handler();
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}
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}
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//Analog Watchdog
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if (adc_sr & (1U << ADC_SR_AWD_BIT)) {
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ADC3->regs->SR &= ~(1<<ADC_SR_AWD_BIT);
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void (*handler)(void) = ADC3->handlers[ADC_AWD];
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if (handler) {
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handler();
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}
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}
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};//end of ADC3 irq
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#endif
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/*
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enable interrupts on the ADC:
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use ADC_EOC, ADC_JEOC, ADC_AWD
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This will set up the interrupt bit in the ADC as well as in the NVIC.
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added by bubulindo
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*/
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void adc_enable_irq(adc_dev* dev, uint8 interrupt) {//ADC1 for now.
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dev->regs->CR1 |= (1U<<(interrupt +ADC_CR1_EOCIE_BIT));
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nvic_irq_enable(dev->irq_num);
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}
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/*
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attach interrupt functionality for ADC
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use ADC_EOC, ADC_JEOC, ADC_AWD
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added by bubulindo
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*/
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void adc_attach_interrupt(adc_dev *dev,
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uint8 interrupt,
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voidFuncPtr handler) {
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dev->handlers[interrupt] = handler;
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adc_enable_irq(dev, interrupt);
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//enable_irq(dev, interrupt); //I need to create this function. to enable NVIC
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// nvic_irq_enable()
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}
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/*
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* STM32F1 routines
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*/
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/**
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* @brief Calibrate an ADC peripheral
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*
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* Availability: STM32F1.
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*
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* @param dev adc device
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*/
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void adc_calibrate(adc_dev *dev) {
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__IO uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
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__IO uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
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*rstcal_bit = 1;
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while (*rstcal_bit)
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;
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*cal_bit = 1;
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while (*cal_bit)
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;
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}
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/*
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* Common routines
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*/
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void adc_set_prescaler(adc_prescaler pre) {
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rcc_set_prescaler(RCC_PRESCALER_ADC, (uint32)pre);
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}
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void adc_foreach(void (*fn)(adc_dev*)) {
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fn(ADC1);
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fn(ADC2);
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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fn(ADC3);
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#endif
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}
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void adc_config_gpio(adc_dev *ignored __attribute__((unused)), gpio_dev *gdev, uint8 bit) {
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gpio_set_mode(gdev, bit, GPIO_INPUT_ANALOG);
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}
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void adc_enable_single_swstart(adc_dev *dev) {
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adc_init(dev);
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adc_set_extsel(dev, ADC_SWSTART);
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adc_set_exttrig(dev, 1);
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adc_enable(dev);
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adc_calibrate(dev);
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}
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