251 lines
13 KiB
C
251 lines
13 KiB
C
/******************************************************************************
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file sdio.h
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* @brief Secure digital input/output interface.
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*/
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#ifndef _SDIO_H_
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#define _SDIO_H_
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#include "libmaple_types.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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#ifdef STM32_HIGH_DENSITY
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/*
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* Register maps and devices
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*/
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// SDIO register map type
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typedef struct sdio_reg_map {
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__IO uint32 POWER; // 0x00
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__IO uint32 CLKCR; // 0x04
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__IO uint32 ARG; // 0x08
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__IO uint32 CMD; // 0x0C
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__IO uint32 RESPCMD; // 0x10 (0x3F)
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const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response.
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__IO uint32 DTIMER; // 0x24 - contains the data timeout period, in card bus clock periods.
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__IO uint32 DLEN; // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
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__IO uint32 DCTRL; // 0x2C
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__IO uint32 DCOUNT; // 0x30 (0x01FF FFFF)
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__IO uint32 STA; // 0x34
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__IO uint32 ICR; // 0x38
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__IO uint32 MASK; // 0x3C
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const uint32 RESERVED1[2];
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__IO uint32 FIFOCNT; // 0x48 (0x01FF FFFF)
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const uint32 RESERVED2[13];
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__IO uint32 FIFO; // 0x80
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} sdio_reg_map;
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#define sdio_dev sdio_reg_map
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/** SDIO register map base pointer */
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#define SDIO_BASE ((struct sdio_reg_map*)0x40012C00)
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extern sdio_dev * SDIO;
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/*
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* Register bit definitions
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*/
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/* NOR/PSRAM chip-select control registers */
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// SDIO_POWER register bits
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// At least seven HCLK clock periods are needed between two write accesses to this register.
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// After a data write, data cannot be written to this register for three SDIOCLK clock periods
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// plus two PCLK2 clock periods.
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#define SDIO_POWER_PWRCTRL_OFF 0x00
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#define SDIO_POWER_PWRCTRL_ON 0x03
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// SDIO_CLKCR register bits
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// Controls the SDIO_CK output clock.
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// After a data write, data cannot be written to this register for three SDIOCLK clock periods
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// plus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval
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// for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.
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#define SDIO_CLKCR_HWFC_EN (1<<14) // HW Flow Control enable - DON'T USE!!! (see errata sheet 2.12.1)
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// Overrun errors (Rx mode) and FIFO underrun (Tx mode)
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// should be managed by the application software.
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#define SDIO_CLKCR_NEGEDGE (1<<13) // SDIO_CK de-phasing selection bit - DON'T USE!!! (see errata sheet 2.12.4)
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#define SDIO_CLKCR_WIDBUS (3<<11) // Data bus width
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#define SDIO_CLKCR_WIDBUS_1BIT (0<<11) // 1 bit (SDIO_D0 used)
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#define SDIO_CLKCR_WIDBUS_4BIT (1<<11) // 4-bit (SDIO_D[3:0] used)
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#define SDIO_CLKCR_BYPASS (1<<10) // Clock divider bypass enable bit - SDIO_CK = SDIOCLK, CLKDIV not relevant.
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#define SDIO_CLKCR_PWRSAV (1<<9) // 0: SDIO_CK clock is always enabled, 1: SDIO_CK is only enabled when the bus is active
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#define SDIO_CLKCR_CLKEN (1<<8) // Clock enable
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#define SDIO_CLKCR_CLKDIV (0xFF) // SDIO_CK = SDIOCLK / [CLKDIV + 2]
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#define SDIOCLK 48000000UL // SDIO master clock frequency
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// SDIO_CMD register bits
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// After a data write, data cannot be written to this register for three SDIOCLK clock periods
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// plus two PCLK2 clock periods.
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// MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long
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// responses,136 bits long. SD card and SD I/O card can send only short responses, the
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// argument can vary according to the type of response: the software will distinguish the type
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// of response according to the sent command. CE-ATA devices send only short responses.
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#define SDIO_CMD_ATACMD (1<<14)
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#define SDIO_CMD_NIEN (1<<13)
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#define SDIO_CMD_ENCMDCOMPL (1<<12)
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#define SDIO_CMD_SDIOSUSPEND (1<<11)
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#define SDIO_CMD_CPSMEN (1<<10)
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#define SDIO_CMD_WAITPEND (1<<9)
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#define SDIO_CMD_WAITINT (1<<8)
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#define SDIO_CMD_WAITRESP (3<<6)
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#define SDIO_CMD_WAIT_NO_RESP (0<<6)
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#define SDIO_CMD_WAIT_SHORT_RESP (1<<6)
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#define SDIO_CMD_WAIT_LONG_RESP (3<<6)
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#define SDIO_CMD_CMDINDEX (0x3F)
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// SDIO_DLEN register bits
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// For a block data transfer, the value in the data length register must be a multiple of the block
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// size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the
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// data length register before being written to the data control register.
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// For an SDIO multibyte transfer the value in the data length register must be between 1 and 512.
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#define SDIO_DLEN_DATALENGTH (0x01FFFFFF)
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// SDIO_DCTRL register bits
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// Controls the data path state machine (DPSM).
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// After a data write, data cannot be written to this register for three SDIOCLK clock periods
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// plus two PCLK2 clock periods.
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#define SDIO_DCTRL_SDIOEN (1<<11) // the DPSM performs an SD I/O-card-specific operation.
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#define SDIO_DCTRL_RWMODE (1<<10) // 0: Read Wait control stopping SDIO_D2, 1:Read Wait control using SDIO_CK
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#define SDIO_DCTRL_RWSTOP (1<<9) // 0: Read wait in progress if RWSTART bit is set, 1: Enable for read wait stop if RWSTART bit is set
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#define SDIO_DCTRL_RWSTART (1<<8) // read wait operation starts
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#define SDIO_DCTRL_DBLOCKSIZE (0xF<<4) // Define the data block length when the block data transfer mode is selected: 2^N bytes
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#define SDIO_BLOCKSIZE_64 (6<<4)
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#define SDIO_BLOCKSIZE_512 (9<<4)
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#define SDIO_DCTRL_DMAEN (1<<3) // DMA enable
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#define SDIO_DCTRL_DTMODE (1<<2) // Data transfer mode selection: 0: Block data transfer, 1: Stream or SDIO multi-byte data transfer
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#define SDIO_DCTRL_DTDIR (1<<1) // Data transfer direction selection: 0: From controller to card, 1: From card to controller.
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#define SDIO_DIR_TX (0<<1)
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#define SDIO_DIR_RX (1<<1)
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#define SDIO_DCTRL_DTEN (1<<0) // Start data transfer. Depending on the direction bit, DTDIR,
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// the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at
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// the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data
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// transfer but the SDIO_DCTRL must be updated to enable a new data transfer
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// The meaning of the DTMODE bit changes according to the value of the SDIOEN bit:
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// When DTEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled.
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// When DTEN=1 and DTMODE=1, the peripheral enables an SDIO multi-byte transfer.
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// SDIO_STA register bits
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#define SDIO_STA_CEATAEND (1<<23) // CE-ATA command completion signal received for CMD61
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#define SDIO_STA_SDIOIT (1<<22) // SDIO interrupt received
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#define SDIO_STA_RXDAVL (1<<21) // Data available in receive FIFO
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#define SDIO_STA_TXDAVL (1<<20) // Data available in transmit FIFO
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#define SDIO_STA_RXFIFOE (1<<19) // Receive FIFO empty
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#define SDIO_STA_TXFIFOE (1<<18) // Transmit FIFO empty (2 words)
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#define SDIO_STA_RXFIFOF (1<<17) // Receive FIFO full (2 words before the FIFO is full.)
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#define SDIO_STA_TXFIFOF (1<<16) // Transmit FIFO full
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#define SDIO_STA_RXFIFOHF (1<<15) // Receive FIFO half full: there are at least 8 words in the FIFO
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#define SDIO_STA_TXFIFOHE (1<<14) // Transmit FIFO half empty: at least 8 words can be written into the FIFO
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#define SDIO_STA_RXACT (1<<13) // Data receive in progress
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#define SDIO_STA_TXACT (1<<12) // Data transmit in progress
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#define SDIO_STA_CMDACT (1<<11) // Command transfer in progress
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#define SDIO_STA_DBCKEND (1<<10) // Data block sent/received (CRC check passed)
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#define SDIO_STA_STBITERR (1<<9) // Start bit not detected on all data signals in wide bus mode
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#define SDIO_STA_DATAEND (1<<8) // Data end (data counter SDIOCOUNT is zero)
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#define SDIO_STA_CMDSENT (1<<7) // Command sent (no response required)
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#define SDIO_STA_CMDREND (1<<6) // Command response received (CRC check passed)
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#define SDIO_STA_RXOVERR (1<<5) // Received FIFO overrun error
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#define SDIO_STA_TXUNDERR (1<<4) // Transmit FIFO underrun error
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#define SDIO_STA_DTIMEOUT (1<<3) // Data timeout
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#define SDIO_STA_CTIMEOUT (1<<2) // Command response timeout. The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.
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#define SDIO_STA_DCRCFAIL (1<<1) // Data block sent/received (CRC check failed)
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#define SDIO_STA_CCRCFAIL (1<<0) // Command response received (CRC check failed)
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#define SDIO_STA_CMD_ERROR_FLAGS (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)
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#define SDIO_STA_TRX_ERROR_FLAGS (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)
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#define SDIO_STA_TRX_ACT_FLAGS (SDIO_STA_RXACT|SDIO_STA_TXACT)
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// SDIO_ICR register bits (WO - write only)
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#define SDIO_ICR_CEATAENDC (1<<23) // clear CEATAEND flag
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#define SDIO_ICR_SDIOITC (1<<22) // clear SDIOIT flag
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#define SDIO_ICR_DBCKENDC (1<<10) // clear DBCKENDC flag
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#define SDIO_ICR_STBITERRC (1<<9) // clear STBITERRC flag
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#define SDIO_ICR_DATAENDC (1<<8) // clear DATAENDC flag
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#define SDIO_ICR_CMDSENTC (1<<7) // clear CMDSENTC flag
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#define SDIO_ICR_CMDRENDC (1<<6) // clear CMDREND flag
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#define SDIO_ICR_RXOVERRC (1<<5) // clear RXOVERR flag
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#define SDIO_ICR_TXUNDERRC (1<<4) // clear TXUNDERR flag
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#define SDIO_ICR_DTIMEOUTC (1<<3) // clear DTIMEOUT flag
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#define SDIO_ICR_CTIMEOUTC (1<<2) // clear CTIMEOUT flag
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#define SDIO_ICR_DCRCFAILC (1<<1) // clear DCRCFAIL flag
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#define SDIO_ICR_CCRCFAILC (1<<0) // clear CCRCFAIL flag
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#define SDIO_ICR_CMD_FLAGS (SDIO_ICR_CEATAENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CMDSENTC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC)
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#define SDIO_ICR_DATA_FLAGS (SDIO_ICR_DBCKENDC | SDIO_ICR_STBITERRC | SDIO_ICR_DATAENDC | SDIO_ICR_RXOVERRC | SDIO_ICR_TXUNDERRC | SDIO_ICR_DTIMEOUTC | SDIO_ICR_DCRCFAILC)
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// SDIO_MASK register bits
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// Determines which status flags generate an interrupt request by setting the corresponding bit to 1b.
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#define SDIO_MASK_CEATAENDIE (1<<23) // enable CEATAEND interrupt
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#define SDIO_MASK_SDIOITIE (1<<22) // enable SDIOIT interrupt
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#define SDIO_MASK_RXDAVLIE (1<<21) // enable RXDAVL interrupt
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#define SDIO_MASK_TXDAVLIE (1<<20) // enable TXDAVL interrupt
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#define SDIO_MASK_RXFIFOEIE (1<<19) // enable RXFIFOE interrupt
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#define SDIO_MASK_TXFIFOEIE (1<<18) // enable TXFIFOE interrupt
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#define SDIO_MASK_RXFIFOFIE (1<<17) // enable RXFIFOF interrupt
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#define SDIO_MASK_TXFIFOFIE (1<<16) // enable TXFIFOF interrupt
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#define SDIO_MASK_RXFIFOHFIE (1<<15) // enable RXFIFOHF interrupt
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#define SDIO_MASK_TXFIFOHEIE (1<<14) // enable TXFIFOHE interrupt
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#define SDIO_MASK_RXACTIE (1<<13) // enable RXACT interrupt
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#define SDIO_MASK_TXACTIE (1<<12) // enable TXACT interrupt
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#define SDIO_MASK_CMDACTIE (1<<11) // enable CMDACT interrupt
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#define SDIO_MASK_DBCKENDIE (1<<10) // enable DBCKENDC interrupt
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#define SDIO_MASK_STBITERRIE (1<<9) // enable STBITERR interrupt
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#define SDIO_MASK_DATAENDIE (1<<8) // enable DATAENDC interrupt
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#define SDIO_MASK_CMDSENTIE (1<<7) // enable CMDSENTC interrupt
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#define SDIO_MASK_CMDRENDIE (1<<6) // enable CMDREND interrupt
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#define SDIO_MASK_RXOVERRIE (1<<5) // enable RXOVERR interrupt
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#define SDIO_MASK_TXUNDERRIE (1<<4) // enable TXUNDERR interrupt
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#define SDIO_MASK_DTIMEOUTIE (1<<3) // enable DTIMEOUT interrupt
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#define SDIO_MASK_CTIMEOUTIE (1<<2) // enable CTIMEOUT interrupt
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#define SDIO_MASK_DCRCFAILIE (1<<1) // enable DCRCFAIL interrupt
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#define SDIO_MASK_CCRCFAILIE (1<<0) // enable CCRCFAIL interrupt
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void sdio_enable(void);
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void sdio_disable(void);
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void sdio_begin(void);
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uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg);
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void sdio_set_clock(uint32_t clk);
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void sdio_set_dbus_width(uint16_t bus_w);
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void sdio_set_dblock_size(uint8_t dbsize);
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//void sdio_trx_enable(uint8_t dir);
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inline void sdio_trx_enable(void)
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{
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SDIO->DCTRL |= SDIO_DCTRL_DTEN; // enable data transfer
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}
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inline uint32_t sdio_cmd_xfer_ongoing(void) { return (SDIO->STA&SDIO_STA_CMDACT); }
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inline uint32_t sdio_cmd_complete(void) { return (SDIO->STA&SDIO_STA_CMDSENT); }
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inline void sdio_setup_transfer(uint32_t dtimer, uint32_t dlen, uint16_t flags)
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{
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SDIO->ICR = SDIO_ICR_DATA_FLAGS; // clear data access relevant flags
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SDIO->DTIMER = dtimer;
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SDIO->DLEN = dlen;
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SDIO->DCTRL = flags;// | SDIO_DCTRL_DTEN; // enable data transfer
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}
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#endif /* STM32_HIGH_DENSITY */
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif
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