118 lines
3.6 KiB
C
118 lines
3.6 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file systick.h
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*
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* @brief Various system timer definitions
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*/
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#ifndef _SYSTICK_H_
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#define _SYSTICK_H_
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#include "libmaple_types.h"
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#include "util.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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/** SysTick register map type */
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typedef struct systick_reg_map {
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__IO uint32 CSR; /**< Control and status register */
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__IO uint32 RVR; /**< Reload value register */
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__IO uint32 CNT; /**< Current value register ("count") */
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__IO uint32 CVR; /**< Calibration value register */
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} systick_reg_map;
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/** SysTick register map base pointer */
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#define SYSTICK_BASE ((struct systick_reg_map*)0xE000E010)
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/*
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* Register bit definitions.
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*/
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/* Control and status register */
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#define SYSTICK_CSR_COUNTFLAG BIT(16)
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#define SYSTICK_CSR_CLKSOURCE BIT(2)
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#define SYSTICK_CSR_CLKSOURCE_EXTERNAL 0
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#define SYSTICK_CSR_CLKSOURCE_CORE BIT(2)
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#define SYSTICK_CSR_TICKINT BIT(1)
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#define SYSTICK_CSR_TICKINT_PEND BIT(1)
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#define SYSTICK_CSR_TICKINT_NO_PEND 0
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#define SYSTICK_CSR_ENABLE BIT(0)
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#define SYSTICK_CSR_ENABLE_MULTISHOT BIT(0)
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#define SYSTICK_CSR_ENABLE_DISABLED 0
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/* Calibration value register */
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#define SYSTICK_CVR_NOREF BIT(31)
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#define SYSTICK_CVR_SKEW BIT(30)
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#define SYSTICK_CVR_TENMS 0xFFFFFF
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/** System elapsed time, in milliseconds */
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extern volatile uint32 systick_uptime_millis;
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/**
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* @brief Returns the system uptime, in milliseconds.
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*/
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static inline uint32 systick_uptime(void) {
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return systick_uptime_millis;
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}
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void systick_init(uint32 reload_val);
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void systick_disable();
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void systick_enable();
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/**
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* @brief Returns the current value of the SysTick counter.
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*/
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static inline uint32 systick_get_count(void) {
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return SYSTICK_BASE->CNT;
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}
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/**
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* @brief Check for underflow.
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*
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* This function returns 1 if the SysTick timer has counted to 0 since
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* the last time it was called. However, any reads of any part of the
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* SysTick Control and Status Register SYSTICK_BASE->CSR will
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* interfere with this functionality. See the ARM Cortex M3 Technical
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* Reference Manual for more details (e.g. Table 8-3 in revision r1p1).
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*/
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static inline uint32 systick_check_underflow(void) {
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return SYSTICK_BASE->CSR & SYSTICK_CSR_COUNTFLAG;
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}
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif
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