191 lines
5.4 KiB
C
191 lines
5.4 KiB
C
/* *****************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 LeafLabs LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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* ****************************************************************************/
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#ifndef __HARDWARE_H
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#define __HARDWARE_H
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#include "stm32f10x_type.h"
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#include "cortexm3_macro.h"
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#include "common.h"
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/* macro'd register and peripheral definitions */
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#define RCC ((u32)0x40021000)
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#define FLASH ((u32)0x40022000)
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#define GPIOA ((u32)0x40010800)
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#define GPIOB ((u32)0x40010C00)
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#define GPIOC ((u32)0x40011000)
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#define RCC_CR RCC
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#define RCC_CFGR (RCC + 0x04)
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#define RCC_CIR (RCC + 0x08)
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#define RCC_AHBENR (RCC + 0x14)
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#define RCC_APB2ENR (RCC + 0x18)
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#define RCC_APB1ENR (RCC + 0x1C)
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#define FLASH_ACR (FLASH + 0x00)
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#define FLASH_KEYR (FLASH + 0x04)
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#define FLASH_OPTKEYR (FLASH + 0x08)
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#define FLASH_SR (FLASH + 0x0C)
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#define FLASH_CR (FLASH + 0x10)
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#define FLASH_AR (FLASH + 0x14)
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#define FLASH_OBR (FLASH + 0x1C)
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#define FLASH_WRPR (FLASH + 0x20)
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xCDEF89AB
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#define FLASH_RDPRT 0x00A5
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#define FLASH_SR_BSY 0x01
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#define FLASH_CR_PER 0x02
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#define FLASH_CR_PG 0x01
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#define FLASH_CR_START 0x40
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#define GPIO_CRL(port) port
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#define GPIO_CRH(port) (port+0x04)
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#define GPIO_IDR(port) (port+0x08)
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#define GPIO_ODR(port) (port+0x0c)
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#define GPIO_BSRR(port) (port+0x10)
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#define SCS_BASE ((u32)0xE000E000)
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#define NVIC_BASE (SCS_BASE + 0x0100)
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#define SCB_BASE (SCS_BASE + 0x0D00)
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#define SCS 0xE000E000
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#define NVIC (SCS+0x100)
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#define SCB (SCS+0xD00)
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#define STK (SCS+0x10)
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#define SCB_VTOR (SCB+0x08)
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#define STK_CTRL (STK+0x00)
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#define TIM1_APB2_ENB ((u32)0x00000800)
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#define TIM1 ((u32)0x40012C00)
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#define TIM1_PSC (TIM1+0x28)
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#define TIM1_ARR (TIM1+0x2C)
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#define TIM1_RCR (TIM1+0x30)
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#define TIM1_CR1 (TIM1+0x00)
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#define TIM1_CR2 (TIM1+0x04)
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#define TIM1_DIER (TIM1+0x0C)
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#define TIM1_UP_IRQ_Channel ((u8)0x19)
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#define USB_HP_IRQ ((u8)0x13)
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#define USB_LP_IRQ ((u8)0x14)
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#define TIM2_IRQ ((u8)0x1C)
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/* AIRCR */
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#define AIRCR_RESET 0x05FA0000
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#define AIRCR_RESET_REQ (AIRCR_RESET | (u32)0x04);
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/* temporary copyage of example from kiel */
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#define __VAL(__TIMCLK, __PERIOD) ((__TIMCLK/1000000UL)*__PERIOD)
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#define __PSC(__TIMCLK, __PERIOD) (((__VAL(__TIMCLK, __PERIOD)+49999UL)/50000UL) - 1)
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#define __ARR(__TIMCLK, __PERIOD) ((__VAL(__TIMCLK, __PERIOD)/(__PSC(__TIMCLK, __PERIOD)+1)) - 1)
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#define SET_REG(addr,val) do { *(vu32*)(addr)=val; } while(0)
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#define GET_REG(addr) (*(vu32*)(addr))
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/* todo: there must be some major misunderstanding in how we access
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regs. The direct access approach (GET_REG) causes the usb init to
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fail upon trying to activate RCC_APB1 |= 0x00800000. However, using
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the struct approach from ST, it works fine...temporarily switching
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to that approach */
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typedef struct {
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vu32 CR;
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vu32 CFGR;
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vu32 CIR;
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vu32 APB2RSTR;
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vu32 APB1RSTR;
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vu32 AHBENR;
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vu32 APB2ENR;
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vu32 APB1ENR;
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vu32 BDCR;
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vu32 CSR;
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} RCC_RegStruct;
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#define pRCC ((RCC_RegStruct *) RCC)
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typedef struct {
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vu32 ISER[2];
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u32 RESERVED0[30];
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vu32 ICER[2];
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u32 RSERVED1[30];
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vu32 ISPR[2];
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u32 RESERVED2[30];
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vu32 ICPR[2];
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u32 RESERVED3[30];
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vu32 IABR[2];
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u32 RESERVED4[62];
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vu32 IPR[15];
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} NVIC_TypeDef;
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typedef struct {
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u8 NVIC_IRQChannel;
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u8 NVIC_IRQChannelPreemptionPriority;
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u8 NVIC_IRQChannelSubPriority;
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bool NVIC_IRQChannelCmd; /* TRUE for enable */
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} NVIC_InitTypeDef;
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typedef struct {
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vuc32 CPUID;
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vu32 ICSR;
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vu32 VTOR;
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vu32 AIRCR;
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vu32 SCR;
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vu32 CCR;
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vu32 SHPR[3];
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vu32 SHCSR;
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vu32 CFSR;
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vu32 HFSR;
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vu32 DFSR;
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vu32 MMFAR;
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vu32 BFAR;
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vu32 AFSR;
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} SCB_TypeDef;
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void setPin(u32 bank, u8 pin);
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void resetPin(u32 bank, u8 pin);
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bool readPin(u32 bank, u8 pin);
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void strobePin(u32 bank, u8 pin, u8 count, u32 rate);
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void systemHardReset(void);
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void systemReset(void);
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void setupCLK(void);
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void setupLED(void);
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void setupFLASH(void);
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void setupBUTTON(void);
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bool checkUserCode(u32 usrAddr);
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void jumpToUser(u32 usrAddr);
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bool flashWriteWord(u32 addr, u32 word);
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bool flashErasePage(u32 addr);
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bool flashErasePages(u32 addr, u16 n);
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void flashLock(void);
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void flashUnlock(void);
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void nvicInit(NVIC_InitTypeDef *);
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void nvicDisableInterrupts(void);
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#endif
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