412 lines
14 KiB
C++
412 lines
14 KiB
C++
/* Arduino SdSpi Library
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* Copyright (C) 2013 by William Greiman
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*
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* This file is part of the Arduino SdSpi Library
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*
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* This Library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This Library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Arduino SdSpi Library. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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#include "ILI_SdSpi.h"
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#if ILI_USE_NATIVE_SAM3X_SPI
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/** Use SAM3X DMAC if nonzero */
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#define ILI_USE_SAM3X_DMAC 1
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/** Use extra Bus Matrix arbitration fix if nonzero */
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#define ILI_USE_SAM3X_BUS_MATRIX_FIX 0
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/** Time in ms for DMA receive timeout */
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#define ILI_SAM3X_DMA_TIMEOUT 100
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/** chip select register number */
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#define ILI_SPI_CHIP_SEL 3
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/** DMAC receive channel */
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#define ILI_SPI_DMAC_RX_CH 1
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/** DMAC transmit channel */
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#define ILI_SPI_DMAC_TX_CH 0
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/** DMAC Channel HW Interface Number for SPI TX. */
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#define ILI_SPI_TX_IDX 1
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/** DMAC Channel HW Interface Number for SPI RX. */
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#define ILI_SPI_RX_IDX 2
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//------------------------------------------------------------------------------
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/** Disable DMA Controller. */
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static void ILI_dmac_disable() {
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DMAC->DMAC_EN &= (~DMAC_EN_ENABLE);
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}
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/** Enable DMA Controller. */
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static void ILI_dmac_enable() {
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DMAC->DMAC_EN = DMAC_EN_ENABLE;
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}
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/** Disable DMA Channel. */
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static void ILI_dmac_channel_disable(uint32_t ul_num) {
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DMAC->DMAC_CHDR = DMAC_CHDR_DIS0 << ul_num;
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}
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/** Enable DMA Channel. */
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static void ILI_dmac_channel_enable(uint32_t ul_num) {
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DMAC->DMAC_CHER = DMAC_CHER_ENA0 << ul_num;
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}
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/** Poll for transfer complete. */
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static bool ILI_dmac_channel_transfer_done(uint32_t ul_num) {
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return (DMAC->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) ? false : true;
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}
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//------------------------------------------------------------------------------
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void ILI_SdSpi::begin() {
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PIO_Configure(
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g_APinDescription[PIN_SPI_MOSI].pPort,
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g_APinDescription[PIN_SPI_MOSI].ulPinType,
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g_APinDescription[PIN_SPI_MOSI].ulPin,
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g_APinDescription[PIN_SPI_MOSI].ulPinConfiguration);
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PIO_Configure(
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g_APinDescription[PIN_SPI_MISO].pPort,
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g_APinDescription[PIN_SPI_MISO].ulPinType,
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g_APinDescription[PIN_SPI_MISO].ulPin,
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g_APinDescription[PIN_SPI_MISO].ulPinConfiguration);
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PIO_Configure(
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g_APinDescription[PIN_SPI_SCK].pPort,
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g_APinDescription[PIN_SPI_SCK].ulPinType,
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g_APinDescription[PIN_SPI_SCK].ulPin,
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g_APinDescription[PIN_SPI_SCK].ulPinConfiguration);
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pmc_enable_periph_clk(ID_SPI0);
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#if ILI_USE_SAM3X_DMAC
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pmc_enable_periph_clk(ID_DMAC);
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ILI_dmac_disable();
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DMAC->DMAC_GCFG = DMAC_GCFG_ARB_CFG_FIXED;
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ILI_dmac_enable();
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#if ILI_USE_SAM3X_BUS_MATRIX_FIX
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MATRIX->MATRIX_WPMR = 0x4d415400;
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MATRIX->MATRIX_MCFG[1] = 1;
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MATRIX->MATRIX_MCFG[2] = 1;
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MATRIX->MATRIX_SCFG[0] = 0x01000010;
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MATRIX->MATRIX_SCFG[1] = 0x01000010;
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MATRIX->MATRIX_SCFG[7] = 0x01000010;
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#endif // ILI_USE_SAM3X_BUS_MATRIX_FIX
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#endif // ILI_USE_SAM3X_DMAC
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}
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//------------------------------------------------------------------------------
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// start RX DMA
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static void ILI_spiDmaRX(uint8_t* dst, uint16_t count) {
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ILI_dmac_channel_disable(ILI_SPI_DMAC_RX_CH);
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_SADDR = (uint32_t)&SPI0->SPI_RDR;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_DADDR = (uint32_t)dst;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_DSCR = 0;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_CTRLA = count |
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DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
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DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
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DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_CFG = DMAC_CFG_SRC_PER(ILI_SPI_RX_IDX) |
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DMAC_CFG_SRC_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ASAP_CFG;
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ILI_dmac_channel_enable(ILI_SPI_DMAC_RX_CH);
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}
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//------------------------------------------------------------------------------
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// start TX DMA
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static void ILI_spiDmaTX(const uint8_t* src, uint16_t count) {
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static uint8_t ff = 0XFF;
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uint32_t src_incr = DMAC_CTRLB_SRC_INCR_INCREMENTING;
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if (!src) {
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src = &ff;
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src_incr = DMAC_CTRLB_SRC_INCR_FIXED;
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}
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ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_SADDR = (uint32_t)src;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_DADDR = (uint32_t)&SPI0->SPI_TDR;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_DSCR = 0;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_CTRLA = count |
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DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
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DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
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src_incr | DMAC_CTRLB_DST_INCR_FIXED;
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DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_CFG = DMAC_CFG_DST_PER(ILI_SPI_TX_IDX) |
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DMAC_CFG_DST_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
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ILI_dmac_channel_enable(ILI_SPI_DMAC_TX_CH);
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}
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//------------------------------------------------------------------------------
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// initialize SPI controller
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void ILI_SdSpi::init(uint8_t sckDivisor) {
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uint8_t scbr = sckDivisor;
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Spi* pSpi = SPI0;
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// disable SPI
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pSpi->SPI_CR = SPI_CR_SPIDIS;
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// reset SPI
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pSpi->SPI_CR = SPI_CR_SWRST;
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// no mode fault detection, set master mode
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pSpi->SPI_MR = SPI_PCS(ILI_SPI_CHIP_SEL) | SPI_MR_MODFDIS | SPI_MR_MSTR;
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// mode 0, 8-bit,
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pSpi->SPI_CSR[ILI_SPI_CHIP_SEL] = SPI_CSR_SCBR(scbr) | SPI_CSR_NCPHA;
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// enable SPI
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pSpi->SPI_CR |= SPI_CR_SPIEN;
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}
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//------------------------------------------------------------------------------
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static inline uint8_t ILI_spiTransfer(uint8_t b) {
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Spi* pSpi = SPI0;
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pSpi->SPI_TDR = b;
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while ((pSpi->SPI_SR & SPI_SR_RDRF) == 0) {}
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b = pSpi->SPI_RDR;
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return b;
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}
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//------------------------------------------------------------------------------
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/** SPI receive a byte */
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uint8_t ILI_SdSpi::receive() {
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return ILI_spiTransfer(0XFF);
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}
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//------------------------------------------------------------------------------
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/** SPI receive multiple bytes */
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uint8_t ILI_SdSpi::receive(uint8_t* buf, size_t n) {
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Spi* pSpi = SPI0;
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int rtn = 0;
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#if ILI_USE_SAM3X_DMAC
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// clear overrun error
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uint32_t s = pSpi->SPI_SR;
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ILI_spiDmaRX(buf, n);
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ILI_spiDmaTX(0, n);
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uint32_t m = millis();
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while (!ILI_dmac_channel_transfer_done(ILI_SPI_DMAC_RX_CH)) {
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if ((millis() - m) > ILI_SAM3X_DMA_TIMEOUT) {
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ILI_dmac_channel_disable(ILI_SPI_DMAC_RX_CH);
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ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
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rtn = 2;
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break;
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}
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}
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if (pSpi->SPI_SR & SPI_SR_OVRES) rtn |= 1;
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#else // ILI_USE_SAM3X_DMAC
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for (size_t i = 0; i < n; i++) {
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pSpi->SPI_TDR = 0XFF;
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while ((pSpi->SPI_SR & SPI_SR_RDRF) == 0) {}
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buf[i] = pSpi->SPI_RDR;
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}
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#endif // ILI_USE_SAM3X_DMAC
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return rtn;
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}
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//------------------------------------------------------------------------------
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/** SPI send a byte */
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void ILI_SdSpi::send(uint8_t b) {
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ILI_spiTransfer(b);
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}
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//------------------------------------------------------------------------------
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void ILI_SdSpi::send(const uint8_t* buf , size_t n) {
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Spi* pSpi = SPI0;
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#if ILI_USE_SAM3X_DMAC
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ILI_spiDmaTX(buf, n);
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while (!ILI_dmac_channel_transfer_done(ILI_SPI_DMAC_TX_CH)) {}
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#else // #if ILI_USE_SAM3X_DMAC
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while ((pSpi->SPI_SR & SPI_SR_TXEMPTY) == 0) {}
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for (size_t i = 0; i < n; i++) {
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pSpi->SPI_TDR = buf[i];
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while ((pSpi->SPI_SR & SPI_SR_TDRE) == 0) {}
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}
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#endif // #if ILI_USE_SAM3X_DMAC
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while ((pSpi->SPI_SR & SPI_SR_TXEMPTY) == 0) {}
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// leave RDR empty
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uint8_t b = pSpi->SPI_RDR;
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}
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#endif // ILI_USE_NATIVE_SAM3X_SPI
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//*********************************************************
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// STM32F1 section
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//*********************************************************
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#if ILI_USE_NATIVE_STM32F1_SPI
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#include <SPI.h>
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#include <libmaple/dma.h>
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/** Use SAM3X DMAC if nonzero */
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#define ILI_USE_STM32F1_DMAC 1
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/** Time in ms for DMA receive timeout */
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#define ILI_STM32F1_DMA_TIMEOUT 100
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/** chip select register number */
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#define ILI_SPI_CHIP_SEL 3
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/** DMAC receive channel */
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#define ILI_SPI_DMAC_RX_CH DMA_CH2
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/** DMAC transmit channel */
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#define ILI_SPI_DMAC_TX_CH DMA_CH3
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/** DMAC Channel HW Interface Number for SPI TX. */
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#define ILI_SPI_TX_IDX 1
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/** DMAC Channel HW Interface Number for SPI RX. */
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#define ILI_SPI_RX_IDX 2
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volatile bool SPI_DMA_TX_Active = false;
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volatile bool SPI_DMA_RX_Active = false;
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inline void SPI_DMA_TX_Event() {
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SPI_DMA_TX_Active = false;
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dma_disable(DMA1, DMA_CH3);
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}
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inline void SPI_DMA_RX_Event() {
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SPI_DMA_RX_Active = false;
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dma_disable(DMA1, DMA_CH2);
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}
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//------------------------------------------------------------------------------
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/** Disable DMA Controller. */
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//static void ILI_dmac_disable() {
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// DMAC->DMAC_EN &= (~DMAC_EN_ENABLE);
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//}
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/** Enable DMA Controller. */
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//static void ILI_dmac_enable() {
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// DMAC->DMAC_EN = DMAC_EN_ENABLE;
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//}
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/** Disable DMA Channel. */
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static void ILI_dmac_channel_disable(dma_channel ul_num) {
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dma_disable(DMA1, ul_num);
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}
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/** Enable DMA Channel. */
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static void ILI_dmac_channel_enable(dma_channel ul_num) {
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dma_enable(DMA1, ul_num);
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}
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/** Poll for transfer complete. */
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//static bool ILI_dmac_channel_transfer_done(dma_tube tube) {
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// uint8 shift = (tube - 1) * 4;
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// return ((DMA1->regs->ISR >> shift) & 0x02) ? false : true;
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// return (DMAC->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) ? false : true;
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//}
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//------------------------------------------------------------------------------
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void ILI_SdSpi::begin() {
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SPI.begin();
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SPI.setClockDivider(SPI_CLOCK_DIV2);
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SPI.setBitOrder(MSBFIRST);
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SPI.setDataMode(SPI_MODE0);
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// DMA setup stuff. We use a line buffer and usa DMA for filling lines and blocks.
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#if ILI_USE_STM32F1_DMAC
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dma_init(DMA1);
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dma_attach_interrupt(DMA1, DMA_CH3, SPI_DMA_TX_Event);
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dma_attach_interrupt(DMA1, DMA_CH2, SPI_DMA_RX_Event);
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spi_tx_dma_enable(SPI1);
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spi_rx_dma_enable(SPI1);
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#endif // ILI_USE_STM32F1_DMAC
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}
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//------------------------------------------------------------------------------
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// start RX DMA
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static void ILI_spiDmaRX(uint8_t* dst, uint16_t count) {
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// spi_rx_dma_enable(SPI1);
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if (count < 1) return;
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dma_setup_transfer(DMA1, DMA_CH2, &SPI1->regs->DR, DMA_SIZE_8BITS,
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dst, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));
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dma_set_num_transfers(DMA1, DMA_CH2, count); // 2 bytes per pixel
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SPI_DMA_RX_Active = true;
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dma_enable(DMA1, DMA_CH2);
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}
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//------------------------------------------------------------------------------
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// start TX DMA
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static void ILI_spiDmaTX(uint8_t* src, uint16_t count) {
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if (count < 1) return;
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static uint8_t ff = 0XFF;
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// spi_tx_dma_enable(SPI1);
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// dma_init(DMA1);
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// dma_attach_interrupt(DMA1, DMA_CH3, SPI_DMA_TX_Event);
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if (!src) {
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src = &ff;
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dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
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src, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));
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}
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else {
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dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
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src, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT));
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}
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dma_set_num_transfers(DMA1, DMA_CH3, count); // 2 bytes per pixel
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SPI_DMA_TX_Active = true;
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dma_enable(DMA1, DMA_CH3);
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}
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//------------------------------------------------------------------------------
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// initialize SPI controller STM32F1
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void ILI_SdSpi::init(uint8_t sckDivisor) {
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SPI.setClockDivider(sckDivisor);
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SPI.setBitOrder(MSBFIRST);
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SPI.setDataMode(SPI_MODE0);
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spi_tx_dma_enable(SPI1);
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spi_rx_dma_enable(SPI1);
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}
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//------------------------------------------------------------------------------
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// STM32
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static inline uint8_t ILI_spiTransfer(uint8_t b) {
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return SPI.transfer(b);
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}
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//------------------------------------------------------------------------------
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// should be valid for STM32
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/** SPI receive a byte */
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uint8_t ILI_SdSpi::receive() {
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return ILI_spiTransfer(0xFF);
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}
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//------------------------------------------------------------------------------
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/** SPI receive multiple bytes */
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// check and finish.
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uint8_t ILI_SdSpi::receive(uint8_t* buf, size_t n) {
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int rtn = 0;
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#if ILI_USE_STM32F1_DMAC
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// clear overrun error
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// uint32_t s = pSpi->SPI_SR;
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ILI_spiDmaRX(buf, n);
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ILI_spiDmaTX(0, n);
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uint32_t m = millis();
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while (SPI_DMA_RX_Active) {
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if ((millis() - m) > ILI_STM32F1_DMA_TIMEOUT) {
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ILI_dmac_channel_disable(ILI_SPI_DMAC_RX_CH);
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ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
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rtn = 2;
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break;
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}
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}
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// if (pSpi->SPI_SR & SPI_SR_OVRES) rtn |= 1;
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#else // ILI_USE_STM32F1_DMAC
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for (size_t i = 0; i < n; i++) {
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buf[i] = SPI.transfer (0xFF);
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}
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#endif // ILI_USE_STM32F1_DMAC
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return rtn;
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}
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//------------------------------------------------------------------------------
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/** SPI send a byte */
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void ILI_SdSpi::send(uint8_t b) {
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ILI_spiTransfer(b);
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}
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//------------------------------------------------------------------------------
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void ILI_SdSpi::send(uint8_t* buf , size_t n) {
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#if ILI_USE_STM32F1_DMAC
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ILI_spiDmaTX(buf, n);
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while (SPI_DMA_TX_Active) {}
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// uint32_t m = millis();
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// while (SPI_DMA_TX_Active) {
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// if ((millis() - m) > ILI_STM32F1_DMA_TIMEOUT) {
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// ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
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// break;
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// }
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// }
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#else // #if ILI_USE_STM32F1_DMAC
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SPI.write (buf, n)
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#endif // #if ILI_USE_STM32F1_DMAC
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// leave RDR empty
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// uint8_t b = pSpi->SPI_RDR;
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}
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#endif // ILI_USE_NATIVE_STM32F1_SPI
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