579 lines
23 KiB
C
579 lines
23 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Michael Hope.
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* Copyright (c) 2012 LeafLabs, LLC
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file libmaple/stm32f1/include/series/dma.h
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* @author Marti Bolivar <mbolivar@leaflabs.com>;
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* Original implementation by Michael Hope
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* @brief STM32F1 DMA series header.
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*/
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/*
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* See /notes/dma-stm32f1.txt for more information.
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*/
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#ifndef _LIBMAPLE_STM32F1_DMA_H_
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#define _LIBMAPLE_STM32F1_DMA_H_
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#ifdef __cplusplus
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extern "C"{
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#endif
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#include <libmaple/libmaple_types.h>
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#include <libmaple/dma_common.h>
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/*
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* Register maps and base pointers
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*/
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/**
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* @brief STM32F1 DMA register map type.
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*
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* Note that DMA controller 2 (register map base pointer DMA2_BASE)
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* only supports channels 1--5.
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*/
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typedef struct dma_reg_map {
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__IO uint32 ISR; /**< Interrupt status register */
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__IO uint32 IFCR; /**< Interrupt flag clear register */
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__IO uint32 CCR1; /**< Channel 1 configuration register */
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__IO uint32 CNDTR1; /**< Channel 1 number of data register */
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__IO uint32 CPAR1; /**< Channel 1 peripheral address register */
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__IO uint32 CMAR1; /**< Channel 1 memory address register */
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const uint32 RESERVED1; /**< Reserved. */
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__IO uint32 CCR2; /**< Channel 2 configuration register */
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__IO uint32 CNDTR2; /**< Channel 2 number of data register */
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__IO uint32 CPAR2; /**< Channel 2 peripheral address register */
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__IO uint32 CMAR2; /**< Channel 2 memory address register */
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const uint32 RESERVED2; /**< Reserved. */
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__IO uint32 CCR3; /**< Channel 3 configuration register */
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__IO uint32 CNDTR3; /**< Channel 3 number of data register */
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__IO uint32 CPAR3; /**< Channel 3 peripheral address register */
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__IO uint32 CMAR3; /**< Channel 3 memory address register */
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const uint32 RESERVED3; /**< Reserved. */
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__IO uint32 CCR4; /**< Channel 4 configuration register */
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__IO uint32 CNDTR4; /**< Channel 4 number of data register */
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__IO uint32 CPAR4; /**< Channel 4 peripheral address register */
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__IO uint32 CMAR4; /**< Channel 4 memory address register */
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const uint32 RESERVED4; /**< Reserved. */
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__IO uint32 CCR5; /**< Channel 5 configuration register */
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__IO uint32 CNDTR5; /**< Channel 5 number of data register */
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__IO uint32 CPAR5; /**< Channel 5 peripheral address register */
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__IO uint32 CMAR5; /**< Channel 5 memory address register */
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const uint32 RESERVED5; /**< Reserved. */
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__IO uint32 CCR6; /**< Channel 6 configuration register */
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__IO uint32 CNDTR6; /**< Channel 6 number of data register */
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__IO uint32 CPAR6; /**< Channel 6 peripheral address register */
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__IO uint32 CMAR6; /**< Channel 6 memory address register */
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const uint32 RESERVED6; /**< Reserved. */
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__IO uint32 CCR7; /**< Channel 7 configuration register */
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__IO uint32 CNDTR7; /**< Channel 7 number of data register */
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__IO uint32 CPAR7; /**< Channel 7 peripheral address register */
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__IO uint32 CMAR7; /**< Channel 7 memory address register */
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const uint32 RESERVED7; /**< Reserved. */
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} dma_reg_map;
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/** DMA controller 1 register map base pointer */
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#define DMA1_BASE ((struct dma_reg_map*)0x40020000)
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/** DMA controller 2 register map base pointer */
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#define DMA2_BASE ((struct dma_reg_map*)0x40020400)
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/**
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* @brief STM32F1 DMA channel (i.e. tube) register map type.
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* Provides access to an individual channel's registers.
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* @see dma_tube_regs()
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*/
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typedef struct dma_tube_reg_map {
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__IO uint32 CCR; /**< Channel configuration register */
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__IO uint32 CNDTR; /**< Channel number of data register */
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__IO uint32 CPAR; /**< Channel peripheral address register */
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__IO uint32 CMAR; /**< Channel memory address register */
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} dma_tube_reg_map;
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/** DMA1 channel 1 register map base pointer */
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#define DMA1CH1_BASE ((struct dma_tube_reg_map*)0x40020008)
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/** DMA1 channel 2 register map base pointer */
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#define DMA1CH2_BASE ((struct dma_tube_reg_map*)0x4002001C)
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/** DMA1 channel 3 register map base pointer */
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#define DMA1CH3_BASE ((struct dma_tube_reg_map*)0x40020030)
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/** DMA1 channel 4 register map base pointer */
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#define DMA1CH4_BASE ((struct dma_tube_reg_map*)0x40020044)
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/** DMA1 channel 5 register map base pointer */
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#define DMA1CH5_BASE ((struct dma_tube_reg_map*)0x40020058)
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/** DMA1 channel 6 register map base pointer */
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#define DMA1CH6_BASE ((struct dma_tube_reg_map*)0x4002006C)
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/** DMA1 channel 7 register map base pointer */
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#define DMA1CH7_BASE ((struct dma_tube_reg_map*)0x40020080)
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/** DMA2 channel 1 register map base pointer */
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#define DMA2CH1_BASE ((struct dma_tube_reg_map*)0x40020408)
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/** DMA2 channel 2 register map base pointer */
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#define DMA2CH2_BASE ((struct dma_tube_reg_map*)0x4002041C)
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/** DMA2 channel 3 register map base pointer */
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#define DMA2CH3_BASE ((struct dma_tube_reg_map*)0x40020430)
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/** DMA2 channel 4 register map base pointer */
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#define DMA2CH4_BASE ((struct dma_tube_reg_map*)0x40020444)
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/** DMA2 channel 5 register map base pointer */
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#define DMA2CH5_BASE ((struct dma_tube_reg_map*)0x40020458)
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/*
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* Register bit definitions
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*/
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/* Interrupt status register */
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#define DMA_ISR_TEIF_BIT 3
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#define DMA_ISR_HTIF_BIT 2
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#define DMA_ISR_TCIF_BIT 1
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#define DMA_ISR_GIF_BIT 0
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#define DMA_ISR_TEIF (1 << DMA_ISR_TEIF_BIT)
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#define DMA_ISR_HTIF (1 << DMA_ISR_HTIF_BIT)
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#define DMA_ISR_TCIF (1 << DMA_ISR_TCIF_BIT)
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#define DMA_ISR_GIF (1 << DMA_ISR_GIF_BIT)
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#define DMA_ISR_TEIF7_BIT 27
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#define DMA_ISR_HTIF7_BIT 26
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#define DMA_ISR_TCIF7_BIT 25
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#define DMA_ISR_GIF7_BIT 24
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#define DMA_ISR_TEIF6_BIT 23
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#define DMA_ISR_HTIF6_BIT 22
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#define DMA_ISR_TCIF6_BIT 21
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#define DMA_ISR_GIF6_BIT 20
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#define DMA_ISR_TEIF5_BIT 19
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#define DMA_ISR_HTIF5_BIT 18
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#define DMA_ISR_TCIF5_BIT 17
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#define DMA_ISR_GIF5_BIT 16
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#define DMA_ISR_TEIF4_BIT 15
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#define DMA_ISR_HTIF4_BIT 14
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#define DMA_ISR_TCIF4_BIT 13
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#define DMA_ISR_GIF4_BIT 12
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#define DMA_ISR_TEIF3_BIT 11
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#define DMA_ISR_HTIF3_BIT 10
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#define DMA_ISR_TCIF3_BIT 9
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#define DMA_ISR_GIF3_BIT 8
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#define DMA_ISR_TEIF2_BIT 7
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#define DMA_ISR_HTIF2_BIT 6
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#define DMA_ISR_TCIF2_BIT 5
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#define DMA_ISR_GIF2_BIT 4
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#define DMA_ISR_TEIF1_BIT 3
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#define DMA_ISR_HTIF1_BIT 2
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#define DMA_ISR_TCIF1_BIT 1
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#define DMA_ISR_GIF1_BIT 0
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#define DMA_ISR_TEIF7 (1U << DMA_ISR_TEIF7_BIT)
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#define DMA_ISR_HTIF7 (1U << DMA_ISR_HTIF7_BIT)
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#define DMA_ISR_TCIF7 (1U << DMA_ISR_TCIF7_BIT)
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#define DMA_ISR_GIF7 (1U << DMA_ISR_GIF7_BIT)
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#define DMA_ISR_TEIF6 (1U << DMA_ISR_TEIF6_BIT)
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#define DMA_ISR_HTIF6 (1U << DMA_ISR_HTIF6_BIT)
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#define DMA_ISR_TCIF6 (1U << DMA_ISR_TCIF6_BIT)
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#define DMA_ISR_GIF6 (1U << DMA_ISR_GIF6_BIT)
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#define DMA_ISR_TEIF5 (1U << DMA_ISR_TEIF5_BIT)
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#define DMA_ISR_HTIF5 (1U << DMA_ISR_HTIF5_BIT)
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#define DMA_ISR_TCIF5 (1U << DMA_ISR_TCIF5_BIT)
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#define DMA_ISR_GIF5 (1U << DMA_ISR_GIF5_BIT)
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#define DMA_ISR_TEIF4 (1U << DMA_ISR_TEIF4_BIT)
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#define DMA_ISR_HTIF4 (1U << DMA_ISR_HTIF4_BIT)
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#define DMA_ISR_TCIF4 (1U << DMA_ISR_TCIF4_BIT)
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#define DMA_ISR_GIF4 (1U << DMA_ISR_GIF4_BIT)
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#define DMA_ISR_TEIF3 (1U << DMA_ISR_TEIF3_BIT)
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#define DMA_ISR_HTIF3 (1U << DMA_ISR_HTIF3_BIT)
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#define DMA_ISR_TCIF3 (1U << DMA_ISR_TCIF3_BIT)
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#define DMA_ISR_GIF3 (1U << DMA_ISR_GIF3_BIT)
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#define DMA_ISR_TEIF2 (1U << DMA_ISR_TEIF2_BIT)
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#define DMA_ISR_HTIF2 (1U << DMA_ISR_HTIF2_BIT)
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#define DMA_ISR_TCIF2 (1U << DMA_ISR_TCIF2_BIT)
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#define DMA_ISR_GIF2 (1U << DMA_ISR_GIF2_BIT)
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#define DMA_ISR_TEIF1 (1U << DMA_ISR_TEIF1_BIT)
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#define DMA_ISR_HTIF1 (1U << DMA_ISR_HTIF1_BIT)
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#define DMA_ISR_TCIF1 (1U << DMA_ISR_TCIF1_BIT)
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#define DMA_ISR_GIF1 (1U << DMA_ISR_GIF1_BIT)
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/* Interrupt flag clear register */
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#define DMA_IFCR_CTEIF7_BIT 27
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#define DMA_IFCR_CHTIF7_BIT 26
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#define DMA_IFCR_CTCIF7_BIT 25
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#define DMA_IFCR_CGIF7_BIT 24
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#define DMA_IFCR_CTEIF6_BIT 23
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#define DMA_IFCR_CHTIF6_BIT 22
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#define DMA_IFCR_CTCIF6_BIT 21
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#define DMA_IFCR_CGIF6_BIT 20
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#define DMA_IFCR_CTEIF5_BIT 19
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#define DMA_IFCR_CHTIF5_BIT 18
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#define DMA_IFCR_CTCIF5_BIT 17
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#define DMA_IFCR_CGIF5_BIT 16
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#define DMA_IFCR_CTEIF4_BIT 15
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#define DMA_IFCR_CHTIF4_BIT 14
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#define DMA_IFCR_CTCIF4_BIT 13
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#define DMA_IFCR_CGIF4_BIT 12
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#define DMA_IFCR_CTEIF3_BIT 11
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#define DMA_IFCR_CHTIF3_BIT 10
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#define DMA_IFCR_CTCIF3_BIT 9
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#define DMA_IFCR_CGIF3_BIT 8
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#define DMA_IFCR_CTEIF2_BIT 7
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#define DMA_IFCR_CHTIF2_BIT 6
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#define DMA_IFCR_CTCIF2_BIT 5
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#define DMA_IFCR_CGIF2_BIT 4
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#define DMA_IFCR_CTEIF1_BIT 3
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#define DMA_IFCR_CHTIF1_BIT 2
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#define DMA_IFCR_CTCIF1_BIT 1
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#define DMA_IFCR_CGIF1_BIT 0
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#define DMA_IFCR_CTEIF7 (1U << DMA_IFCR_CTEIF7_BIT)
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#define DMA_IFCR_CHTIF7 (1U << DMA_IFCR_CHTIF7_BIT)
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#define DMA_IFCR_CTCIF7 (1U << DMA_IFCR_CTCIF7_BIT)
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#define DMA_IFCR_CGIF7 (1U << DMA_IFCR_CGIF7_BIT)
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#define DMA_IFCR_CTEIF6 (1U << DMA_IFCR_CTEIF6_BIT)
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#define DMA_IFCR_CHTIF6 (1U << DMA_IFCR_CHTIF6_BIT)
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#define DMA_IFCR_CTCIF6 (1U << DMA_IFCR_CTCIF6_BIT)
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#define DMA_IFCR_CGIF6 (1U << DMA_IFCR_CGIF6_BIT)
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#define DMA_IFCR_CTEIF5 (1U << DMA_IFCR_CTEIF5_BIT)
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#define DMA_IFCR_CHTIF5 (1U << DMA_IFCR_CHTIF5_BIT)
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#define DMA_IFCR_CTCIF5 (1U << DMA_IFCR_CTCIF5_BIT)
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#define DMA_IFCR_CGIF5 (1U << DMA_IFCR_CGIF5_BIT)
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#define DMA_IFCR_CTEIF4 (1U << DMA_IFCR_CTEIF4_BIT)
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#define DMA_IFCR_CHTIF4 (1U << DMA_IFCR_CHTIF4_BIT)
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#define DMA_IFCR_CTCIF4 (1U << DMA_IFCR_CTCIF4_BIT)
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#define DMA_IFCR_CGIF4 (1U << DMA_IFCR_CGIF4_BIT)
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#define DMA_IFCR_CTEIF3 (1U << DMA_IFCR_CTEIF3_BIT)
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#define DMA_IFCR_CHTIF3 (1U << DMA_IFCR_CHTIF3_BIT)
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#define DMA_IFCR_CTCIF3 (1U << DMA_IFCR_CTCIF3_BIT)
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#define DMA_IFCR_CGIF3 (1U << DMA_IFCR_CGIF3_BIT)
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#define DMA_IFCR_CTEIF2 (1U << DMA_IFCR_CTEIF2_BIT)
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#define DMA_IFCR_CHTIF2 (1U << DMA_IFCR_CHTIF2_BIT)
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#define DMA_IFCR_CTCIF2 (1U << DMA_IFCR_CTCIF2_BIT)
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#define DMA_IFCR_CGIF2 (1U << DMA_IFCR_CGIF2_BIT)
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#define DMA_IFCR_CTEIF1 (1U << DMA_IFCR_CTEIF1_BIT)
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#define DMA_IFCR_CHTIF1 (1U << DMA_IFCR_CHTIF1_BIT)
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#define DMA_IFCR_CTCIF1 (1U << DMA_IFCR_CTCIF1_BIT)
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#define DMA_IFCR_CGIF1 (1U << DMA_IFCR_CGIF1_BIT)
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/* Channel configuration register */
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#define DMA_CCR_MEM2MEM_BIT 14
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#define DMA_CCR_MINC_BIT 7
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#define DMA_CCR_PINC_BIT 6
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#define DMA_CCR_CIRC_BIT 5
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#define DMA_CCR_DIR_BIT 4
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#define DMA_CCR_TEIE_BIT 3
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#define DMA_CCR_HTIE_BIT 2
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#define DMA_CCR_TCIE_BIT 1
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#define DMA_CCR_EN_BIT 0
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#define DMA_CCR_MEM2MEM (1U << DMA_CCR_MEM2MEM_BIT)
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#define DMA_CCR_PL (0x3 << 12)
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#define DMA_CCR_PL_LOW (0x0 << 12)
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#define DMA_CCR_PL_MEDIUM (0x1 << 12)
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#define DMA_CCR_PL_HIGH (0x2 << 12)
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#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
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#define DMA_CCR_MSIZE (0x3 << 10)
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#define DMA_CCR_MSIZE_8BITS (0x0 << 10)
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#define DMA_CCR_MSIZE_16BITS (0x1 << 10)
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#define DMA_CCR_MSIZE_32BITS (0x2 << 10)
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#define DMA_CCR_PSIZE (0x3 << 8)
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#define DMA_CCR_PSIZE_8BITS (0x0 << 8)
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#define DMA_CCR_PSIZE_16BITS (0x1 << 8)
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#define DMA_CCR_PSIZE_32BITS (0x2 << 8)
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#define DMA_CCR_MINC (1U << DMA_CCR_MINC_BIT)
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#define DMA_CCR_PINC (1U << DMA_CCR_PINC_BIT)
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#define DMA_CCR_CIRC (1U << DMA_CCR_CIRC_BIT)
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#define DMA_CCR_DIR (1U << DMA_CCR_DIR_BIT)
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#define DMA_CCR_DIR_FROM_PER (0U << DMA_CCR_DIR_BIT)
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#define DMA_CCR_DIR_FROM_MEM (1U << DMA_CCR_DIR_BIT)
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#define DMA_CCR_TEIE (1U << DMA_CCR_TEIE_BIT)
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#define DMA_CCR_HTIE (1U << DMA_CCR_HTIE_BIT)
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#define DMA_CCR_TCIE (1U << DMA_CCR_TCIE_BIT)
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#define DMA_CCR_EN (1U << DMA_CCR_EN_BIT)
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/*
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* Devices
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*/
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extern dma_dev *DMA1;
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#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
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extern dma_dev *DMA2;
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#endif
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/*
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* Other types needed by, or useful for, <libmaple/dma.h>.
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*/
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/**
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* @brief STM32F1 dma_tube.
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* On STM32F1, DMA tubes are just channels.
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*/
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#define dma_tube dma_channel
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/**
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* @brief On STM32F1, dma_channel_reg_map is an alias for dma_tube_reg_map.
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* This is for backwards compatibility. */
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#define dma_channel_reg_map dma_tube_reg_map
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/**
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* @brief STM32F1 configuration flags for dma_tube_config
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* @see struct dma_tube_config
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*/
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typedef enum dma_cfg_flags {
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/**
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* Source address increment mode
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*
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* If this flag is set, the source address is incremented (by the
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* source size) after each DMA transfer.
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*/
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DMA_CFG_SRC_INC = 1U << 31,
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/**
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* Destination address increment mode
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*
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* If this flag is set, the destination address is incremented (by
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* the destination size) after each DMA transfer.
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*/
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DMA_CFG_DST_INC = 1U << 30,
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/**
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* Circular mode
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*
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* This mode is not available for memory-to-memory transfers.
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*/
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DMA_CFG_CIRC = DMA_CCR_CIRC,
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/** Transfer complete interrupt enable */
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DMA_CFG_CMPLT_IE = DMA_CCR_TCIE,
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/** Transfer half-complete interrupt enable */
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DMA_CFG_HALF_CMPLT_IE = DMA_CCR_HTIE,
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/** Transfer error interrupt enable */
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DMA_CFG_ERR_IE = DMA_CCR_TEIE,
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} dma_cfg_flags;
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/**
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* @brief STM32F1 DMA request sources.
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*
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* IMPORTANT:
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*
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* 1. On STM32F1, each dma_request_src can only be used by a
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* particular tube on a particular DMA controller. For example,
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* DMA_REQ_SRC_ADC1 belongs to DMA1, tube 1. DMA2 cannot serve
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* requests from ADC1, nor can DMA1 tube 2, etc. If you try to use a
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* request source with the wrong DMA controller or tube on STM32F1,
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* dma_tube_cfg() will fail.
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*
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* 2. In general, a DMA tube can only serve a single request source at
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* a time, and on STM32F1, Terrible Super-Bad Things will happen if
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* two request sources are active for a single tube.
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*
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* To make all this easier to sort out, these dma_request_src
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* enumerators are grouped by DMA controller and tube.
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*
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* @see struct dma_tube_config
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* @see dma_tube_cfg()
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*/
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typedef enum dma_request_src {
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/* Each request source encodes the DMA controller and channel it
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* belongs to, for error checking in dma_tube_cfg(). */
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/* DMA1 request sources */
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/**@{*/
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/** (DMA1, tube 1) */
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DMA_REQ_SRC_ADC1 = (RCC_DMA1 << 3) | 1,
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DMA_REQ_SRC_TIM2_CH3 = (RCC_DMA1 << 3) | 1,
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DMA_REQ_SRC_TIM4_CH1 = (RCC_DMA1 << 3) | 1,
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/**@}*/
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/**@{*/
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/** (DMA1, tube 2)*/
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DMA_REQ_SRC_SPI1_RX = (RCC_DMA1 << 3) | 2,
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DMA_REQ_SRC_USART3_TX = (RCC_DMA1 << 3) | 2,
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DMA_REQ_SRC_TIM1_CH1 = (RCC_DMA1 << 3) | 2,
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DMA_REQ_SRC_TIM2_UP = (RCC_DMA1 << 3) | 2,
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DMA_REQ_SRC_TIM3_CH3 = (RCC_DMA1 << 3) | 2,
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/**@}*/
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/**@{*/
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/** (DMA1, tube 3)*/
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DMA_REQ_SRC_SPI1_TX = (RCC_DMA1 << 3) | 3,
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DMA_REQ_SRC_USART3_RX = (RCC_DMA1 << 3) | 3,
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DMA_REQ_SRC_TIM1_CH2 = (RCC_DMA1 << 3) | 3,
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DMA_REQ_SRC_TIM3_CH4 = (RCC_DMA1 << 3) | 3,
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DMA_REQ_SRC_TIM3_UP = (RCC_DMA1 << 3) | 3,
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/**@}*/
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/**@{*/
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/** (DMA1, tube 4)*/
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DMA_REQ_SRC_SPI2_RX = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_I2S2_RX = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_USART1_TX = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_I2C2_TX = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_TIM1_CH4 = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_TIM1_TRIG = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_TIM1_COM = (RCC_DMA1 << 3) | 4,
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DMA_REQ_SRC_TIM4_CH2 = (RCC_DMA1 << 3) | 4,
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/**@}*/
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/**@{*/
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/** (DMA1, tube 5)*/
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DMA_REQ_SRC_SPI2_TX = (RCC_DMA1 << 3) | 5,
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DMA_REQ_SRC_I2S2_TX = (RCC_DMA1 << 3) | 5,
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DMA_REQ_SRC_USART1_RX = (RCC_DMA1 << 3) | 5,
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DMA_REQ_SRC_I2C2_RX = (RCC_DMA1 << 3) | 5,
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DMA_REQ_SRC_TIM1_UP = (RCC_DMA1 << 3) | 5,
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DMA_REQ_SRC_TIM2_CH1 = (RCC_DMA1 << 3) | 5,
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DMA_REQ_SRC_TIM4_CH3 = (RCC_DMA1 << 3) | 5,
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/**@}*/
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/**@{*/
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/** (DMA1, tube 6)*/
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DMA_REQ_SRC_USART2_RX = (RCC_DMA1 << 3) | 6,
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DMA_REQ_SRC_I2C1_TX = (RCC_DMA1 << 3) | 6,
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DMA_REQ_SRC_TIM1_CH3 = (RCC_DMA1 << 3) | 6,
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DMA_REQ_SRC_TIM3_CH1 = (RCC_DMA1 << 3) | 6,
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DMA_REQ_SRC_TIM3_TRIG = (RCC_DMA1 << 3) | 6,
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/**@}*/
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/**@{*/
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/* Tube 7 */
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DMA_REQ_SRC_USART2_TX = (RCC_DMA1 << 3) | 7,
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DMA_REQ_SRC_I2C1_RX = (RCC_DMA1 << 3) | 7,
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DMA_REQ_SRC_TIM2_CH2 = (RCC_DMA1 << 3) | 7,
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DMA_REQ_SRC_TIM2_CH4 = (RCC_DMA1 << 3) | 7,
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DMA_REQ_SRC_TIM4_UP = (RCC_DMA1 << 3) | 7,
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/**@}*/
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/* DMA2 request sources */
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/**@{*/
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/** (DMA2, tube 1)*/
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DMA_REQ_SRC_SPI3_RX = (RCC_DMA2 << 3) | 1,
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DMA_REQ_SRC_I2S3_RX = (RCC_DMA2 << 3) | 1,
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DMA_REQ_SRC_TIM5_CH4 = (RCC_DMA2 << 3) | 1,
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DMA_REQ_SRC_TIM5_TRIG = (RCC_DMA2 << 3) | 1,
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/**@}*/
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/**@{*/
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/** (DMA2, tube 2)*/
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DMA_REQ_SRC_SPI3_TX = (RCC_DMA2 << 3) | 2,
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DMA_REQ_SRC_I2S3_TX = (RCC_DMA2 << 3) | 2,
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DMA_REQ_SRC_TIM5_CH3 = (RCC_DMA2 << 3) | 2,
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DMA_REQ_SRC_TIM5_UP = (RCC_DMA2 << 3) | 2,
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/**@}*/
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/**@{*/
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/** (DMA2, tube 3)*/
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DMA_REQ_SRC_UART4_RX = (RCC_DMA2 << 3) | 3,
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DMA_REQ_SRC_TIM6_UP = (RCC_DMA2 << 3) | 3,
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DMA_REQ_SRC_DAC_CH1 = (RCC_DMA2 << 3) | 3,
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/**@}*/
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/**@{*/
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/** (DMA2, tube 4)*/
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DMA_REQ_SRC_SDIO = (RCC_DMA2 << 3) | 4,
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DMA_REQ_SRC_TIM5_CH2 = (RCC_DMA2 << 3) | 4,
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/**@}*/
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/**@{*/
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/** (DMA2, tube 5)*/
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DMA_REQ_SRC_ADC3 = (RCC_DMA2 << 3) | 5,
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DMA_REQ_SRC_UART4_TX = (RCC_DMA2 << 3) | 5,
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DMA_REQ_SRC_TIM5_CH1 = (RCC_DMA2 << 3) | 5,
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/**@}*/
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} dma_request_src;
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|
|
/*
|
|
* Convenience routines.
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*/
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|
|
/**
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* @brief On STM32F1, dma_is_channel_enabled() is an alias for
|
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* dma_is_enabled().
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* This is for backwards compatibility.
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*/
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|
#define dma_is_channel_enabled dma_is_enabled
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|
|
#define DMA_CHANNEL_NREGS 5 /* accounts for reserved word */
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static inline dma_tube_reg_map* dma_tube_regs(dma_dev *dev, dma_tube tube) {
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__IO uint32 *ccr1 = &dev->regs->CCR1;
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return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (tube - 1));
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}
|
|
|
|
/**
|
|
* @brief On STM32F1, dma_channel_regs() is an alias for dma_tube_regs().
|
|
* This is for backwards compatibility. */
|
|
#define dma_channel_regs(dev, ch) dma_tube_regs(dev, ch)
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|
|
static inline uint8 dma_is_enabled(dma_dev *dev, dma_tube tube) {
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|
return (uint8)(dma_tube_regs(dev, tube)->CCR & DMA_CCR_EN);
|
|
}
|
|
|
|
static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_tube tube) {
|
|
uint8 shift = (tube - 1) * 4;
|
|
return (dev->regs->ISR >> shift) & 0xF;
|
|
}
|
|
|
|
static inline void dma_clear_isr_bits(dma_dev *dev, dma_tube tube) {
|
|
dev->regs->IFCR = (1U << (4 * (tube - 1)));
|
|
}
|
|
|
|
static inline uint16 dma_get_count(dma_dev *dev, dma_tube tube) {
|
|
return dma_channel_regs(dev, tube)->CNDTR;
|
|
}
|
|
|
|
/**
|
|
* @brief Deprecated
|
|
* STM32F1 mode flags for dma_setup_xfer(). Use dma_tube_cfg() instead.
|
|
* @see dma_tube_cfg()
|
|
*/
|
|
typedef enum dma_mode_flags {
|
|
DMA_MEM_2_MEM = 1 << 14, /**< Memory to memory mode */
|
|
DMA_MINC_MODE = 1 << 7, /**< Auto-increment memory address */
|
|
DMA_PINC_MODE = 1 << 6, /**< Auto-increment peripheral address */
|
|
DMA_CIRC_MODE = 1 << 5, /**< Circular mode */
|
|
DMA_FROM_MEM = 1 << 4, /**< Read from memory to peripheral */
|
|
DMA_TRNS_ERR = 1 << 3, /**< Interrupt on transfer error */
|
|
DMA_HALF_TRNS = 1 << 2, /**< Interrupt on half-transfer */
|
|
DMA_TRNS_CMPLT = 1 << 1 /**< Interrupt on transfer completion */
|
|
} dma_mode_flags;
|
|
|
|
/* Keep this around for backwards compatibility, but it's deprecated.
|
|
* New code should use dma_tube_cfg() instead.
|
|
*
|
|
* (It's not possible to fully configure a DMA stream on F2 with just
|
|
* this information, so this interface is too tied to the F1.) */
|
|
void dma_setup_transfer(dma_dev *dev,
|
|
dma_channel channel,
|
|
__IO void *peripheral_address,
|
|
dma_xfer_size peripheral_size,
|
|
__IO void *memory_address,
|
|
dma_xfer_size memory_size,
|
|
uint32 mode);
|
|
|
|
#ifdef __cplusplus
|
|
} // extern "C"
|
|
#endif
|
|
|
|
#endif
|