460 lines
17 KiB
C
460 lines
17 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file spi.h
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* @author Marti Bolivar <mbolivar@leaflabs.com>
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* @brief Serial Peripheral Interface (SPI) and Integrated
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* Interchip Sound (I2S) peripheral support.
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*
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* I2S support is currently limited to register maps and bit definitions.
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*/
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#ifndef _SPI_H_
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#define _SPI_H_
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#include "libmaple_types.h"
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#include "rcc.h"
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#include "nvic.h"
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#include "gpio.h"
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#include "util.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Register maps
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*/
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/** SPI register map type. */
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typedef struct spi_reg_map {
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__io uint32 CR1; /**< Control register 1 */
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__io uint32 CR2; /**< Control register 2 */
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__io uint32 SR; /**< Status register */
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__io uint32 DR; /**< Data register */
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__io uint32 CRCPR; /**< CRC polynomial register */
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__io uint32 RXCRCR; /**< RX CRC register */
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__io uint32 TXCRCR; /**< TX CRC register */
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__io uint32 I2SCFGR; /**< I2S configuration register */
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__io uint32 I2SPR; /**< I2S prescaler register */
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} spi_reg_map;
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/** SPI1 register map base pointer */
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#define SPI1_BASE ((struct spi_reg_map*)0x40013000)
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/** SPI2 register map base pointer */
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#define SPI2_BASE ((struct spi_reg_map*)0x40003800)
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/** SPI3 register map base pointer */
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#define SPI3_BASE ((struct spi_reg_map*)0x40003C00)
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/*
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* Register bit definitions
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*/
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/* Control register 1 */
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#define SPI_CR1_BIDIMODE_BIT 15
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#define SPI_CR1_BIDIOE_BIT 14
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#define SPI_CR1_CRCEN_BIT 13
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#define SPI_CR1_CRCNEXT_BIT 12
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#define SPI_CR1_DFF_BIT 11
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#define SPI_CR1_RXONLY_BIT 10
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#define SPI_CR1_SSM_BIT 9
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#define SPI_CR1_SSI_BIT 8
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#define SPI_CR1_LSBFIRST_BIT 7
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#define SPI_CR1_SPE_BIT 6
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#define SPI_CR1_MSTR_BIT 2
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#define SPI_CR1_CPOL_BIT 1
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#define SPI_CR1_CPHA_BIT 0
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#define SPI_CR1_BIDIMODE BIT(SPI_CR1_BIDIMODE_BIT)
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#define SPI_CR1_BIDIMODE_2_LINE (0x0 << SPI_CR1_BIDIMODE_BIT)
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#define SPI_CR1_BIDIMODE_1_LINE (0x1 << SPI_CR1_BIDIMODE_BIT)
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#define SPI_CR1_BIDIOE BIT(SPI_CR1_BIDIOE_BIT)
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#define SPI_CR1_CRCEN BIT(SPI_CR1_CRCEN_BIT)
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#define SPI_CR1_CRCNEXT BIT(SPI_CR1_CRCNEXT_BIT)
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#define SPI_CR1_DFF BIT(SPI_CR1_DFF_BIT)
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#define SPI_CR1_DFF_8_BIT (0x0 << SPI_CR1_DFF_BIT)
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#define SPI_CR1_DFF_16_BIT (0x1 << SPI_CR1_DFF_BIT)
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#define SPI_CR1_RXONLY BIT(SPI_CR1_RXONLY_BIT)
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#define SPI_CR1_SSM BIT(SPI_CR1_SSM_BIT)
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#define SPI_CR1_SSI BIT(SPI_CR1_SSI_BIT)
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#define SPI_CR1_LSBFIRST BIT(SPI_CR1_LSBFIRST_BIT)
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#define SPI_CR1_SPE BIT(SPI_CR1_SPE_BIT)
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#define SPI_CR1_BR (0x7 << 3)
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#define SPI_CR1_BR_PCLK_DIV_2 (0x0 << 3)
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#define SPI_CR1_BR_PCLK_DIV_4 (0x1 << 3)
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#define SPI_CR1_BR_PCLK_DIV_8 (0x2 << 3)
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#define SPI_CR1_BR_PCLK_DIV_16 (0x3 << 3)
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#define SPI_CR1_BR_PCLK_DIV_32 (0x4 << 3)
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#define SPI_CR1_BR_PCLK_DIV_64 (0x5 << 3)
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#define SPI_CR1_BR_PCLK_DIV_128 (0x6 << 3)
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#define SPI_CR1_BR_PCLK_DIV_256 (0x7 << 3)
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#define SPI_CR1_MSTR BIT(SPI_CR1_MSTR_BIT)
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#define SPI_CR1_CPOL BIT(SPI_CR1_CPOL_BIT)
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#define SPI_CR1_CPOL_LOW (0x0 << SPI_CR1_CPOL_BIT)
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#define SPI_CR1_CPOL_HIGH (0x1 << SPI_CR1_CPOL_BIT)
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#define SPI_CR1_CPHA BIT(SPI_CR1_CPHA_BIT)
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/* Control register 2 */
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/* RM0008-ism: SPI CR2 has "TXDMAEN" and "RXDMAEN" bits, while the
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* USARTs have CR3 "DMAR" and "DMAT" bits. */
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#define SPI_CR2_TXEIE_BIT 7
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#define SPI_CR2_RXNEIE_BIT 6
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#define SPI_CR2_ERRIE_BIT 5
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#define SPI_CR2_SSOE_BIT 2
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#define SPI_CR2_TXDMAEN_BIT 1
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#define SPI_CR2_RXDMAEN_BIT 0
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#define SPI_CR2_TXEIE BIT(SPI_CR2_TXEIE_BIT)
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#define SPI_CR2_RXNEIE BIT(SPI_CR2_RXNEIE_BIT)
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#define SPI_CR2_ERRIE BIT(SPI_CR2_ERRIE_BIT)
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#define SPI_CR2_SSOE BIT(SPI_CR2_SSOE_BIT)
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#define SPI_CR2_TXDMAEN BIT(SPI_CR2_TXDMAEN_BIT)
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#define SPI_CR2_RXDMAEN BIT(SPI_CR2_RXDMAEN_BIT)
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/* Status register */
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#define SPI_SR_BSY_BIT 7
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#define SPI_SR_OVR_BIT 6
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#define SPI_SR_MODF_BIT 5
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#define SPI_SR_CRCERR_BIT 4
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#define SPI_SR_UDR_BIT 3
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#define SPI_SR_CHSIDE_BIT 2
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#define SPI_SR_TXE_BIT 1
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#define SPI_SR_RXNE_BIT 0
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#define SPI_SR_BSY BIT(SPI_SR_BSY_BIT)
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#define SPI_SR_OVR BIT(SPI_SR_OVR_BIT)
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#define SPI_SR_MODF BIT(SPI_SR_MODF_BIT)
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#define SPI_SR_CRCERR BIT(SPI_SR_CRCERR_BIT)
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#define SPI_SR_UDR BIT(SPI_SR_UDR_BIT)
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#define SPI_SR_CHSIDE BIT(SPI_SR_CHSIDE_BIT)
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#define SPI_SR_CHSIDE_LEFT (0x0 << SPI_SR_CHSIDE_BIT)
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#define SPI_SR_CHSIDE_RIGHT (0x1 << SPI_SR_CHSIDE_BIT)
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#define SPI_SR_TXE BIT(SPI_SR_TXE_BIT)
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#define SPI_SR_RXNE BIT(SPI_SR_RXNE_BIT)
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/* I2S configuration register */
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/* RM0008-ism: CR1 has "CPOL", I2SCFGR has "CKPOL". */
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#define SPI_I2SCFGR_I2SMOD_BIT 11
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#define SPI_I2SCFGR_I2SE_BIT 10
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#define SPI_I2SCFGR_PCMSYNC_BIT 7
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#define SPI_I2SCFGR_CKPOL_BIT 3
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#define SPI_I2SCFGR_CHLEN_BIT 0
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#define SPI_I2SCFGR_I2SMOD BIT(SPI_I2SCFGR_I2SMOD_BIT)
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#define SPI_I2SCFGR_I2SMOD_SPI (0x0 << SPI_I2SCFGR_I2SMOD_BIT)
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#define SPI_I2SCFGR_I2SMOD_I2S (0x1 << SPI_I2SCFGR_I2SMOD_BIT)
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#define SPI_I2SCFGR_I2SE BIT(SPI_I2SCFGR_I2SE_BIT)
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#define SPI_I2SCFGR_I2SCFG (0x3 << 8)
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#define SPI_I2SCFGR_I2SCFG_SLAVE_TX (0x0 << 8)
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#define SPI_I2SCFGR_I2SCFG_SLAVE_RX (0x1 << 8)
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#define SPI_I2SCFGR_I2SCFG_MASTER_TX (0x2 << 8)
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#define SPI_I2SCFGR_I2SCFG_MASTER_RX (0x3 << 8)
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#define SPI_I2SCFGR_PCMSYNC BIT(SPI_I2SCFGR_PCMSYNC_BIT)
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#define SPI_I2SCFGR_PCMSYNC_SHORT (0x0 << SPI_I2SCFGR_PCMSYNC_BIT)
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#define SPI_I2SCFGR_PCMSYNC_LONG (0x1 << SPI_I2SCFGR_PCMSYNC_BIT)
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#define SPI_I2SCFGR_I2SSTD (0x3 << 4)
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#define SPI_I2SCFGR_I2SSTD_PHILLIPS (0x0 << 4)
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#define SPI_I2SCFGR_I2SSTD_MSB (0x1 << 4)
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#define SPI_I2SCFGR_I2SSTD_LSB (0x2 << 4)
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#define SPI_I2SCFGR_I2SSTD_PCM (0x3 << 4)
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#define SPI_I2SCFGR_CKPOL BIT(SPI_I2SCFGR_CKPOL_BIT)
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#define SPI_I2SCFGR_CKPOL_LOW (0x0 << SPI_I2SCFGR_CKPOL_BIT)
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#define SPI_I2SCFGR_CKPOL_HIGH (0x1 << SPI_I2SCFGR_CKPOL_BIT)
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#define SPI_I2SCFGR_DATLEN (0x3 << 1)
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#define SPI_I2SCFGR_DATLEN_16_BIT (0x0 << 1)
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#define SPI_I2SCFGR_DATLEN_24_BIT (0x1 << 1)
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#define SPI_I2SCFGR_DATLEN_32_BIT (0x2 << 1)
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#define SPI_I2SCFGR_CHLEN BIT(SPI_I2SCFGR_CHLEN_BIT)
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#define SPI_I2SCFGR_CHLEN_16_BIT (0x0 << SPI_I2SCFGR_CHLEN_BIT)
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#define SPI_I2SCFGR_CHLEN_32_BIT (0x1 << SPI_I2SCFGR_CHLEN_BIT)
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/*
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* Devices
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*/
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/** SPI device type */
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typedef struct spi_dev {
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spi_reg_map *regs; /**< Register map */
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rcc_clk_id clk_id; /**< RCC clock information */
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nvic_irq_num irq_num; /**< NVIC interrupt number */
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} spi_dev;
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extern spi_dev *SPI1;
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extern spi_dev *SPI2;
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#ifdef STM32_HIGH_DENSITY
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extern spi_dev *SPI3;
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#endif
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#ifdef STM32F2
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extern spi_dev *SPI4;
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#endif
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/*
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* SPI Convenience functions
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*/
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void spi_init(spi_dev *dev);
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void spi_gpio_cfg(uint8 as_master,
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gpio_dev *nss_dev,
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uint8 nss_bit,
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gpio_dev *comm_dev,
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uint8 sck_bit,
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uint8 miso_bit,
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uint8 mosi_bit);
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/**
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* @brief SPI mode configuration.
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*
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* Determines a combination of clock polarity (CPOL), which determines
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* idle state of the clock line, and clock phase (CPHA), which
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* determines which clock edge triggers data capture.
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*/
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typedef enum spi_mode {
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SPI_MODE_0, /**< Clock line idles low (0), data capture on first
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clock transition. */
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SPI_MODE_1, /**< Clock line idles low (0), data capture on second
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clock transition */
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SPI_MODE_2, /**< Clock line idles high (1), data capture on first
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clock transition. */
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SPI_MODE_3 /**< Clock line idles high (1), data capture on
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second clock transition. */
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} spi_mode;
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/**
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* @brief SPI baud rate configuration, as a divisor of f_PCLK, the
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* PCLK clock frequency.
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*/
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typedef enum spi_baud_rate {
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SPI_BAUD_PCLK_DIV_2 = SPI_CR1_BR_PCLK_DIV_2, /**< f_PCLK/2 */
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SPI_BAUD_PCLK_DIV_4 = SPI_CR1_BR_PCLK_DIV_4, /**< f_PCLK/4 */
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SPI_BAUD_PCLK_DIV_8 = SPI_CR1_BR_PCLK_DIV_8, /**< f_PCLK/8 */
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SPI_BAUD_PCLK_DIV_16 = SPI_CR1_BR_PCLK_DIV_16, /**< f_PCLK/16 */
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SPI_BAUD_PCLK_DIV_32 = SPI_CR1_BR_PCLK_DIV_32, /**< f_PCLK/32 */
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SPI_BAUD_PCLK_DIV_64 = SPI_CR1_BR_PCLK_DIV_64, /**< f_PCLK/64 */
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SPI_BAUD_PCLK_DIV_128 = SPI_CR1_BR_PCLK_DIV_128, /**< f_PCLK/128 */
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SPI_BAUD_PCLK_DIV_256 = SPI_CR1_BR_PCLK_DIV_256, /**< f_PCLK/256 */
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} spi_baud_rate;
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/**
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* @brief SPI initialization flags.
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* @see spi_master_enable()
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* @see spi_slave_enable()
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*/
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typedef enum spi_cfg_flag {
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SPI_BIDIMODE = SPI_CR1_BIDIMODE, /**< Bidirectional mode enable */
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SPI_BIDIOE = SPI_CR1_BIDIOE, /**< Output enable in bidirectional
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mode */
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SPI_CRCEN = SPI_CR1_CRCEN, /**< Cyclic redundancy check (CRC)
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enable */
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SPI_DFF_8_BIT = SPI_CR1_DFF_8_BIT, /**< 8-bit data frame format (this is
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the default) */
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SPI_DFF_16_BIT = SPI_CR1_DFF_16_BIT, /**< 16-bit data frame format */
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SPI_RX_ONLY = SPI_CR1_RXONLY, /**< Receive only */
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SPI_SW_SLAVE = SPI_CR1_SSM, /**< Software slave management */
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SPI_SOFT_SS = SPI_CR1_SSI, /**< Software (internal) slave
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select. This flag only has an
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effect when used in combination
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with SPI_SW_SLAVE. */
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SPI_FRAME_LSB = SPI_CR1_LSBFIRST, /**< LSB-first (little-endian) frame
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format */
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SPI_FRAME_MSB = 0, /**< MSB-first (big-endian) frame
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format (this is the default) */
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} spi_cfg_flag;
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void spi_master_enable(spi_dev *dev,
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spi_baud_rate baud,
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spi_mode mode,
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uint32 flags);
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void spi_slave_enable(spi_dev *dev,
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spi_mode mode,
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uint32 flags);
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uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len);
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void spi_foreach(void (*fn)(spi_dev (*dev)));
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void spi_peripheral_enable(spi_dev *dev);
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void spi_peripheral_disable(spi_dev *dev);
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void spi_tx_dma_enable(spi_dev *dev);
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void spi_tx_dma_disable(spi_dev *dev);
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void spi_rx_dma_enable(spi_dev *dev);
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void spi_rx_dma_disable(spi_dev *dev);
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/**
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* @brief Determine if a SPI peripheral is enabled.
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* @param dev SPI device
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* @return True, if and only if dev's peripheral is enabled.
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*/
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static inline uint8 spi_is_enabled(spi_dev *dev) {
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return dev->regs->CR1 & SPI_CR1_SPE_BIT;
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}
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/**
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* @brief Disable all SPI peripherals
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*/
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static inline void spi_peripheral_disable_all(void) {
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spi_foreach(spi_peripheral_disable);
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}
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/** Available SPI interrupts */
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typedef enum spi_interrupt {
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SPI_TXE_INTERRUPT = SPI_CR2_TXEIE, /**< TX buffer empty interrupt */
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SPI_RXNE_INTERRUPT = SPI_CR2_RXNEIE, /**< RX buffer not empty interrupt */
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SPI_ERR_INTERRUPT = SPI_CR2_ERRIE /**<
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* Error interrupt (CRC, overrun,
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* and mode fault errors for SPI;
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* underrun, overrun errors for I2S)
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*/
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} spi_interrupt;
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/**
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* @brief Mask for all spi_interrupt values
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* @see spi_interrupt
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*/
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#define SPI_INTERRUPTS_ALL (SPI_TXE_INTERRUPT | \
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SPI_RXNE_INTERRUPT | \
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SPI_ERR_INTERRUPT)
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/**
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* @brief Enable SPI interrupt requests
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* @param dev SPI device
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* @param interrupt_flags Bitwise OR of spi_interrupt values to enable
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* @see spi_interrupt
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*/
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static inline void spi_irq_enable(spi_dev *dev, uint32 interrupt_flags) {
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dev->regs->CR2 |= interrupt_flags;
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nvic_irq_enable(dev->irq_num);
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}
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/**
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* @brief Disable SPI interrupt requests
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* @param dev SPI device
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* @param interrupt_flags Bitwise OR of spi_interrupt values to disable
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* @see spi_interrupt
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*/
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static inline void spi_irq_disable(spi_dev *dev, uint32 interrupt_flags) {
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dev->regs->CR2 &= ~interrupt_flags;
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}
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/**
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* @brief Get the data frame format flags with which a SPI port is
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* configured.
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* @param dev SPI device whose data frame format to get.
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* @return SPI_DFF_8_BIT, if dev has an 8-bit data frame format.
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* Otherwise, SPI_DFF_16_BIT.
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*/
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static inline spi_cfg_flag spi_dff(spi_dev *dev) {
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return ((dev->regs->CR1 & SPI_CR1_DFF) == SPI_CR1_DFF_8_BIT ?
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SPI_DFF_8_BIT :
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SPI_DFF_16_BIT);
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}
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/**
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* @brief Determine whether the device's peripheral receive (RX)
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* register is empty.
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* @param dev SPI device
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* @return true, iff dev's RX register is empty.
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*/
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static inline uint8 spi_is_rx_nonempty(spi_dev *dev) {
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return dev->regs->SR & SPI_SR_RXNE;
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}
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/**
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* @brief Retrieve the contents of the device's peripheral receive
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* (RX) register.
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*
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* You may only call this function when the RX register is nonempty.
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* Calling this function clears the contents of the RX register.
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*
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* @param dev SPI device
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* @return Contents of dev's peripheral RX register
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* @see spi_is_rx_reg_nonempty()
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*/
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static inline uint16 spi_rx_reg(spi_dev *dev) {
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return (uint16)dev->regs->DR;
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}
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/**
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* @brief Determine whether the device's peripheral transmit (TX)
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* register is empty.
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* @param dev SPI device
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* @return true, iff dev's TX register is empty.
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*/
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static inline uint8 spi_is_tx_empty(spi_dev *dev) {
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return dev->regs->SR & SPI_SR_TXE;
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}
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/**
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* @brief Load a value into the device's peripheral transmit (TX) register.
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*
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* You may only call this function when the TX register is empty.
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* Calling this function loads val into the peripheral's TX register.
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* If the device is properly configured, this will initiate a
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* transmission, the completion of which will cause the TX register to
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* be empty again.
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*
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* @param dev SPI device
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* @param val Value to load into the TX register. If the SPI data
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* frame format is 8 bit, the value must be right-aligned.
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* @see spi_is_tx_reg_empty()
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* @see spi_init()
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* @see spi_master_enable()
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* @see spi_slave_enable()
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*/
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static inline void spi_tx_reg(spi_dev *dev, uint16 val) {
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dev->regs->DR = val;
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}
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/**
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* @brief Determine whether the device's peripheral busy (SPI_SR_BSY)
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* flag is set.
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* @param dev SPI device
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* @return true, iff dev's BSY flag is set.
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*/
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static inline uint8 spi_is_busy(spi_dev *dev) {
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return dev->regs->SR & SPI_SR_BSY;
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}
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/*
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* I2S convenience functions (TODO)
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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