67 lines
2.1 KiB
Makefile
67 lines
2.1 KiB
Makefile
# Standard things
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sp := $(sp).x
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dirstack_$(sp) := $(d)
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d := $(dir)
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BUILDDIRS += $(BUILD_PATH)/$(d)
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# Add board directory and MCU-specific directory to BUILDDIRS. These
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# are in subdirectories, but they're logically part of the Wirish
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# submodule.
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ifeq ($(MCU_SERIES), stm32f3)
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WIRISH_BOARD_PATH := boards/$(MCU_F3_LINE)
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else
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WIRISH_BOARD_PATH := boards/$(BOARD)
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endif
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BUILDDIRS += $(BUILD_PATH)/$(d)/$(WIRISH_BOARD_PATH)
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BUILDDIRS += $(BUILD_PATH)/$(d)/$(MCU_SERIES)
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# Safe includes for Wirish.
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WIRISH_INCLUDES := -I$(d)/include -I$(d)/$(WIRISH_BOARD_PATH)/include
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# Local flags. Add -I$(d) to allow for private includes.
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CFLAGS_$(d) := $(LIBMAPLE_INCLUDES) $(WIRISH_INCLUDES) -I$(d)
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# Local rules and targets
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sSRCS_$(d) := start.S
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cSRCS_$(d) := start_c.c
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cSRCS_$(d) += syscalls.c
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cSRCS_$(d) += $(MCU_SERIES)/util_hooks.c
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cppSRCS_$(d) := boards.cpp
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cppSRCS_$(d) += cxxabi-compat.cpp
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cppSRCS_$(d) += ext_interrupts.cpp
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cppSRCS_$(d) += HardwareSerial.cpp
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cppSRCS_$(d) += HardwareTimer.cpp
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cppSRCS_$(d) += Print.cpp
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cppSRCS_$(d) += pwm.cpp
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ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),stm32f1 stm32f3)) # TODO port USB serial to F2
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cppSRCS_$(d) += usb_serial.cpp
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cppSRCS_$(d) += HardwareSPI.cpp
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endif
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cppSRCS_$(d) += wirish_analog.cpp
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cppSRCS_$(d) += wirish_digital.cpp
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cppSRCS_$(d) += wirish_math.cpp
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cppSRCS_$(d) += wirish_shift.cpp
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cppSRCS_$(d) += wirish_time.cpp
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cppSRCS_$(d) += $(MCU_SERIES)/boards_setup.cpp
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cppSRCS_$(d) += $(MCU_SERIES)/wirish_digital.cpp
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cppSRCS_$(d) += $(MCU_SERIES)/wirish_debug.cpp
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cppSRCS_$(d) += $(WIRISH_BOARD_PATH)/board.cpp
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sFILES_$(d) := $(sSRCS_$(d):%=$(d)/%)
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cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%)
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cppFILES_$(d) := $(cppSRCS_$(d):%=$(d)/%)
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OBJS_$(d) := $(sFILES_$(d):%.S=$(BUILD_PATH)/%.o) \
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$(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) \
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$(cppFILES_$(d):%.cpp=$(BUILD_PATH)/%.o)
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DEPS_$(d) := $(OBJS_$(d):%.o=%.d)
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$(OBJS_$(d)): TGT_CFLAGS := $(CFLAGS_$(d))
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TGT_BIN += $(OBJS_$(d))
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# Standard things
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-include $(DEPS_$(d))
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d := $(dirstack_$(sp))
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sp := $(basename $(sp))
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