347 lines
14 KiB
C
347 lines
14 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Bryan Newbold.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file fsmc.h
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* @brief Flexible static memory controller support.
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*/
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/*
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* See ../notes/fsmc.txt for more info
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*/
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/**
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* @file fsmc.h
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*/
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#ifndef _FSMC_H_
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#define _FSMC_H_
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#include <libmaple\util.h>
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#include "libmaple_types.h"
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#ifdef __cplusplus
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extern "C"{
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#endif
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#ifdef STM32_HIGH_DENSITY
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/*
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* Register maps and devices
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*/
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/** FSMC register map type */
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typedef struct fsmc_reg_map {
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__io uint32 BCR1; /**< SRAM/NOR-Flash chip-select control register 1 */
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__io uint32 BTR1; /**< SRAM/NOR-Flash chip-select timing register 1 */
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__io uint32 BCR2; /**< SRAM/NOR-Flash chip-select control register 2 */
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__io uint32 BTR2; /**< SRAM/NOR-Flash chip-select timing register 2 */
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__io uint32 BCR3; /**< SRAM/NOR-Flash chip-select control register 3 */
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__io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
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__io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
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__io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
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const uint32 RESERVED1[16]; /**< Reserved */
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__io uint32 PCR2; /**< PC Card/NAND Flash control register 2 */
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__io uint32 SR2; /**< FIFO status and interrupt register 2 */
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__io uint32 PMEM2; /**< Common memory space timing register 2 */
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__io uint32 PATT2; /**< Attribute memory space timing register 2 */
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const uint32 RESERVED2; /**< Reserved */
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__io uint32 ECCR2; /**< ECC result register 2 */
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const uint32 RESERVED3[2]; /**< Reserved */
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__io uint32 PCR3; /**< PC Card/NAND Flash control register 3 */
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__io uint32 SR3; /**< FIFO status and interrupt register 3 */
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__io uint32 PMEM3; /**< Common memory space timing register 3 */
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__io uint32 PATT3; /**< Attribute memory space timing register 3 */
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const uint32 RESERVED4; /**< Reserved */
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__io uint32 ECCR3; /**< ECC result register 3 */
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const uint32 RESERVED5[2]; /**< Reserved */
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__io uint32 PCR4; /**< PC Card/NAND Flash control register 4 */
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__io uint32 SR4; /**< FIFO status and interrupt register 4 */
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__io uint32 PMEM4; /**< Common memory space timing register 4 */
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__io uint32 PATT4; /**< Attribute memory space timing register 4 */
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__io uint32 PIO4; /**< I/O space timing register 4 */
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const uint32 RESERVED6[20]; /**< Reserved */
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__io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
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const uint32 RESERVED7; /**< Reserved */
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__io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
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const uint32 RESERVED8; /**< Reserved */
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__io uint32 BWTR3; /**< SRAM/NOR-Flash write timing register 3 */
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const uint32 RESERVED9; /**< Reserved */
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__io uint32 BWTR4; /**< SRAM/NOR-Flash write timing register 4 */
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} __attribute__((packed)) fsmc_reg_map;
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#define __FSMCB 0xA0000000
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/** FSMC register map base pointer */
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#define FSMC_BASE ((struct fsmc_reg_map*)__FSMCB)
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/** FSMC NOR/PSRAM register map type */
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typedef struct fsmc_nor_psram_reg_map {
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__io uint32 BCR; /**< Chip-select control register */
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__io uint32 BTR; /**< Chip-select timing register */
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const uint32 RESERVED[63]; /**< Reserved */
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__io uint32 BWTR; /**< Write timing register */
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} fsmc_nor_psram_reg_map;
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/** FSMC NOR/PSRAM base pointer 1 */
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#define FSMC_NOR_PSRAM1_BASE ((struct fsmc_nor_psram_reg_map*)__FSMCB)
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/** FSMC NOR/PSRAM base pointer 2 */
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#define FSMC_NOR_PSRAM2_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x8))
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/** FSMC NOR/PSRAM base pointer 3 */
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#define FSMC_NOR_PSRAM3_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x10))
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/** FSMC NOR/PSRAM base pointer 4 */
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#define FSMC_NOR_PSRAM4_BASE ((struct fsmc_nor_psram_reg_map*)(__FSMCB + 0x18))
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/*
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* Register bit definitions
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*/
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/* NOR/PSRAM chip-select control registers */
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#define FSMC_BCR_CBURSTRW_BIT 19
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#define FSMC_BCR_ASYNCWAIT_BIT 15
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#define FSMC_BCR_EXTMOD_BIT 14
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#define FSMC_BCR_WAITEN_BIT 13
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#define FSMC_BCR_WREN_BIT 12
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#define FSMC_BCR_WAITCFG_BIT 11
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#define FSMC_BCR_WRAPMOD_BIT 10
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#define FSMC_BCR_WAITPOL_BIT 9
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#define FSMC_BCR_BURSTEN_BIT 8
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#define FSMC_BCR_FACCEN_BIT 6
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#define FSMC_BCR_MUXEN_BIT 1
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#define FSMC_BCR_MBKEN_BIT 0
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#define FSMC_BCR_CBURSTRW BIT(FSMC_BCR_CBURSTRW_BIT)
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#define FSMC_BCR_ASYNCWAIT BIT(FSMC_BCR_ASYNCWAIT_BIT)
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#define FSMC_BCR_EXTMOD BIT(FSMC_BCR_EXTMOD_BIT)
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#define FSMC_BCR_WAITEN BIT(FSMC_BCR_WAITEN_BIT)
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#define FSMC_BCR_WREN BIT(FSMC_BCR_WREN_BIT)
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#define FSMC_BCR_WAITCFG BIT(FSMC_BCR_WAITCFG_BIT)
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#define FSMC_BCR_WRAPMOD BIT(FSMC_BCR_WRAPMOD_BIT)
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#define FSMC_BCR_WAITPOL BIT(FSMC_BCR_WAITPOL_BIT)
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#define FSMC_BCR_BURSTEN BIT(FSMC_BCR_BURSTEN_BIT)
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#define FSMC_BCR_FACCEN BIT(FSMC_BCR_FACCEN_BIT)
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#define FSMC_BCR_MWID (0x3 << 4)
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#define FSMC_BCR_MWID_8BITS (0x0 << 4)
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#define FSMC_BCR_MWID_16BITS (0x1 << 4)
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#define FSMC_BCR_MTYP (0x3 << 2)
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#define FSMC_BCR_MTYP_SRAM (0x0 << 2)
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#define FSMC_BCR_MTYP_PSRAM (0x1 << 2)
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#define FSMC_BCR_MTYP_NOR_FLASH (0x2 << 2)
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#define FSMC_BCR_MUXEN BIT(FSMC_BCR_MUXEN_BIT)
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#define FSMC_BCR_MBKEN BIT(FSMC_BCR_MBKEN_BIT)
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/* SRAM/NOR-Flash chip-select timing registers */
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#define FSMC_BTR_ACCMOD (0x3 << 28)
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#define FSMC_BTR_ACCMOD_A (0x0 << 28)
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#define FSMC_BTR_ACCMOD_B (0x1 << 28)
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#define FSMC_BTR_ACCMOD_C (0x2 << 28)
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#define FSMC_BTR_ACCMOD_D (0x3 << 28)
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#define FSMC_BTR_DATLAT (0xF << 24)
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#define FSMC_BTR_CLKDIV (0xF << 20)
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#define FSMC_BTR_BUSTURN (0xF << 16)
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#define FSMC_BTR_DATAST (0xFF << 8)
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#define FSMC_BTR_ADDHLD (0xF << 4)
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#define FSMC_BTR_ADDSET 0xF
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#define FSMC_BTR_DATLAT_(x) ((x<<24)&FSMC_BTR_DATLAT)
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#define FSMC_BTR_CLKDIV_(x) ((x<<20)&FSMC_BTR_CLKDIV)
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#define FSMC_BTR_BUSTURN_(x) ((x<<16)&FSMC_BTR_BUSTURN)
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#define FSMC_BTR_DATAST_(x) ((x<<8)&FSMC_BTR_DATAST)
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#define FSMC_BTR_ADDHLD_(x) ((x<<4)&FSMC_BTR_ADDHLD)
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#define FSMC_BTR_ADDSET_(x) ((x<<0)&FSMC_BTR_ADDSET)
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/* SRAM/NOR-Flash write timing registers */
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#define FSMC_BWTR_ACCMOD (0x3 << 28)
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#define FSMC_BWTR_ACCMOD_A (0x0 << 28)
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#define FSMC_BWTR_ACCMOD_B (0x1 << 28)
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#define FSMC_BWTR_ACCMOD_C (0x2 << 28)
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#define FSMC_BWTR_ACCMOD_D (0x3 << 28)
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#define FSMC_BWTR_DATLAT (0xF << 24)
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#define FSMC_BWTR_CLKDIV (0xF << 20)
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#define FSMC_BWTR_DATAST (0xFF << 8)
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#define FSMC_BWTR_ADDHLD (0xF << 4)
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#define FSMC_BWTR_ADDSET 0xF
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/* NAND Flash/PC Card controller registers */
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#define FSMC_PCR_ECCEN_BIT 6
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#define FSMC_PCR_PTYP_BIT 3
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#define FSMC_PCR_PBKEN_BIT 2
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#define FSMC_PCR_PWAITEN_BIT 1
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#define FSMC_PCR_ECCPS (0x7 << 17)
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#define FSMC_PCR_ECCPS_256B (0x0 << 17)
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#define FSMC_PCR_ECCPS_512B (0x1 << 17)
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#define FSMC_PCR_ECCPS_1024B (0x2 << 17)
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#define FSMC_PCR_ECCPS_2048B (0x3 << 17)
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#define FSMC_PCR_ECCPS_4096B (0x4 << 17)
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#define FSMC_PCR_ECCPS_8192B (0x5 << 17)
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#define FSMC_PCR_TAR (0xF << 13)
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#define FSMC_PCR_TCLR (0xF << 9)
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#define FSMC_PCR_ECCEN BIT(FSMC_PCR_ECCEN_BIT)
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#define FSMC_PCR_PWID (0x3 << 4)
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#define FSMC_PCR_PWID_8BITS (0x0 << 4)
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#define FSMC_PCR_PWID_16BITS (0x1 << 4)
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#define FSMC_PCR_PTYP BIT(FSMC_PCR_PTYP_BIT)
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#define FSMC_PCR_PTYP_PC_CF_PCMCIA (0x0 << FSMC_PCR_PTYP_BIT)
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#define FSMC_PCR_PTYP_NAND (0x1 << FSMC_PCR_PTYP_BIT)
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#define FSMC_PCR_PBKEN BIT(FSMC_PCR_PBKEN_BIT)
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#define FSMC_PCR_PWAITEN BIT(FSMC_PCR_PWAITEN_BIT)
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/* FIFO status and interrupt registers */
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#define FSMC_SR_FEMPT_BIT 6
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#define FSMC_SR_IFEN_BIT 5
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#define FSMC_SR_ILEN_BIT 4
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#define FSMC_SR_IREN_BIT 3
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#define FSMC_SR_IFS_BIT 2
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#define FSMC_SR_ILS_BIT 1
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#define FSMC_SR_IRS_BIT 0
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#define FSMC_SR_FEMPT BIT(FSMC_SR_FEMPT_BIT)
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#define FSMC_SR_IFEN BIT(FSMC_SR_IFEN_BIT)
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#define FSMC_SR_ILEN BIT(FSMC_SR_ILEN_BIT)
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#define FSMC_SR_IREN BIT(FSMC_SR_IREN_BIT)
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#define FSMC_SR_IFS BIT(FSMC_SR_IFS_BIT)
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#define FSMC_SR_ILS BIT(FSMC_SR_ILS_BIT)
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#define FSMC_SR_IRS BIT(FSMC_SR_IRS_BIT)
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/* Common memory space timing registers */
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#define FSMC_PMEM_MEMHIZ (0xFF << 24)
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#define FSMC_PMEM_MEMHOLD (0xFF << 16)
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#define FSMC_PMEM_MEMWAIT (0xFF << 8)
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#define FSMC_PMEM_MEMSET 0xFF
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/* Attribute memory space timing registers */
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#define FSMC_PATT_ATTHIZ (0xFF << 24)
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#define FSMC_PATT_ATTHOLD (0xFF << 16)
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#define FSMC_PATT_ATTWAIT (0xFF << 8)
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#define FSMC_PATT_ATTSET 0xFF
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/* I/O space timing register 4 */
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#define FSMC_PIO_IOHIZ (0xFF << 24)
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#define FSMC_PIO_IOHOLD (0xFF << 16)
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#define FSMC_PIO_IOWAIT (0xFF << 8)
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#define FSMC_PIO_IOSET 0xFF
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/*
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* Memory bank boundary addresses
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*/
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/** Pointer to base address of FSMC memory bank 1 (split into 4
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* regions, each supporting 1 NOR Flash, SRAM, or PSRAM chip) */
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#define FSMC_BANK1 ((void*)0x60000000)
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/** Pointer to base address of FSMC memory bank 1, region 1 (for NOR/PSRAM) */
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#define FSMC_NOR_PSRAM_REGION1 FSMC_BANK1
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/** Pointer to base address of FSMC memory bank 1, region 2 (for NOR/PSRAM) */
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#define FSMC_NOR_PSRAM_REGION2 ((void*)0x64000000)
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/** Pointer to base address of FSMC memory bank 1, region 3 (for NOR/PSRAM) */
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#define FSMC_NOR_PSRAM_REGION3 ((void*)0x68000000)
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/** Pointer to base address of FSMC memory bank 1, region 4 (for NOR/PSRAM) */
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#define FSMC_NOR_PSRAM_REGION4 ((void*)0x6C000000)
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/** Pointer to base address of FSMC memory bank 2 (for NAND Flash) */
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#define FSMC_BANK2 ((void*)0x70000000)
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/** Pointer to base address of FSMC memory bank 3 (for NAND Flash) */
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#define FSMC_BANK3 ((void*)0x80000000)
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/** Pointer to base address of FSMC memory bank 4 (for PC card devices */
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#define FSMC_BANK4 ((void*)0x90000000)
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/*
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* SRAM/NOR Flash routines
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*/
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extern volatile uint16_t * fsmcData;
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extern volatile uint16_t * fsmcCommand;
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void fsmc_lcd_init(void);
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static inline void fsmc_nor_psram_set_BCR(fsmc_nor_psram_reg_map *regs, uint32_t bcr) {
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regs->BCR = bcr;
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}
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static inline void fsmc_nor_psram_set_BTR(fsmc_nor_psram_reg_map *regs, uint32_t btr) {
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regs->BTR = btr;
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}
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static inline void fsmc_nor_psram_bank_enable(fsmc_nor_psram_reg_map *regs) {
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regs->BCR |= FSMC_BCR_MBKEN;
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}
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static inline void fsmc_nor_psram_bank_disable(fsmc_nor_psram_reg_map *regs) {
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regs->BCR ^= FSMC_BCR_MBKEN;
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}
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/**
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* Set the DATAST bits in the given NOR/PSRAM register map's
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* chip-select timing register (FSMC_BTR).
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*
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* @param regs NOR Flash/PSRAM register map whose chip-select timing
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* register to set.
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* @param datast Value to use for DATAST bits.
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*/
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static inline void fsmc_nor_psram_set_datast(fsmc_nor_psram_reg_map *regs,
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uint8 datast) {
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regs->BTR &= ~FSMC_BTR_DATAST;
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regs->BTR |= datast << 8;
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}
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/**
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* Set the ADDHLD bits in the given NOR/PSRAM register map's chip
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* select timing register (FSMC_BTRx).
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*
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* @param regs NOR Flash/PSRAM register map whose chip-select timing
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* register to set.
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* @param addset Value to use for ADDSET bits.
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*/
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static inline void fsmc_nor_psram_set_addset(fsmc_nor_psram_reg_map *regs,
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uint8 addset) {
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regs->BTR &= ~FSMC_BTR_ADDSET;
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regs->BTR |= addset & 0xF;
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}
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#endif /* STM32_HIGH_DENSITY */
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#ifdef __cplusplus
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} /* extern "C" */
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#endif
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#endif
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