66 lines
2.8 KiB
C
66 lines
2.8 KiB
C
/******************************************************************************
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* The MIT License
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*
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* Copyright (c) 2010 Perry Hung.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*****************************************************************************/
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/**
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* @file scb.h
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* @brief System control block header
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*/
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#include "libmaple_types.h"
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#ifndef _SCB_H_
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#define _SCB_H_
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/** System control block register map type */
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typedef struct scb_reg_map {
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__io uint32 CPUID; /**< CPU ID Base Register */
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__io uint32 ICSR; /**< Interrupt Control State Register */
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__io uint32 VTOR; /**< Vector Table Offset Register */
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__io uint32 AIRCR; /**< Application Interrupt / Reset Control Register */
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__io uint32 SCR; /**< System Control Register */
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__io uint32 CCR; /**< Configuration Control Register */
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__io uint8 SHP[12]; /**< System Handlers Priority Registers
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(4-7, 8-11, 12-15) */
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__io uint32 SHCSR; /**< System Handler Control and State Register */
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__io uint32 CFSR; /**< Configurable Fault Status Register */
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__io uint32 HFSR; /**< Hard Fault Status Register */
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__io uint32 DFSR; /**< Debug Fault Status Register */
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__io uint32 MMFAR; /**< Mem Manage Address Register */
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__io uint32 BFAR; /**< Bus Fault Address Register */
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__io uint32 AFSR; /**< Auxiliary Fault Status Register */
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__io uint32 PFR[2]; /**< Processor Feature Register */
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__io uint32 DFR; /**< Debug Feature Register */
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__io uint32 ADR; /**< Auxiliary Feature Register */
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__io uint32 MMFR[4]; /**< Memory Model Feature Register */
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__io uint32 ISAR[5]; /**< ISA Feature Register */
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} scb_reg_map;
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/** System control block register map base pointer */
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#define SCB_BASE ((struct scb_reg_map*)0xE000ED00)
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#endif
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